Lines Matching +full:0 +full:xff00
20 #define RF2522 0x0000
21 #define RF2523 0x0001
22 #define RF2524 0x0002
23 #define RF2525 0x0003
24 #define RF2525E 0x0005
25 #define RF5222 0x0010
43 #define CSR_REG_BASE 0x0400
44 #define CSR_REG_SIZE 0x0100
45 #define EEPROM_BASE 0x0000
46 #define EEPROM_SIZE 0x006e
47 #define BBP_BASE 0x0000
48 #define BBP_SIZE 0x0060
49 #define RF_BASE 0x0004
50 #define RF_SIZE 0x0010
65 #define MAC_CSR0 0x0400
69 * SOFT_RESET: Software reset, 1: reset, 0: normal.
70 * BBP_RESET: Hardware reset, 1: reset, 0, release.
73 #define MAC_CSR1 0x0402
74 #define MAC_CSR1_SOFT_RESET FIELD16(0x00000001)
75 #define MAC_CSR1_BBP_RESET FIELD16(0x00000002)
76 #define MAC_CSR1_HOST_READY FIELD16(0x00000004)
79 * MAC_CSR2: STA MAC register 0.
81 #define MAC_CSR2 0x0404
82 #define MAC_CSR2_BYTE0 FIELD16(0x00ff)
83 #define MAC_CSR2_BYTE1 FIELD16(0xff00)
88 #define MAC_CSR3 0x0406
89 #define MAC_CSR3_BYTE2 FIELD16(0x00ff)
90 #define MAC_CSR3_BYTE3 FIELD16(0xff00)
95 #define MAC_CSR4 0X0408
96 #define MAC_CSR4_BYTE4 FIELD16(0x00ff)
97 #define MAC_CSR4_BYTE5 FIELD16(0xff00)
100 * MAC_CSR5: BSSID register 0.
102 #define MAC_CSR5 0x040a
103 #define MAC_CSR5_BYTE0 FIELD16(0x00ff)
104 #define MAC_CSR5_BYTE1 FIELD16(0xff00)
109 #define MAC_CSR6 0x040c
110 #define MAC_CSR6_BYTE2 FIELD16(0x00ff)
111 #define MAC_CSR6_BYTE3 FIELD16(0xff00)
116 #define MAC_CSR7 0x040e
117 #define MAC_CSR7_BYTE4 FIELD16(0x00ff)
118 #define MAC_CSR7_BYTE5 FIELD16(0xff00)
123 #define MAC_CSR8 0x0410
124 #define MAC_CSR8_MAX_FRAME_UNIT FIELD16(0x0fff)
137 #define MAC_CSR9 0x0412
138 #define MAC_CSR10 0x0414
139 #define MAC_CSR11 0x0416
140 #define MAC_CSR12 0x0418
141 #define MAC_CSR13 0x041a
142 #define MAC_CSR14 0x041c
143 #define MAC_CSR15 0x041e
144 #define MAC_CSR16 0x0420
148 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
156 #define MAC_CSR17 0x0422
157 #define MAC_CSR17_SET_STATE FIELD16(0x0001)
158 #define MAC_CSR17_BBP_DESIRE_STATE FIELD16(0x0006)
159 #define MAC_CSR17_RF_DESIRE_STATE FIELD16(0x0018)
160 #define MAC_CSR17_BBP_CURR_STATE FIELD16(0x0060)
161 #define MAC_CSR17_RF_CURR_STATE FIELD16(0x0180)
162 #define MAC_CSR17_PUT_TO_SLEEP FIELD16(0x0200)
170 #define MAC_CSR18 0x0424
171 #define MAC_CSR18_DELAY_AFTER_BEACON FIELD16(0x00ff)
172 #define MAC_CSR18_BEACONS_BEFORE_WAKEUP FIELD16(0x7f00)
173 #define MAC_CSR18_AUTO_WAKE FIELD16(0x8000)
178 * MAC_CSR19_DIRx: GPIO direction: 0 = input; 1 = output
180 #define MAC_CSR19 0x0426
181 #define MAC_CSR19_VAL0 FIELD16(0x0001)
182 #define MAC_CSR19_VAL1 FIELD16(0x0002)
183 #define MAC_CSR19_VAL2 FIELD16(0x0004)
184 #define MAC_CSR19_VAL3 FIELD16(0x0008)
185 #define MAC_CSR19_VAL4 FIELD16(0x0010)
186 #define MAC_CSR19_VAL5 FIELD16(0x0020)
187 #define MAC_CSR19_VAL6 FIELD16(0x0040)
188 #define MAC_CSR19_VAL7 FIELD16(0x0080)
189 #define MAC_CSR19_DIR0 FIELD16(0x0100)
190 #define MAC_CSR19_DIR1 FIELD16(0x0200)
191 #define MAC_CSR19_DIR2 FIELD16(0x0400)
192 #define MAC_CSR19_DIR3 FIELD16(0x0800)
193 #define MAC_CSR19_DIR4 FIELD16(0x1000)
194 #define MAC_CSR19_DIR5 FIELD16(0x2000)
195 #define MAC_CSR19_DIR6 FIELD16(0x4000)
196 #define MAC_CSR19_DIR7 FIELD16(0x8000)
200 * ACTIVITY: 0: idle, 1: active.
201 * LINK: 0: linkoff, 1: linkup.
202 * ACTIVITY_POLARITY: 0: active low, 1: active high.
204 #define MAC_CSR20 0x0428
205 #define MAC_CSR20_ACTIVITY FIELD16(0x0001)
206 #define MAC_CSR20_LINK FIELD16(0x0002)
207 #define MAC_CSR20_ACTIVITY_POLARITY FIELD16(0x0004)
214 #define MAC_CSR21 0x042a
215 #define MAC_CSR21_ON_PERIOD FIELD16(0x00ff)
216 #define MAC_CSR21_OFF_PERIOD FIELD16(0xff00)
221 #define MAC_CSR22 0x042c
231 #define TXRX_CSR0 0x0440
232 #define TXRX_CSR0_ALGORITHM FIELD16(0x0007)
233 #define TXRX_CSR0_IV_OFFSET FIELD16(0x01f8)
234 #define TXRX_CSR0_KEY_ID FIELD16(0x1e00)
242 #define TXRX_CSR1 0x0442
243 #define TXRX_CSR1_ACK_TIMEOUT FIELD16(0x00ff)
244 #define TXRX_CSR1_TSF_OFFSET FIELD16(0x7f00)
245 #define TXRX_CSR1_AUTO_SEQUENCE FIELD16(0x8000)
259 #define TXRX_CSR2 0x0444
260 #define TXRX_CSR2_DISABLE_RX FIELD16(0x0001)
261 #define TXRX_CSR2_DROP_CRC FIELD16(0x0002)
262 #define TXRX_CSR2_DROP_PHYSICAL FIELD16(0x0004)
263 #define TXRX_CSR2_DROP_CONTROL FIELD16(0x0008)
264 #define TXRX_CSR2_DROP_NOT_TO_ME FIELD16(0x0010)
265 #define TXRX_CSR2_DROP_TODS FIELD16(0x0020)
266 #define TXRX_CSR2_DROP_VERSION_ERROR FIELD16(0x0040)
267 #define TXRX_CSR2_DROP_MULTICAST FIELD16(0x0200)
268 #define TXRX_CSR2_DROP_BROADCAST FIELD16(0x0400)
275 #define TXRX_CSR3 0x0446
276 #define TXRX_CSR4 0x0448
281 #define TXRX_CSR5 0x044a
282 #define TXRX_CSR5_BBP_ID0 FIELD16(0x007f)
283 #define TXRX_CSR5_BBP_ID0_VALID FIELD16(0x0080)
284 #define TXRX_CSR5_BBP_ID1 FIELD16(0x7f00)
285 #define TXRX_CSR5_BBP_ID1_VALID FIELD16(0x8000)
290 #define TXRX_CSR6 0x044c
291 #define TXRX_CSR6_BBP_ID0 FIELD16(0x007f)
292 #define TXRX_CSR6_BBP_ID0_VALID FIELD16(0x0080)
293 #define TXRX_CSR6_BBP_ID1 FIELD16(0x7f00)
294 #define TXRX_CSR6_BBP_ID1_VALID FIELD16(0x8000)
299 #define TXRX_CSR7 0x044e
300 #define TXRX_CSR7_BBP_ID0 FIELD16(0x007f)
301 #define TXRX_CSR7_BBP_ID0_VALID FIELD16(0x0080)
302 #define TXRX_CSR7_BBP_ID1 FIELD16(0x7f00)
303 #define TXRX_CSR7_BBP_ID1_VALID FIELD16(0x8000)
308 #define TXRX_CSR8 0x0450
309 #define TXRX_CSR8_BBP_ID0 FIELD16(0x007f)
310 #define TXRX_CSR8_BBP_ID0_VALID FIELD16(0x0080)
311 #define TXRX_CSR8_BBP_ID1 FIELD16(0x7f00)
312 #define TXRX_CSR8_BBP_ID1_VALID FIELD16(0x8000)
317 #define TXRX_CSR9 0x0452
322 #define TXRX_CSR10 0x0454
323 #define TXRX_CSR10_AUTORESPOND_PREAMBLE FIELD16(0x0004)
328 #define TXRX_CSR11 0x0456
333 #define TXRX_CSR12 0x0458
334 #define TXRX_CSR13 0x045a
335 #define TXRX_CSR14 0x045c
336 #define TXRX_CSR15 0x045e
337 #define TXRX_CSR16 0x0460
338 #define TXRX_CSR17 0x0462
343 #define TXRX_CSR18 0x0464
344 #define TXRX_CSR18_OFFSET FIELD16(0x000f)
345 #define TXRX_CSR18_INTERVAL FIELD16(0xfff0)
350 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
354 #define TXRX_CSR19 0x0466
355 #define TXRX_CSR19_TSF_COUNT FIELD16(0x0001)
356 #define TXRX_CSR19_TSF_SYNC FIELD16(0x0006)
357 #define TXRX_CSR19_TBCN FIELD16(0x0008)
358 #define TXRX_CSR19_BEACON_GEN FIELD16(0x0010)
365 #define TXRX_CSR20 0x0468
366 #define TXRX_CSR20_OFFSET FIELD16(0x1fff)
367 #define TXRX_CSR20_BCN_EXPECT_WINDOW FIELD16(0xe000)
372 #define TXRX_CSR21 0x046a
380 * SEC_CSR0: Shared key 0, word 0
381 * SEC_CSR1: Shared key 0, word 1
382 * SEC_CSR2: Shared key 0, word 2
383 * SEC_CSR3: Shared key 0, word 3
384 * SEC_CSR4: Shared key 0, word 4
385 * SEC_CSR5: Shared key 0, word 5
386 * SEC_CSR6: Shared key 0, word 6
387 * SEC_CSR7: Shared key 0, word 7
389 #define SEC_CSR0 0x0480
390 #define SEC_CSR1 0x0482
391 #define SEC_CSR2 0x0484
392 #define SEC_CSR3 0x0486
393 #define SEC_CSR4 0x0488
394 #define SEC_CSR5 0x048a
395 #define SEC_CSR6 0x048c
396 #define SEC_CSR7 0x048e
399 * SEC_CSR8: Shared key 1, word 0
408 #define SEC_CSR8 0x0490
409 #define SEC_CSR9 0x0492
410 #define SEC_CSR10 0x0494
411 #define SEC_CSR11 0x0496
412 #define SEC_CSR12 0x0498
413 #define SEC_CSR13 0x049a
414 #define SEC_CSR14 0x049c
415 #define SEC_CSR15 0x049e
418 * SEC_CSR16: Shared key 2, word 0
427 #define SEC_CSR16 0x04a0
428 #define SEC_CSR17 0x04a2
429 #define SEC_CSR18 0X04A4
430 #define SEC_CSR19 0x04a6
431 #define SEC_CSR20 0x04a8
432 #define SEC_CSR21 0x04aa
433 #define SEC_CSR22 0x04ac
434 #define SEC_CSR23 0x04ae
437 * SEC_CSR24: Shared key 3, word 0
446 #define SEC_CSR24 0x04b0
447 #define SEC_CSR25 0x04b2
448 #define SEC_CSR26 0x04b4
449 #define SEC_CSR27 0x04b6
450 #define SEC_CSR28 0x04b8
451 #define SEC_CSR29 0x04ba
452 #define SEC_CSR30 0x04bc
453 #define SEC_CSR31 0x04be
465 #define PHY_CSR0 0x04c0
470 #define PHY_CSR1 0x04c2
482 #define PHY_CSR2 0x04c4
483 #define PHY_CSR2_LNA FIELD16(0x0002)
484 #define PHY_CSR2_LNA_MODE FIELD16(0x3000)
489 #define PHY_CSR3 0x04c6
494 #define PHY_CSR4 0x04c8
495 #define PHY_CSR4_LOW_RF_LE FIELD16(0x0001)
501 #define PHY_CSR5 0x04ca
502 #define PHY_CSR5_CCK FIELD16(0x0003)
503 #define PHY_CSR5_CCK_FLIP FIELD16(0x0004)
509 #define PHY_CSR6 0x04cc
510 #define PHY_CSR6_OFDM FIELD16(0x0003)
511 #define PHY_CSR6_OFDM_FLIP FIELD16(0x0004)
514 * PHY_CSR7: BBP access register 0.
517 * BBP_READ_CONTROL: 0: write, 1: read.
519 #define PHY_CSR7 0x04ce
520 #define PHY_CSR7_DATA FIELD16(0x00ff)
521 #define PHY_CSR7_REG_ID FIELD16(0x7f00)
522 #define PHY_CSR7_READ_CONTROL FIELD16(0x8000)
528 #define PHY_CSR8 0x04d0
529 #define PHY_CSR8_BUSY FIELD16(0x0001)
535 #define PHY_CSR9 0x04d2
536 #define PHY_CSR9_RF_VALUE FIELD16(0xffff)
542 * RF_IF_SELECT: Chip to program: 0: rf, 1: if.
546 #define PHY_CSR10 0x04d4
547 #define PHY_CSR10_RF_VALUE FIELD16(0x00ff)
548 #define PHY_CSR10_RF_NUMBER_OF_BITS FIELD16(0x1f00)
549 #define PHY_CSR10_RF_IF_SELECT FIELD16(0x2000)
550 #define PHY_CSR10_RF_PLL_LD FIELD16(0x4000)
551 #define PHY_CSR10_RF_BUSY FIELD16(0x8000)
557 #define STA_CSR0 0x04e0
558 #define STA_CSR0_FCS_ERROR FIELD16(0xffff)
563 #define STA_CSR1 0x04e2
568 #define STA_CSR2 0x04e4
574 #define STA_CSR3 0x04e6
575 #define STA_CSR3_FALSE_CCA_ERROR FIELD16(0xffff)
580 #define STA_CSR4 0x04e8
585 #define STA_CSR5 0x04ea
590 #define STA_CSR6 0x04ec
591 #define STA_CSR7 0x04ee
592 #define STA_CSR8 0x04f0
593 #define STA_CSR9 0x04f2
594 #define STA_CSR10 0x04f4
604 #define BBP_R2_TX_ANTENNA FIELD8(0x03)
605 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
610 #define BBP_R14_RX_ANTENNA FIELD8(0x03)
611 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
620 #define RF1_TUNER FIELD32(0x00020000)
625 #define RF3_TUNER FIELD32(0x00000100)
626 #define RF3_TXPOWER FIELD32(0x00003e00)
635 #define EEPROM_MAC_ADDR_0 0x0002
636 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
637 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
638 #define EEPROM_MAC_ADDR1 0x0003
639 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
640 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
641 #define EEPROM_MAC_ADDR_2 0x0004
642 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
643 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
648 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
649 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
650 * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd.
655 #define EEPROM_ANTENNA 0x000b
656 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
657 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
658 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
659 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
660 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
661 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
662 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
666 * CARDBUS_ACCEL: 0: enable, 1: disable.
667 * DYN_BBP_TUNE: 0: enable, 1: disable.
670 #define EEPROM_NIC 0x000c
671 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
672 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
673 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
679 #define EEPROM_GEOGRAPHY 0x000d
680 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
685 #define EEPROM_BBP_START 0x000e
687 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
688 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
693 #define EEPROM_TXPOWER_START 0x001e
695 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
696 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
701 #define EEPROM_BBPTUNE 0x0030
702 #define EEPROM_BBPTUNE_THRESHOLD FIELD16(0x00ff)
707 #define EEPROM_BBPTUNE_R24 0x0031
708 #define EEPROM_BBPTUNE_R24_LOW FIELD16(0x00ff)
709 #define EEPROM_BBPTUNE_R24_HIGH FIELD16(0xff00)
714 #define EEPROM_BBPTUNE_R25 0x0032
715 #define EEPROM_BBPTUNE_R25_LOW FIELD16(0x00ff)
716 #define EEPROM_BBPTUNE_R25_HIGH FIELD16(0xff00)
721 #define EEPROM_BBPTUNE_R61 0x0033
722 #define EEPROM_BBPTUNE_R61_LOW FIELD16(0x00ff)
723 #define EEPROM_BBPTUNE_R61_HIGH FIELD16(0xff00)
728 #define EEPROM_BBPTUNE_VGC 0x0034
729 #define EEPROM_BBPTUNE_VGCUPPER FIELD16(0x00ff)
730 #define EEPROM_BBPTUNE_VGCLOWER FIELD16(0xff00)
735 #define EEPROM_BBPTUNE_R17 0x0035
736 #define EEPROM_BBPTUNE_R17_LOW FIELD16(0x00ff)
737 #define EEPROM_BBPTUNE_R17_HIGH FIELD16(0xff00)
742 #define EEPROM_CALIBRATE_OFFSET 0x0036
743 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
758 #define TXD_W0_PACKET_ID FIELD32(0x0000000f)
759 #define TXD_W0_RETRY_LIMIT FIELD32(0x000000f0)
760 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
761 #define TXD_W0_ACK FIELD32(0x00000200)
762 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
763 #define TXD_W0_OFDM FIELD32(0x00000800)
764 #define TXD_W0_NEW_SEQ FIELD32(0x00001000)
765 #define TXD_W0_IFS FIELD32(0x00006000)
766 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
767 #define TXD_W0_CIPHER FIELD32(0x20000000)
768 #define TXD_W0_KEY_ID FIELD32(0xc0000000)
773 #define TXD_W1_IV_OFFSET FIELD32(0x0000003f)
774 #define TXD_W1_AIFS FIELD32(0x000000c0)
775 #define TXD_W1_CWMIN FIELD32(0x00000f00)
776 #define TXD_W1_CWMAX FIELD32(0x0000f000)
781 #define TXD_W2_PLCP_SIGNAL FIELD32(0x000000ff)
782 #define TXD_W2_PLCP_SERVICE FIELD32(0x0000ff00)
783 #define TXD_W2_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
784 #define TXD_W2_PLCP_LENGTH_HIGH FIELD32(0xff000000)
789 #define TXD_W3_IV FIELD32(0xffffffff)
794 #define TXD_W4_EIV FIELD32(0xffffffff)
803 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
804 #define RXD_W0_MULTICAST FIELD32(0x00000004)
805 #define RXD_W0_BROADCAST FIELD32(0x00000008)
806 #define RXD_W0_MY_BSS FIELD32(0x00000010)
807 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
808 #define RXD_W0_OFDM FIELD32(0x00000040)
809 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
810 #define RXD_W0_CIPHER FIELD32(0x00000100)
811 #define RXD_W0_CIPHER_ERROR FIELD32(0x00000200)
812 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
817 #define RXD_W1_RSSI FIELD32(0x000000ff)
818 #define RXD_W1_SIGNAL FIELD32(0x0000ff00)
823 #define RXD_W2_IV FIELD32(0xffffffff)
828 #define RXD_W3_EIV FIELD32(0xffffffff)
834 #define MIN_TXPOWER 0