Lines Matching +full:0 +full:x000000ff
20 #define RF2522 0x0000
21 #define RF2523 0x0001
22 #define RF2524 0x0002
23 #define RF2525 0x0003
24 #define RF2525E 0x0004
25 #define RF5222 0x0010
43 #define CSR_REG_BASE 0x0000
44 #define CSR_REG_SIZE 0x0174
45 #define EEPROM_BASE 0x0000
46 #define EEPROM_SIZE 0x0200
47 #define BBP_BASE 0x0000
48 #define BBP_SIZE 0x0040
49 #define RF_BASE 0x0004
50 #define RF_SIZE 0x0010
65 #define CSR0 0x0000
66 #define CSR0_REVISION FIELD32(0x0000ffff)
70 * SOFT_RESET: Software reset, 1: reset, 0: normal.
71 * BBP_RESET: Hardware reset, 1: reset, 0, release.
74 #define CSR1 0x0004
75 #define CSR1_SOFT_RESET FIELD32(0x00000001)
76 #define CSR1_BBP_RESET FIELD32(0x00000002)
77 #define CSR1_HOST_READY FIELD32(0x00000004)
82 #define CSR2 0x0008
85 * CSR3: STA MAC address register 0.
87 #define CSR3 0x000c
88 #define CSR3_BYTE0 FIELD32(0x000000ff)
89 #define CSR3_BYTE1 FIELD32(0x0000ff00)
90 #define CSR3_BYTE2 FIELD32(0x00ff0000)
91 #define CSR3_BYTE3 FIELD32(0xff000000)
96 #define CSR4 0x0010
97 #define CSR4_BYTE4 FIELD32(0x000000ff)
98 #define CSR4_BYTE5 FIELD32(0x0000ff00)
101 * CSR5: BSSID register 0.
103 #define CSR5 0x0014
104 #define CSR5_BYTE0 FIELD32(0x000000ff)
105 #define CSR5_BYTE1 FIELD32(0x0000ff00)
106 #define CSR5_BYTE2 FIELD32(0x00ff0000)
107 #define CSR5_BYTE3 FIELD32(0xff000000)
112 #define CSR6 0x0018
113 #define CSR6_BYTE4 FIELD32(0x000000ff)
114 #define CSR6_BYTE5 FIELD32(0x0000ff00)
141 #define CSR7 0x001c
142 #define CSR7_TBCN_EXPIRE FIELD32(0x00000001)
143 #define CSR7_TWAKE_EXPIRE FIELD32(0x00000002)
144 #define CSR7_TATIMW_EXPIRE FIELD32(0x00000004)
145 #define CSR7_TXDONE_TXRING FIELD32(0x00000008)
146 #define CSR7_TXDONE_ATIMRING FIELD32(0x00000010)
147 #define CSR7_TXDONE_PRIORING FIELD32(0x00000020)
148 #define CSR7_RXDONE FIELD32(0x00000040)
149 #define CSR7_DECRYPTION_DONE FIELD32(0x00000080)
150 #define CSR7_ENCRYPTION_DONE FIELD32(0x00000100)
151 #define CSR7_UART1_TX_TRESHOLD FIELD32(0x00000200)
152 #define CSR7_UART1_RX_TRESHOLD FIELD32(0x00000400)
153 #define CSR7_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
154 #define CSR7_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
155 #define CSR7_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
156 #define CSR7_UART2_TX_TRESHOLD FIELD32(0x00004000)
157 #define CSR7_UART2_RX_TRESHOLD FIELD32(0x00008000)
158 #define CSR7_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
159 #define CSR7_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
160 #define CSR7_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
161 #define CSR7_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
187 #define CSR8 0x0020
188 #define CSR8_TBCN_EXPIRE FIELD32(0x00000001)
189 #define CSR8_TWAKE_EXPIRE FIELD32(0x00000002)
190 #define CSR8_TATIMW_EXPIRE FIELD32(0x00000004)
191 #define CSR8_TXDONE_TXRING FIELD32(0x00000008)
192 #define CSR8_TXDONE_ATIMRING FIELD32(0x00000010)
193 #define CSR8_TXDONE_PRIORING FIELD32(0x00000020)
194 #define CSR8_RXDONE FIELD32(0x00000040)
195 #define CSR8_DECRYPTION_DONE FIELD32(0x00000080)
196 #define CSR8_ENCRYPTION_DONE FIELD32(0x00000100)
197 #define CSR8_UART1_TX_TRESHOLD FIELD32(0x00000200)
198 #define CSR8_UART1_RX_TRESHOLD FIELD32(0x00000400)
199 #define CSR8_UART1_IDLE_TRESHOLD FIELD32(0x00000800)
200 #define CSR8_UART1_TX_BUFF_ERROR FIELD32(0x00001000)
201 #define CSR8_UART1_RX_BUFF_ERROR FIELD32(0x00002000)
202 #define CSR8_UART2_TX_TRESHOLD FIELD32(0x00004000)
203 #define CSR8_UART2_RX_TRESHOLD FIELD32(0x00008000)
204 #define CSR8_UART2_IDLE_TRESHOLD FIELD32(0x00010000)
205 #define CSR8_UART2_TX_BUFF_ERROR FIELD32(0x00020000)
206 #define CSR8_UART2_RX_BUFF_ERROR FIELD32(0x00040000)
207 #define CSR8_TIMER_CSR3_EXPIRE FIELD32(0x00080000)
213 #define CSR9 0x0024
214 #define CSR9_MAX_FRAME_UNIT FIELD32(0x00000f80)
219 * ONE_SHOT: 0: ring mode, 1: One shot only mode.
222 #define SECCSR0 0x0028
223 #define SECCSR0_KICK_DECRYPT FIELD32(0x00000001)
224 #define SECCSR0_ONE_SHOT FIELD32(0x00000002)
225 #define SECCSR0_DESC_ADDRESS FIELD32(0xfffffffc)
232 * CW_SELECT: CWmin/CWmax selection, 1: Register, 0: TXD.
236 #define CSR11 0x002c
237 #define CSR11_CWMIN FIELD32(0x0000000f)
238 #define CSR11_CWMAX FIELD32(0x000000f0)
239 #define CSR11_SLOT_TIME FIELD32(0x00001f00)
240 #define CSR11_CW_SELECT FIELD32(0x00002000)
241 #define CSR11_LONG_RETRY FIELD32(0x00ff0000)
242 #define CSR11_SHORT_RETRY FIELD32(0xff000000)
245 * CSR12: Synchronization configuration register 0.
250 #define CSR12 0x0030
251 #define CSR12_BEACON_INTERVAL FIELD32(0x0000ffff)
252 #define CSR12_CFP_MAX_DURATION FIELD32(0xffff0000)
258 * CFP_PERIOD: Cfp period, default is 0 TU.
260 #define CSR13 0x0034
261 #define CSR13_ATIMW_DURATION FIELD32(0x0000ffff)
262 #define CSR13_CFP_PERIOD FIELD32(0x00ff0000)
267 * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode.
275 #define CSR14 0x0038
276 #define CSR14_TSF_COUNT FIELD32(0x00000001)
277 #define CSR14_TSF_SYNC FIELD32(0x00000006)
278 #define CSR14_TBCN FIELD32(0x00000008)
279 #define CSR14_TCFP FIELD32(0x00000010)
280 #define CSR14_TATIMW FIELD32(0x00000020)
281 #define CSR14_BEACON_GEN FIELD32(0x00000040)
282 #define CSR14_CFP_COUNT_PRELOAD FIELD32(0x0000ff00)
283 #define CSR14_TBCM_PRELOAD FIELD32(0xffff0000)
291 #define CSR15 0x003c
292 #define CSR15_CFP FIELD32(0x00000001)
293 #define CSR15_ATIMW FIELD32(0x00000002)
294 #define CSR15_BEACON_SENT FIELD32(0x00000004)
297 * CSR16: TSF timer register 0.
299 #define CSR16 0x0040
300 #define CSR16_LOW_TSFTIMER FIELD32(0xffffffff)
305 #define CSR17 0x0044
306 #define CSR17_HIGH_TSFTIMER FIELD32(0xffffffff)
309 * CSR18: IFS timer register 0.
313 #define CSR18 0x0048
314 #define CSR18_SIFS FIELD32(0x000001ff)
315 #define CSR18_PIFS FIELD32(0x001f0000)
322 #define CSR19 0x004c
323 #define CSR19_DIFS FIELD32(0x0000ffff)
324 #define CSR19_EIFS FIELD32(0xffff0000)
332 #define CSR20 0x0050
333 #define CSR20_DELAY_AFTER_TBCN FIELD32(0x0000ffff)
334 #define CSR20_TBCN_BEFORE_WAKEUP FIELD32(0x00ff0000)
335 #define CSR20_AUTOWAKE FIELD32(0x01000000)
340 * TYPE_93C46: 1: 93c46, 0:93c66.
342 #define CSR21 0x0054
343 #define CSR21_RELOAD FIELD32(0x00000001)
344 #define CSR21_EEPROM_DATA_CLOCK FIELD32(0x00000002)
345 #define CSR21_EEPROM_CHIP_SELECT FIELD32(0x00000004)
346 #define CSR21_EEPROM_DATA_IN FIELD32(0x00000008)
347 #define CSR21_EEPROM_DATA_OUT FIELD32(0x00000010)
348 #define CSR21_TYPE_93C46 FIELD32(0x00000020)
355 #define CSR22 0x0058
356 #define CSR22_CFP_DURATION_REMAIN FIELD32(0x0000ffff)
357 #define CSR22_RELOAD_CFP_DURATION FIELD32(0x00010000)
371 #define TXCSR0 0x0060
372 #define TXCSR0_KICK_TX FIELD32(0x00000001)
373 #define TXCSR0_KICK_ATIM FIELD32(0x00000002)
374 #define TXCSR0_KICK_PRIO FIELD32(0x00000004)
375 #define TXCSR0_ABORT FIELD32(0x00000008)
384 #define TXCSR1 0x0064
385 #define TXCSR1_ACK_TIMEOUT FIELD32(0x000001ff)
386 #define TXCSR1_ACK_CONSUME_TIME FIELD32(0x0003fe00)
387 #define TXCSR1_TSF_OFFSET FIELD32(0x00fc0000)
388 #define TXCSR1_AUTORESPONDER FIELD32(0x01000000)
397 #define TXCSR2 0x0068
398 #define TXCSR2_TXD_SIZE FIELD32(0x000000ff)
399 #define TXCSR2_NUM_TXD FIELD32(0x0000ff00)
400 #define TXCSR2_NUM_ATIM FIELD32(0x00ff0000)
401 #define TXCSR2_NUM_PRIO FIELD32(0xff000000)
406 #define TXCSR3 0x006c
407 #define TXCSR3_TX_RING_REGISTER FIELD32(0xffffffff)
412 #define TXCSR4 0x0070
413 #define TXCSR4_ATIM_RING_REGISTER FIELD32(0xffffffff)
418 #define TXCSR5 0x0074
419 #define TXCSR5_PRIO_RING_REGISTER FIELD32(0xffffffff)
424 #define TXCSR6 0x0078
425 #define TXCSR6_BEACON_RING_REGISTER FIELD32(0xffffffff)
431 #define TXCSR7 0x007c
432 #define TXCSR7_AR_POWERMANAGEMENT FIELD32(0x00000001)
437 #define TXCSR8 0x0098
438 #define TXCSR8_BBP_ID0 FIELD32(0x0000007f)
439 #define TXCSR8_BBP_ID0_VALID FIELD32(0x00000080)
440 #define TXCSR8_BBP_ID1 FIELD32(0x00007f00)
441 #define TXCSR8_BBP_ID1_VALID FIELD32(0x00008000)
442 #define TXCSR8_BBP_ID2 FIELD32(0x007f0000)
443 #define TXCSR8_BBP_ID2_VALID FIELD32(0x00800000)
444 #define TXCSR8_BBP_ID3 FIELD32(0x7f000000)
445 #define TXCSR8_BBP_ID3_VALID FIELD32(0x80000000)
454 #define TXCSR9 0x0094
455 #define TXCSR9_OFDM_RATE FIELD32(0x000000ff)
456 #define TXCSR9_OFDM_SERVICE FIELD32(0x0000ff00)
457 #define TXCSR9_OFDM_LENGTH_LOW FIELD32(0x00ff0000)
458 #define TXCSR9_OFDM_LENGTH_HIGH FIELD32(0xff000000)
481 #define RXCSR0 0x0080
482 #define RXCSR0_DISABLE_RX FIELD32(0x00000001)
483 #define RXCSR0_DROP_CRC FIELD32(0x00000002)
484 #define RXCSR0_DROP_PHYSICAL FIELD32(0x00000004)
485 #define RXCSR0_DROP_CONTROL FIELD32(0x00000008)
486 #define RXCSR0_DROP_NOT_TO_ME FIELD32(0x00000010)
487 #define RXCSR0_DROP_TODS FIELD32(0x00000020)
488 #define RXCSR0_DROP_VERSION_ERROR FIELD32(0x00000040)
489 #define RXCSR0_PASS_CRC FIELD32(0x00000080)
490 #define RXCSR0_PASS_PLCP FIELD32(0x00000100)
491 #define RXCSR0_DROP_MCAST FIELD32(0x00000200)
492 #define RXCSR0_DROP_BCAST FIELD32(0x00000400)
493 #define RXCSR0_ENABLE_QOS FIELD32(0x00000800)
500 #define RXCSR1 0x0084
501 #define RXCSR1_RXD_SIZE FIELD32(0x000000ff)
502 #define RXCSR1_NUM_RXD FIELD32(0x0000ff00)
507 #define RXCSR2 0x0088
508 #define RXCSR2_RX_RING_REGISTER FIELD32(0xffffffff)
515 #define RXCSR3 0x0090
516 #define RXCSR3_BBP_ID0 FIELD32(0x0000007f)
517 #define RXCSR3_BBP_ID0_VALID FIELD32(0x00000080)
518 #define RXCSR3_BBP_ID1 FIELD32(0x00007f00)
519 #define RXCSR3_BBP_ID1_VALID FIELD32(0x00008000)
520 #define RXCSR3_BBP_ID2 FIELD32(0x007f0000)
521 #define RXCSR3_BBP_ID2_VALID FIELD32(0x00800000)
522 #define RXCSR3_BBP_ID3 FIELD32(0x7f000000)
523 #define RXCSR3_BBP_ID3_VALID FIELD32(0x80000000)
530 #define ARCSR1 0x009c
531 #define ARCSR1_AR_BBP_DATA2 FIELD32(0x000000ff)
532 #define ARCSR1_AR_BBP_ID2 FIELD32(0x0000ff00)
533 #define ARCSR1_AR_BBP_DATA3 FIELD32(0x00ff0000)
534 #define ARCSR1_AR_BBP_ID3 FIELD32(0xff000000)
544 * BIG_ENDIAN: 1: big endian, 0: little endian.
546 * 0: 16dw (default), 1: 8dw, 2: 4dw, 3: 32dw.
548 * 0: 0dw (default), 1: 1dw, 2: 4dw, 3: forward.
549 * BURST_LENTH: Pci burst length 0: 4dw (default, 1: 8dw, 2: 16dw, 3:32dw.
554 #define PCICSR 0x008c
555 #define PCICSR_BIG_ENDIAN FIELD32(0x00000001)
556 #define PCICSR_RX_TRESHOLD FIELD32(0x00000006)
557 #define PCICSR_TX_TRESHOLD FIELD32(0x00000018)
558 #define PCICSR_BURST_LENTH FIELD32(0x00000060)
559 #define PCICSR_ENABLE_CLK FIELD32(0x00000080)
560 #define PCICSR_READ_MULTIPLE FIELD32(0x00000100)
561 #define PCICSR_WRITE_INVALID FIELD32(0x00000200)
567 #define CNT0 0x00a0
568 #define CNT0_FCS_ERROR FIELD32(0x0000ffff)
575 #define TIMECSR2 0x00a8
576 #define CNT1 0x00ac
577 #define CNT2 0x00b0
578 #define TIMECSR3 0x00b4
583 #define CNT3 0x00b8
584 #define CNT3_FALSE_CCA FIELD32(0x0000ffff)
591 #define CNT4 0x00bc
592 #define CNT5 0x00c0
601 #define PWRCSR0 0x00c4
606 #define PSCSR0 0x00c8
607 #define PSCSR1 0x00cc
608 #define PSCSR2 0x00d0
609 #define PSCSR3 0x00d4
613 * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake.
621 #define PWRCSR1 0x00d8
622 #define PWRCSR1_SET_STATE FIELD32(0x00000001)
623 #define PWRCSR1_BBP_DESIRE_STATE FIELD32(0x00000006)
624 #define PWRCSR1_RF_DESIRE_STATE FIELD32(0x00000018)
625 #define PWRCSR1_BBP_CURR_STATE FIELD32(0x00000060)
626 #define PWRCSR1_RF_CURR_STATE FIELD32(0x00000180)
627 #define PWRCSR1_PUT_TO_SLEEP FIELD32(0x00000200)
635 #define TIMECSR 0x00dc
636 #define TIMECSR_US_COUNT FIELD32(0x000000ff)
637 #define TIMECSR_US_64_COUNT FIELD32(0x0000ff00)
638 #define TIMECSR_BEACON_EXPECT FIELD32(0x00070000)
641 * MACCSR0: MAC configuration register 0.
643 #define MACCSR0 0x00e0
652 * LOOPBACK: Loopback mode. 0: normal, 1: internal, 2: external, 3:rsvd.
655 #define MACCSR1 0x00e4
656 #define MACCSR1_KICK_RX FIELD32(0x00000001)
657 #define MACCSR1_ONESHOT_RXMODE FIELD32(0x00000002)
658 #define MACCSR1_BBPRX_RESET_MODE FIELD32(0x00000004)
659 #define MACCSR1_AUTO_TXBBP FIELD32(0x00000008)
660 #define MACCSR1_AUTO_RXBBP FIELD32(0x00000010)
661 #define MACCSR1_LOOPBACK FIELD32(0x00000060)
662 #define MACCSR1_INTERSIL_IF FIELD32(0x00000080)
669 #define RALINKCSR 0x00e8
670 #define RALINKCSR_AR_BBP_DATA0 FIELD32(0x000000ff)
671 #define RALINKCSR_AR_BBP_ID0 FIELD32(0x00007f00)
672 #define RALINKCSR_AR_BBP_VALID0 FIELD32(0x00008000)
673 #define RALINKCSR_AR_BBP_DATA1 FIELD32(0x00ff0000)
674 #define RALINKCSR_AR_BBP_ID1 FIELD32(0x7f000000)
675 #define RALINKCSR_AR_BBP_VALID1 FIELD32(0x80000000)
685 #define BCNCSR 0x00ec
686 #define BCNCSR_CHANGE FIELD32(0x00000001)
687 #define BCNCSR_DELTATIME FIELD32(0x0000001e)
688 #define BCNCSR_NUM_BEACON FIELD32(0x00001fe0)
689 #define BCNCSR_MODE FIELD32(0x00006000)
690 #define BCNCSR_PLUS FIELD32(0x00008000)
701 * WRITE_CONTROL: 1: write BBP, 0: read BBP.
703 #define BBPCSR 0x00f0
704 #define BBPCSR_VALUE FIELD32(0x000000ff)
705 #define BBPCSR_REGNUM FIELD32(0x00007f00)
706 #define BBPCSR_BUSY FIELD32(0x00008000)
707 #define BBPCSR_WRITE_CONTROL FIELD32(0x00010000)
713 * IF_SELECT: Chip to program: 0: rf, 1: if.
717 #define RFCSR 0x00f4
718 #define RFCSR_VALUE FIELD32(0x00ffffff)
719 #define RFCSR_NUMBER_OF_BITS FIELD32(0x1f000000)
720 #define RFCSR_IF_SELECT FIELD32(0x20000000)
721 #define RFCSR_PLL_LD FIELD32(0x40000000)
722 #define RFCSR_BUSY FIELD32(0x80000000)
728 * LINK: 0: linkoff, 1: linkup.
729 * ACTIVITY: 0: idle, 1: active.
730 * LINK_POLARITY: 0: active low, 1: active high.
731 * ACTIVITY_POLARITY: 0: active low, 1: active high.
732 * LED_DEFAULT: LED state for "enable" 0: ON, 1: OFF.
734 #define LEDCSR 0x00f8
735 #define LEDCSR_ON_PERIOD FIELD32(0x000000ff)
736 #define LEDCSR_OFF_PERIOD FIELD32(0x0000ff00)
737 #define LEDCSR_LINK FIELD32(0x00010000)
738 #define LEDCSR_ACTIVITY FIELD32(0x00020000)
739 #define LEDCSR_LINK_POLARITY FIELD32(0x00040000)
740 #define LEDCSR_ACTIVITY_POLARITY FIELD32(0x00080000)
741 #define LEDCSR_LED_DEFAULT FIELD32(0x00100000)
746 #define SECCSR3 0x00fc
755 #define RXPTR 0x0100
756 #define TXPTR 0x0104
757 #define PRIPTR 0x0108
758 #define ATIMPTR 0x010c
763 #define TXACKCSR0 0x0110
770 #define ACKCNT0 0x0114
771 #define ACKCNT1 0x0118
780 * GPIOCSR_DIRx: GPIO direction: 0 = output; 1 = input
782 #define GPIOCSR 0x0120
783 #define GPIOCSR_VAL0 FIELD32(0x00000001)
784 #define GPIOCSR_VAL1 FIELD32(0x00000002)
785 #define GPIOCSR_VAL2 FIELD32(0x00000004)
786 #define GPIOCSR_VAL3 FIELD32(0x00000008)
787 #define GPIOCSR_VAL4 FIELD32(0x00000010)
788 #define GPIOCSR_VAL5 FIELD32(0x00000020)
789 #define GPIOCSR_VAL6 FIELD32(0x00000040)
790 #define GPIOCSR_VAL7 FIELD32(0x00000080)
791 #define GPIOCSR_DIR0 FIELD32(0x00000100)
792 #define GPIOCSR_DIR1 FIELD32(0x00000200)
793 #define GPIOCSR_DIR2 FIELD32(0x00000400)
794 #define GPIOCSR_DIR3 FIELD32(0x00000800)
795 #define GPIOCSR_DIR4 FIELD32(0x00001000)
796 #define GPIOCSR_DIR5 FIELD32(0x00002000)
797 #define GPIOCSR_DIR6 FIELD32(0x00004000)
798 #define GPIOCSR_DIR7 FIELD32(0x00008000)
805 #define FIFOCSR0 0x0128
806 #define FIFOCSR1 0x012c
813 #define BCNCSR1 0x0130
814 #define BCNCSR1_PRELOAD FIELD32(0x0000ffff)
815 #define BCNCSR1_BEACON_CWMIN FIELD32(0x000f0000)
821 #define MACCSR2 0x0134
822 #define MACCSR2_DELAY FIELD32(0x000000ff)
827 #define TESTCSR 0x0138
832 #define ARCSR2 0x013c
833 #define ARCSR2_SIGNAL FIELD32(0x000000ff)
834 #define ARCSR2_SERVICE FIELD32(0x0000ff00)
835 #define ARCSR2_LENGTH FIELD32(0xffff0000)
840 #define ARCSR3 0x0140
841 #define ARCSR3_SIGNAL FIELD32(0x000000ff)
842 #define ARCSR3_SERVICE FIELD32(0x0000ff00)
843 #define ARCSR3_LENGTH FIELD32(0xffff0000)
848 #define ARCSR4 0x0144
849 #define ARCSR4_SIGNAL FIELD32(0x000000ff)
850 #define ARCSR4_SERVICE FIELD32(0x0000ff00)
851 #define ARCSR4_LENGTH FIELD32(0xffff0000)
856 #define ARCSR5 0x0148
857 #define ARCSR5_SIGNAL FIELD32(0x000000ff)
858 #define ARCSR5_SERVICE FIELD32(0x0000ff00)
859 #define ARCSR5_LENGTH FIELD32(0xffff0000)
864 #define ARTCSR0 0x014c
865 #define ARTCSR0_ACK_CTS_11MBS FIELD32(0x000000ff)
866 #define ARTCSR0_ACK_CTS_5_5MBS FIELD32(0x0000ff00)
867 #define ARTCSR0_ACK_CTS_2MBS FIELD32(0x00ff0000)
868 #define ARTCSR0_ACK_CTS_1MBS FIELD32(0xff000000)
874 #define ARTCSR1 0x0150
875 #define ARTCSR1_ACK_CTS_6MBS FIELD32(0x000000ff)
876 #define ARTCSR1_ACK_CTS_9MBS FIELD32(0x0000ff00)
877 #define ARTCSR1_ACK_CTS_12MBS FIELD32(0x00ff0000)
878 #define ARTCSR1_ACK_CTS_18MBS FIELD32(0xff000000)
883 #define ARTCSR2 0x0154
884 #define ARTCSR2_ACK_CTS_24MBS FIELD32(0x000000ff)
885 #define ARTCSR2_ACK_CTS_36MBS FIELD32(0x0000ff00)
886 #define ARTCSR2_ACK_CTS_48MBS FIELD32(0x00ff0000)
887 #define ARTCSR2_ACK_CTS_54MBS FIELD32(0xff000000)
892 * ONE_SHOT: 0: ring mode, 1: One shot only mode.
895 #define SECCSR1 0x0158
896 #define SECCSR1_KICK_ENCRYPT FIELD32(0x00000001)
897 #define SECCSR1_ONE_SHOT FIELD32(0x00000002)
898 #define SECCSR1_DESC_ADDRESS FIELD32(0xfffffffc)
903 #define BBPCSR1 0x015c
904 #define BBPCSR1_CCK FIELD32(0x00000003)
905 #define BBPCSR1_CCK_FLIP FIELD32(0x00000004)
906 #define BBPCSR1_OFDM FIELD32(0x00030000)
907 #define BBPCSR1_OFDM_FLIP FIELD32(0x00040000)
911 * DBANDCSR0: Dual band configuration register 0.
914 #define DBANDCSR0 0x0160
915 #define DBANDCSR1 0x0164
920 #define BBPPCSR 0x0168
924 * DBGSEL0: MAC special debug mode selection register 0.
927 #define DBGSEL0 0x016c
928 #define DBGSEL1 0x0170
933 #define BISTCSR 0x0174
937 * MCAST0: Multicast filter register 0.
940 #define MCAST0 0x0178
941 #define MCAST1 0x017c
954 #define UARTCSR0 0x0180
955 #define UARTCSR1 0x0184
956 #define UARTCSR3 0x0188
957 #define UARTCSR4 0x018c
958 #define UART2CSR0 0x0190
959 #define UART2CSR1 0x0194
960 #define UART2CSR3 0x0198
961 #define UART2CSR4 0x019c
971 #define BBP_R2_TX_ANTENNA FIELD8(0x03)
972 #define BBP_R2_TX_IQ_FLIP FIELD8(0x04)
977 #define BBP_R14_RX_ANTENNA FIELD8(0x03)
978 #define BBP_R14_RX_IQ_FLIP FIELD8(0x04)
983 #define BBP_R70_JAPAN_FILTER FIELD8(0x08)
992 #define RF1_TUNER FIELD32(0x00020000)
997 #define RF3_TUNER FIELD32(0x00000100)
998 #define RF3_TXPOWER FIELD32(0x00003e00)
1008 #define EEPROM_MAC_ADDR_0 0x0002
1009 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1010 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1011 #define EEPROM_MAC_ADDR1 0x0003
1012 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1013 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1014 #define EEPROM_MAC_ADDR_2 0x0004
1015 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1016 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1021 * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1022 * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B.
1023 * LED_MODE: 0: default, 1: TX/RX activity,2: Single (ignore link), 3: rsvd.
1028 #define EEPROM_ANTENNA 0x10
1029 #define EEPROM_ANTENNA_NUM FIELD16(0x0003)
1030 #define EEPROM_ANTENNA_TX_DEFAULT FIELD16(0x000c)
1031 #define EEPROM_ANTENNA_RX_DEFAULT FIELD16(0x0030)
1032 #define EEPROM_ANTENNA_LED_MODE FIELD16(0x01c0)
1033 #define EEPROM_ANTENNA_DYN_TXAGC FIELD16(0x0200)
1034 #define EEPROM_ANTENNA_HARDWARE_RADIO FIELD16(0x0400)
1035 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0xf800)
1039 * CARDBUS_ACCEL: 0: enable, 1: disable.
1040 * DYN_BBP_TUNE: 0: enable, 1: disable.
1043 #define EEPROM_NIC 0x11
1044 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0001)
1045 #define EEPROM_NIC_DYN_BBP_TUNE FIELD16(0x0002)
1046 #define EEPROM_NIC_CCK_TX_POWER FIELD16(0x000c)
1052 #define EEPROM_GEOGRAPHY 0x12
1053 #define EEPROM_GEOGRAPHY_GEO FIELD16(0x0f00)
1058 #define EEPROM_BBP_START 0x13
1060 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1061 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1066 #define EEPROM_TXPOWER_START 0x23
1068 #define EEPROM_TXPOWER_1 FIELD16(0x00ff)
1069 #define EEPROM_TXPOWER_2 FIELD16(0xff00)
1074 #define EEPROM_CALIBRATE_OFFSET 0x3e
1075 #define EEPROM_CALIBRATE_OFFSET_RSSI FIELD16(0x00ff)
1090 #define TXD_W0_OWNER_NIC FIELD32(0x00000001)
1091 #define TXD_W0_VALID FIELD32(0x00000002)
1092 #define TXD_W0_RESULT FIELD32(0x0000001c)
1093 #define TXD_W0_RETRY_COUNT FIELD32(0x000000e0)
1094 #define TXD_W0_MORE_FRAG FIELD32(0x00000100)
1095 #define TXD_W0_ACK FIELD32(0x00000200)
1096 #define TXD_W0_TIMESTAMP FIELD32(0x00000400)
1097 #define TXD_W0_OFDM FIELD32(0x00000800)
1098 #define TXD_W0_CIPHER_OWNER FIELD32(0x00001000)
1099 #define TXD_W0_IFS FIELD32(0x00006000)
1100 #define TXD_W0_RETRY_MODE FIELD32(0x00008000)
1101 #define TXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1102 #define TXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1107 #define TXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1112 #define TXD_W2_IV_OFFSET FIELD32(0x0000003f)
1113 #define TXD_W2_AIFS FIELD32(0x000000c0)
1114 #define TXD_W2_CWMIN FIELD32(0x00000f00)
1115 #define TXD_W2_CWMAX FIELD32(0x0000f000)
1120 #define TXD_W3_PLCP_SIGNAL FIELD32(0x000000ff)
1121 #define TXD_W3_PLCP_SERVICE FIELD32(0x0000ff00)
1122 #define TXD_W3_PLCP_LENGTH_LOW FIELD32(0x00ff0000)
1123 #define TXD_W3_PLCP_LENGTH_HIGH FIELD32(0xff000000)
1128 #define TXD_W4_IV FIELD32(0xffffffff)
1133 #define TXD_W5_EIV FIELD32(0xffffffff)
1138 #define TXD_W6_KEY FIELD32(0xffffffff)
1139 #define TXD_W7_KEY FIELD32(0xffffffff)
1140 #define TXD_W8_KEY FIELD32(0xffffffff)
1141 #define TXD_W9_KEY FIELD32(0xffffffff)
1146 #define TXD_W10_RTS FIELD32(0x00000001)
1147 #define TXD_W10_TX_RATE FIELD32(0x000000fe)
1156 #define RXD_W0_OWNER_NIC FIELD32(0x00000001)
1157 #define RXD_W0_UNICAST_TO_ME FIELD32(0x00000002)
1158 #define RXD_W0_MULTICAST FIELD32(0x00000004)
1159 #define RXD_W0_BROADCAST FIELD32(0x00000008)
1160 #define RXD_W0_MY_BSS FIELD32(0x00000010)
1161 #define RXD_W0_CRC_ERROR FIELD32(0x00000020)
1162 #define RXD_W0_OFDM FIELD32(0x00000040)
1163 #define RXD_W0_PHYSICAL_ERROR FIELD32(0x00000080)
1164 #define RXD_W0_CIPHER_OWNER FIELD32(0x00000100)
1165 #define RXD_W0_ICV_ERROR FIELD32(0x00000200)
1166 #define RXD_W0_IV_OFFSET FIELD32(0x0000fc00)
1167 #define RXD_W0_DATABYTE_COUNT FIELD32(0x0fff0000)
1168 #define RXD_W0_CIPHER_ALG FIELD32(0xe0000000)
1173 #define RXD_W1_BUFFER_ADDRESS FIELD32(0xffffffff)
1178 #define RXD_W2_SIGNAL FIELD32(0x000000ff)
1179 #define RXD_W2_RSSI FIELD32(0x0000ff00)
1180 #define RXD_W2_TA FIELD32(0xffff0000)
1185 #define RXD_W3_TA FIELD32(0xffffffff)
1190 #define RXD_W4_IV FIELD32(0xffffffff)
1195 #define RXD_W5_EIV FIELD32(0xffffffff)
1200 #define RXD_W6_KEY FIELD32(0xffffffff)
1201 #define RXD_W7_KEY FIELD32(0xffffffff)
1202 #define RXD_W8_KEY FIELD32(0xffffffff)
1203 #define RXD_W9_KEY FIELD32(0xffffffff)
1208 #define RXD_W10_DROP FIELD32(0x00000001)
1214 #define MIN_TXPOWER 0