Lines Matching full:reg
48 u32 reg; in rt2400pci_bbp_write() local
56 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_write()
57 reg = 0; in rt2400pci_bbp_write()
58 rt2x00_set_field32(®, BBPCSR_VALUE, value); in rt2400pci_bbp_write()
59 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_write()
60 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_write()
61 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 1); in rt2400pci_bbp_write()
63 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_write()
72 u32 reg; in rt2400pci_bbp_read() local
82 * doesn't become available in time, reg will be 0xffffffff in rt2400pci_bbp_read()
85 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt2400pci_bbp_read()
86 reg = 0; in rt2400pci_bbp_read()
87 rt2x00_set_field32(®, BBPCSR_REGNUM, word); in rt2400pci_bbp_read()
88 rt2x00_set_field32(®, BBPCSR_BUSY, 1); in rt2400pci_bbp_read()
89 rt2x00_set_field32(®, BBPCSR_WRITE_CONTROL, 0); in rt2400pci_bbp_read()
91 rt2x00mmio_register_write(rt2x00dev, BBPCSR, reg); in rt2400pci_bbp_read()
93 WAIT_FOR_BBP(rt2x00dev, ®); in rt2400pci_bbp_read()
96 value = rt2x00_get_field32(reg, BBPCSR_VALUE); in rt2400pci_bbp_read()
106 u32 reg; in rt2400pci_rf_write() local
114 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt2400pci_rf_write()
115 reg = 0; in rt2400pci_rf_write()
116 rt2x00_set_field32(®, RFCSR_VALUE, value); in rt2400pci_rf_write()
117 rt2x00_set_field32(®, RFCSR_NUMBER_OF_BITS, 20); in rt2400pci_rf_write()
118 rt2x00_set_field32(®, RFCSR_IF_SELECT, 0); in rt2400pci_rf_write()
119 rt2x00_set_field32(®, RFCSR_BUSY, 1); in rt2400pci_rf_write()
121 rt2x00mmio_register_write(rt2x00dev, RFCSR, reg); in rt2400pci_rf_write()
131 u32 reg; in rt2400pci_eepromregister_read() local
133 reg = rt2x00mmio_register_read(rt2x00dev, CSR21); in rt2400pci_eepromregister_read()
135 eeprom->reg_data_in = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_IN); in rt2400pci_eepromregister_read()
136 eeprom->reg_data_out = !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_OUT); in rt2400pci_eepromregister_read()
138 !!rt2x00_get_field32(reg, CSR21_EEPROM_DATA_CLOCK); in rt2400pci_eepromregister_read()
140 !!rt2x00_get_field32(reg, CSR21_EEPROM_CHIP_SELECT); in rt2400pci_eepromregister_read()
146 u32 reg = 0; in rt2400pci_eepromregister_write() local
148 rt2x00_set_field32(®, CSR21_EEPROM_DATA_IN, !!eeprom->reg_data_in); in rt2400pci_eepromregister_write()
149 rt2x00_set_field32(®, CSR21_EEPROM_DATA_OUT, !!eeprom->reg_data_out); in rt2400pci_eepromregister_write()
150 rt2x00_set_field32(®, CSR21_EEPROM_DATA_CLOCK, in rt2400pci_eepromregister_write()
152 rt2x00_set_field32(®, CSR21_EEPROM_CHIP_SELECT, in rt2400pci_eepromregister_write()
155 rt2x00mmio_register_write(rt2x00dev, CSR21, reg); in rt2400pci_eepromregister_write()
195 u32 reg; in rt2400pci_rfkill_poll() local
197 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); in rt2400pci_rfkill_poll()
198 return rt2x00_get_field32(reg, GPIOCSR_VAL0); in rt2400pci_rfkill_poll()
208 u32 reg; in rt2400pci_brightness_set() local
210 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); in rt2400pci_brightness_set()
213 rt2x00_set_field32(®, LEDCSR_LINK, enabled); in rt2400pci_brightness_set()
215 rt2x00_set_field32(®, LEDCSR_ACTIVITY, enabled); in rt2400pci_brightness_set()
217 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_brightness_set()
226 u32 reg; in rt2400pci_blink_set() local
228 reg = rt2x00mmio_register_read(led->rt2x00dev, LEDCSR); in rt2400pci_blink_set()
229 rt2x00_set_field32(®, LEDCSR_ON_PERIOD, *delay_on); in rt2400pci_blink_set()
230 rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, *delay_off); in rt2400pci_blink_set()
231 rt2x00mmio_register_write(led->rt2x00dev, LEDCSR, reg); in rt2400pci_blink_set()
254 u32 reg; in rt2400pci_config_filter() local
261 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2400pci_config_filter()
262 rt2x00_set_field32(®, RXCSR0_DROP_CRC, in rt2400pci_config_filter()
264 rt2x00_set_field32(®, RXCSR0_DROP_PHYSICAL, in rt2400pci_config_filter()
266 rt2x00_set_field32(®, RXCSR0_DROP_CONTROL, in rt2400pci_config_filter()
268 rt2x00_set_field32(®, RXCSR0_DROP_NOT_TO_ME, in rt2400pci_config_filter()
270 rt2x00_set_field32(®, RXCSR0_DROP_TODS, in rt2400pci_config_filter()
273 rt2x00_set_field32(®, RXCSR0_DROP_VERSION_ERROR, 1); in rt2400pci_config_filter()
274 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_config_filter()
283 u32 reg; in rt2400pci_config_intf() local
290 reg = rt2x00mmio_register_read(rt2x00dev, BCNCSR1); in rt2400pci_config_intf()
291 rt2x00_set_field32(®, BCNCSR1_PRELOAD, bcn_preload); in rt2400pci_config_intf()
292 rt2x00mmio_register_write(rt2x00dev, BCNCSR1, reg); in rt2400pci_config_intf()
297 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_config_intf()
298 rt2x00_set_field32(®, CSR14_TSF_SYNC, conf->sync); in rt2400pci_config_intf()
299 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_config_intf()
317 u32 reg; in rt2400pci_config_erp() local
325 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR1); in rt2400pci_config_erp()
326 rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, 0x1ff); in rt2400pci_config_erp()
327 rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, 0x13a); in rt2400pci_config_erp()
328 rt2x00_set_field32(®, TXCSR1_TSF_OFFSET, IEEE80211_HEADER); in rt2400pci_config_erp()
329 rt2x00_set_field32(®, TXCSR1_AUTORESPONDER, 1); in rt2400pci_config_erp()
330 rt2x00mmio_register_write(rt2x00dev, TXCSR1, reg); in rt2400pci_config_erp()
332 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR2); in rt2400pci_config_erp()
333 rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00); in rt2400pci_config_erp()
334 rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04); in rt2400pci_config_erp()
335 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
337 rt2x00mmio_register_write(rt2x00dev, ARCSR2, reg); in rt2400pci_config_erp()
339 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR3); in rt2400pci_config_erp()
340 rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask); in rt2400pci_config_erp()
341 rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04); in rt2400pci_config_erp()
342 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
344 rt2x00mmio_register_write(rt2x00dev, ARCSR3, reg); in rt2400pci_config_erp()
346 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR4); in rt2400pci_config_erp()
347 rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask); in rt2400pci_config_erp()
348 rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04); in rt2400pci_config_erp()
349 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
351 rt2x00mmio_register_write(rt2x00dev, ARCSR4, reg); in rt2400pci_config_erp()
353 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR5); in rt2400pci_config_erp()
354 rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask); in rt2400pci_config_erp()
355 rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84); in rt2400pci_config_erp()
356 rt2x00_set_field32(®, ARCSR2_LENGTH, in rt2400pci_config_erp()
358 rt2x00mmio_register_write(rt2x00dev, ARCSR5, reg); in rt2400pci_config_erp()
365 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2400pci_config_erp()
366 rt2x00_set_field32(®, CSR11_SLOT_TIME, erp->slot_time); in rt2400pci_config_erp()
367 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_erp()
369 reg = rt2x00mmio_register_read(rt2x00dev, CSR18); in rt2400pci_config_erp()
370 rt2x00_set_field32(®, CSR18_SIFS, erp->sifs); in rt2400pci_config_erp()
371 rt2x00_set_field32(®, CSR18_PIFS, erp->pifs); in rt2400pci_config_erp()
372 rt2x00mmio_register_write(rt2x00dev, CSR18, reg); in rt2400pci_config_erp()
374 reg = rt2x00mmio_register_read(rt2x00dev, CSR19); in rt2400pci_config_erp()
375 rt2x00_set_field32(®, CSR19_DIFS, erp->difs); in rt2400pci_config_erp()
376 rt2x00_set_field32(®, CSR19_EIFS, erp->eifs); in rt2400pci_config_erp()
377 rt2x00mmio_register_write(rt2x00dev, CSR19, reg); in rt2400pci_config_erp()
381 reg = rt2x00mmio_register_read(rt2x00dev, CSR12); in rt2400pci_config_erp()
382 rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, in rt2400pci_config_erp()
384 rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, in rt2400pci_config_erp()
386 rt2x00mmio_register_write(rt2x00dev, CSR12, reg); in rt2400pci_config_erp()
501 u32 reg; in rt2400pci_config_retry_limit() local
503 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2400pci_config_retry_limit()
504 rt2x00_set_field32(®, CSR11_LONG_RETRY, in rt2400pci_config_retry_limit()
506 rt2x00_set_field32(®, CSR11_SHORT_RETRY, in rt2400pci_config_retry_limit()
508 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_retry_limit()
517 u32 reg; in rt2400pci_config_ps() local
520 reg = rt2x00mmio_register_read(rt2x00dev, CSR20); in rt2400pci_config_ps()
521 rt2x00_set_field32(®, CSR20_DELAY_AFTER_TBCN, in rt2400pci_config_ps()
523 rt2x00_set_field32(®, CSR20_TBCN_BEFORE_WAKEUP, in rt2400pci_config_ps()
527 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2400pci_config_ps()
528 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
530 rt2x00_set_field32(®, CSR20_AUTOWAKE, 1); in rt2400pci_config_ps()
531 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
533 reg = rt2x00mmio_register_read(rt2x00dev, CSR20); in rt2400pci_config_ps()
534 rt2x00_set_field32(®, CSR20_AUTOWAKE, 0); in rt2400pci_config_ps()
535 rt2x00mmio_register_write(rt2x00dev, CSR20, reg); in rt2400pci_config_ps()
559 u32 reg; in rt2400pci_config_cw() local
561 reg = rt2x00mmio_register_read(rt2x00dev, CSR11); in rt2400pci_config_cw()
562 rt2x00_set_field32(®, CSR11_CWMIN, cw_min); in rt2400pci_config_cw()
563 rt2x00_set_field32(®, CSR11_CWMAX, cw_max); in rt2400pci_config_cw()
564 rt2x00mmio_register_write(rt2x00dev, CSR11, reg); in rt2400pci_config_cw()
573 u32 reg; in rt2400pci_link_stats() local
579 reg = rt2x00mmio_register_read(rt2x00dev, CNT0); in rt2400pci_link_stats()
580 qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR); in rt2400pci_link_stats()
630 u32 reg; in rt2400pci_start_queue() local
634 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2400pci_start_queue()
635 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 0); in rt2400pci_start_queue()
636 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_start_queue()
639 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_start_queue()
640 rt2x00_set_field32(®, CSR14_TSF_COUNT, 1); in rt2400pci_start_queue()
641 rt2x00_set_field32(®, CSR14_TBCN, 1); in rt2400pci_start_queue()
642 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_start_queue()
643 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_start_queue()
653 u32 reg; in rt2400pci_kick_queue() local
657 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_kick_queue()
658 rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1); in rt2400pci_kick_queue()
659 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
662 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_kick_queue()
663 rt2x00_set_field32(®, TXCSR0_KICK_TX, 1); in rt2400pci_kick_queue()
664 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
667 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_kick_queue()
668 rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1); in rt2400pci_kick_queue()
669 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_kick_queue()
679 u32 reg; in rt2400pci_stop_queue() local
685 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR0); in rt2400pci_stop_queue()
686 rt2x00_set_field32(®, TXCSR0_ABORT, 1); in rt2400pci_stop_queue()
687 rt2x00mmio_register_write(rt2x00dev, TXCSR0, reg); in rt2400pci_stop_queue()
690 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR0); in rt2400pci_stop_queue()
691 rt2x00_set_field32(®, RXCSR0_DISABLE_RX, 1); in rt2400pci_stop_queue()
692 rt2x00mmio_register_write(rt2x00dev, RXCSR0, reg); in rt2400pci_stop_queue()
695 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_stop_queue()
696 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2400pci_stop_queue()
697 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2400pci_stop_queue()
698 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_stop_queue()
699 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_stop_queue()
760 u32 reg; in rt2400pci_init_queues() local
765 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR2); in rt2400pci_init_queues()
766 rt2x00_set_field32(®, TXCSR2_TXD_SIZE, rt2x00dev->tx[0].desc_size); in rt2400pci_init_queues()
767 rt2x00_set_field32(®, TXCSR2_NUM_TXD, rt2x00dev->tx[1].limit); in rt2400pci_init_queues()
768 rt2x00_set_field32(®, TXCSR2_NUM_ATIM, rt2x00dev->atim->limit); in rt2400pci_init_queues()
769 rt2x00_set_field32(®, TXCSR2_NUM_PRIO, rt2x00dev->tx[0].limit); in rt2400pci_init_queues()
770 rt2x00mmio_register_write(rt2x00dev, TXCSR2, reg); in rt2400pci_init_queues()
773 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR3); in rt2400pci_init_queues()
774 rt2x00_set_field32(®, TXCSR3_TX_RING_REGISTER, in rt2400pci_init_queues()
776 rt2x00mmio_register_write(rt2x00dev, TXCSR3, reg); in rt2400pci_init_queues()
779 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR5); in rt2400pci_init_queues()
780 rt2x00_set_field32(®, TXCSR5_PRIO_RING_REGISTER, in rt2400pci_init_queues()
782 rt2x00mmio_register_write(rt2x00dev, TXCSR5, reg); in rt2400pci_init_queues()
785 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR4); in rt2400pci_init_queues()
786 rt2x00_set_field32(®, TXCSR4_ATIM_RING_REGISTER, in rt2400pci_init_queues()
788 rt2x00mmio_register_write(rt2x00dev, TXCSR4, reg); in rt2400pci_init_queues()
791 reg = rt2x00mmio_register_read(rt2x00dev, TXCSR6); in rt2400pci_init_queues()
792 rt2x00_set_field32(®, TXCSR6_BEACON_RING_REGISTER, in rt2400pci_init_queues()
794 rt2x00mmio_register_write(rt2x00dev, TXCSR6, reg); in rt2400pci_init_queues()
796 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR1); in rt2400pci_init_queues()
797 rt2x00_set_field32(®, RXCSR1_RXD_SIZE, rt2x00dev->rx->desc_size); in rt2400pci_init_queues()
798 rt2x00_set_field32(®, RXCSR1_NUM_RXD, rt2x00dev->rx->limit); in rt2400pci_init_queues()
799 rt2x00mmio_register_write(rt2x00dev, RXCSR1, reg); in rt2400pci_init_queues()
802 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR2); in rt2400pci_init_queues()
803 rt2x00_set_field32(®, RXCSR2_RX_RING_REGISTER, in rt2400pci_init_queues()
805 rt2x00mmio_register_write(rt2x00dev, RXCSR2, reg); in rt2400pci_init_queues()
812 u32 reg; in rt2400pci_init_registers() local
819 reg = rt2x00mmio_register_read(rt2x00dev, TIMECSR); in rt2400pci_init_registers()
820 rt2x00_set_field32(®, TIMECSR_US_COUNT, 33); in rt2400pci_init_registers()
821 rt2x00_set_field32(®, TIMECSR_US_64_COUNT, 63); in rt2400pci_init_registers()
822 rt2x00_set_field32(®, TIMECSR_BEACON_EXPECT, 0); in rt2400pci_init_registers()
823 rt2x00mmio_register_write(rt2x00dev, TIMECSR, reg); in rt2400pci_init_registers()
825 reg = rt2x00mmio_register_read(rt2x00dev, CSR9); in rt2400pci_init_registers()
826 rt2x00_set_field32(®, CSR9_MAX_FRAME_UNIT, in rt2400pci_init_registers()
828 rt2x00mmio_register_write(rt2x00dev, CSR9, reg); in rt2400pci_init_registers()
830 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_init_registers()
831 rt2x00_set_field32(®, CSR14_TSF_COUNT, 0); in rt2400pci_init_registers()
832 rt2x00_set_field32(®, CSR14_TSF_SYNC, 0); in rt2400pci_init_registers()
833 rt2x00_set_field32(®, CSR14_TBCN, 0); in rt2400pci_init_registers()
834 rt2x00_set_field32(®, CSR14_TCFP, 0); in rt2400pci_init_registers()
835 rt2x00_set_field32(®, CSR14_TATIMW, 0); in rt2400pci_init_registers()
836 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_init_registers()
837 rt2x00_set_field32(®, CSR14_CFP_COUNT_PRELOAD, 0); in rt2400pci_init_registers()
838 rt2x00_set_field32(®, CSR14_TBCM_PRELOAD, 0); in rt2400pci_init_registers()
839 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_init_registers()
843 reg = rt2x00mmio_register_read(rt2x00dev, ARCSR0); in rt2400pci_init_registers()
844 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA0, 133); in rt2400pci_init_registers()
845 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID0, 134); in rt2400pci_init_registers()
846 rt2x00_set_field32(®, ARCSR0_AR_BBP_DATA1, 136); in rt2400pci_init_registers()
847 rt2x00_set_field32(®, ARCSR0_AR_BBP_ID1, 135); in rt2400pci_init_registers()
848 rt2x00mmio_register_write(rt2x00dev, ARCSR0, reg); in rt2400pci_init_registers()
850 reg = rt2x00mmio_register_read(rt2x00dev, RXCSR3); in rt2400pci_init_registers()
851 rt2x00_set_field32(®, RXCSR3_BBP_ID0, 3); /* Tx power.*/ in rt2400pci_init_registers()
852 rt2x00_set_field32(®, RXCSR3_BBP_ID0_VALID, 1); in rt2400pci_init_registers()
853 rt2x00_set_field32(®, RXCSR3_BBP_ID1, 32); /* Signal */ in rt2400pci_init_registers()
854 rt2x00_set_field32(®, RXCSR3_BBP_ID1_VALID, 1); in rt2400pci_init_registers()
855 rt2x00_set_field32(®, RXCSR3_BBP_ID2, 36); /* Rssi */ in rt2400pci_init_registers()
856 rt2x00_set_field32(®, RXCSR3_BBP_ID2_VALID, 1); in rt2400pci_init_registers()
857 rt2x00mmio_register_write(rt2x00dev, RXCSR3, reg); in rt2400pci_init_registers()
867 reg = rt2x00mmio_register_read(rt2x00dev, MACCSR2); in rt2400pci_init_registers()
868 rt2x00_set_field32(®, MACCSR2_DELAY, 64); in rt2400pci_init_registers()
869 rt2x00mmio_register_write(rt2x00dev, MACCSR2, reg); in rt2400pci_init_registers()
871 reg = rt2x00mmio_register_read(rt2x00dev, RALINKCSR); in rt2400pci_init_registers()
872 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA0, 17); in rt2400pci_init_registers()
873 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID0, 154); in rt2400pci_init_registers()
874 rt2x00_set_field32(®, RALINKCSR_AR_BBP_DATA1, 0); in rt2400pci_init_registers()
875 rt2x00_set_field32(®, RALINKCSR_AR_BBP_ID1, 154); in rt2400pci_init_registers()
876 rt2x00mmio_register_write(rt2x00dev, RALINKCSR, reg); in rt2400pci_init_registers()
878 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2400pci_init_registers()
879 rt2x00_set_field32(®, CSR1_SOFT_RESET, 1); in rt2400pci_init_registers()
880 rt2x00_set_field32(®, CSR1_BBP_RESET, 0); in rt2400pci_init_registers()
881 rt2x00_set_field32(®, CSR1_HOST_READY, 0); in rt2400pci_init_registers()
882 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
884 reg = rt2x00mmio_register_read(rt2x00dev, CSR1); in rt2400pci_init_registers()
885 rt2x00_set_field32(®, CSR1_SOFT_RESET, 0); in rt2400pci_init_registers()
886 rt2x00_set_field32(®, CSR1_HOST_READY, 1); in rt2400pci_init_registers()
887 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); in rt2400pci_init_registers()
894 reg = rt2x00mmio_register_read(rt2x00dev, CNT0); in rt2400pci_init_registers()
895 reg = rt2x00mmio_register_read(rt2x00dev, CNT4); in rt2400pci_init_registers()
961 u32 reg; in rt2400pci_toggle_irq() local
969 reg = rt2x00mmio_register_read(rt2x00dev, CSR7); in rt2400pci_toggle_irq()
970 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_toggle_irq()
979 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_toggle_irq()
980 rt2x00_set_field32(®, CSR8_TBCN_EXPIRE, mask); in rt2400pci_toggle_irq()
981 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, mask); in rt2400pci_toggle_irq()
982 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, mask); in rt2400pci_toggle_irq()
983 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, mask); in rt2400pci_toggle_irq()
984 rt2x00_set_field32(®, CSR8_RXDONE, mask); in rt2400pci_toggle_irq()
985 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_toggle_irq()
1024 u32 reg, reg2; in rt2400pci_set_state() local
1032 reg = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); in rt2400pci_set_state()
1033 rt2x00_set_field32(®, PWRCSR1_SET_STATE, 1); in rt2400pci_set_state()
1034 rt2x00_set_field32(®, PWRCSR1_BBP_DESIRE_STATE, state); in rt2400pci_set_state()
1035 rt2x00_set_field32(®, PWRCSR1_RF_DESIRE_STATE, state); in rt2400pci_set_state()
1036 rt2x00_set_field32(®, PWRCSR1_PUT_TO_SLEEP, put_to_sleep); in rt2400pci_set_state()
1037 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1050 rt2x00mmio_register_write(rt2x00dev, PWRCSR1, reg); in rt2400pci_set_state()
1169 u32 reg; in rt2400pci_write_beacon() local
1175 reg = rt2x00mmio_register_read(rt2x00dev, CSR14); in rt2400pci_write_beacon()
1176 rt2x00_set_field32(®, CSR14_BEACON_GEN, 0); in rt2400pci_write_beacon()
1177 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1186 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_write_beacon()
1200 rt2x00_set_field32(®, CSR14_BEACON_GEN, 1); in rt2400pci_write_beacon()
1201 rt2x00mmio_register_write(rt2x00dev, CSR14, reg); in rt2400pci_write_beacon()
1307 u32 reg; in rt2400pci_enable_interrupt() local
1315 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_enable_interrupt()
1316 rt2x00_set_field32(®, irq_field, 0); in rt2400pci_enable_interrupt()
1317 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_enable_interrupt()
1326 u32 reg; in rt2400pci_txstatus_tasklet() local
1341 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_txstatus_tasklet()
1342 rt2x00_set_field32(®, CSR8_TXDONE_TXRING, 0); in rt2400pci_txstatus_tasklet()
1343 rt2x00_set_field32(®, CSR8_TXDONE_ATIMRING, 0); in rt2400pci_txstatus_tasklet()
1344 rt2x00_set_field32(®, CSR8_TXDONE_PRIORING, 0); in rt2400pci_txstatus_tasklet()
1345 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_txstatus_tasklet()
1372 u32 reg, mask; in rt2400pci_interrupt() local
1378 reg = rt2x00mmio_register_read(rt2x00dev, CSR7); in rt2400pci_interrupt()
1379 rt2x00mmio_register_write(rt2x00dev, CSR7, reg); in rt2400pci_interrupt()
1381 if (!reg) in rt2400pci_interrupt()
1387 mask = reg; in rt2400pci_interrupt()
1392 if (rt2x00_get_field32(reg, CSR7_TBCN_EXPIRE)) in rt2400pci_interrupt()
1395 if (rt2x00_get_field32(reg, CSR7_RXDONE)) in rt2400pci_interrupt()
1398 if (rt2x00_get_field32(reg, CSR7_TXDONE_ATIMRING) || in rt2400pci_interrupt()
1399 rt2x00_get_field32(reg, CSR7_TXDONE_PRIORING) || in rt2400pci_interrupt()
1400 rt2x00_get_field32(reg, CSR7_TXDONE_TXRING)) { in rt2400pci_interrupt()
1416 reg = rt2x00mmio_register_read(rt2x00dev, CSR8); in rt2400pci_interrupt()
1417 reg |= mask; in rt2400pci_interrupt()
1418 rt2x00mmio_register_write(rt2x00dev, CSR8, reg); in rt2400pci_interrupt()
1433 u32 reg; in rt2400pci_validate_eeprom() local
1437 reg = rt2x00mmio_register_read(rt2x00dev, CSR21); in rt2400pci_validate_eeprom()
1442 eeprom.width = rt2x00_get_field32(reg, CSR21_TYPE_93C46) ? in rt2400pci_validate_eeprom()
1469 u32 reg; in rt2400pci_init_eeprom() local
1482 reg = rt2x00mmio_register_read(rt2x00dev, CSR0); in rt2400pci_init_eeprom()
1484 rt2x00_get_field32(reg, CSR0_REVISION)); in rt2400pci_init_eeprom()
1610 u32 reg; in rt2400pci_probe_hw() local
1627 reg = rt2x00mmio_register_read(rt2x00dev, GPIOCSR); in rt2400pci_probe_hw()
1628 rt2x00_set_field32(®, GPIOCSR_DIR0, 1); in rt2400pci_probe_hw()
1629 rt2x00mmio_register_write(rt2x00dev, GPIOCSR, reg); in rt2400pci_probe_hw()
1688 u32 reg; in rt2400pci_get_tsf() local
1690 reg = rt2x00mmio_register_read(rt2x00dev, CSR17); in rt2400pci_get_tsf()
1691 tsf = (u64) rt2x00_get_field32(reg, CSR17_HIGH_TSFTIMER) << 32; in rt2400pci_get_tsf()
1692 reg = rt2x00mmio_register_read(rt2x00dev, CSR16); in rt2400pci_get_tsf()
1693 tsf |= rt2x00_get_field32(reg, CSR16_LOW_TSFTIMER); in rt2400pci_get_tsf()
1701 u32 reg; in rt2400pci_tx_last_beacon() local
1703 reg = rt2x00mmio_register_read(rt2x00dev, CSR15); in rt2400pci_tx_last_beacon()
1704 return rt2x00_get_field32(reg, CSR15_BEACON_SENT); in rt2400pci_tx_last_beacon()