Lines Matching refs:WILC_SPI_REG_BASE

84 #define WILC_SPI_REG_BASE		0xe800  macro
85 #define WILC_SPI_CTL			WILC_SPI_REG_BASE
86 #define WILC_SPI_MASTER_DMA_ADDR	(WILC_SPI_REG_BASE + 0x4)
87 #define WILC_SPI_MASTER_DMA_COUNT	(WILC_SPI_REG_BASE + 0x8)
88 #define WILC_SPI_SLAVE_DMA_ADDR		(WILC_SPI_REG_BASE + 0xc)
89 #define WILC_SPI_SLAVE_DMA_COUNT	(WILC_SPI_REG_BASE + 0x10)
90 #define WILC_SPI_TX_MODE		(WILC_SPI_REG_BASE + 0x20)
91 #define WILC_SPI_PROTOCOL_CONFIG	(WILC_SPI_REG_BASE + 0x24)
92 #define WILC_SPI_INTR_CTL		(WILC_SPI_REG_BASE + 0x2c)
93 #define WILC_SPI_INT_STATUS		(WILC_SPI_REG_BASE + 0x40)
94 #define WILC_SPI_INT_CLEAR		(WILC_SPI_REG_BASE + 0x44)
108 					 WILC_SPI_REG_BASE)