Lines Matching +full:cmd +full:- +full:dat +full:- +full:delay +full:- +full:select
1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2012 - 2018 Microchip Technology Inc., and its subsidiaries.
10 #include <linux/crc-itu-t.h>
23 "\t\t\tCommand transfers are short and the CPU-cycle cost\n"
31 "\t\t\tData transfers can be large and the CPU-cycle cost\n"
38 * USER GUIDE" (https://tinyurl.com/4hhshdts) but we have observed 1-4
105 * Select the data packet size (log2 of number of bytes): Use the
165 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_parse_gpios()
166 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_parse_gpios()
167 struct wilc_gpios *gpios = &spi_priv->gpios; in wilc_parse_gpios()
170 gpios->enable = devm_gpiod_get_optional(&spi->dev, in wilc_parse_gpios()
173 if (gpios->enable) { in wilc_parse_gpios()
175 gpios->reset = devm_gpiod_get(&spi->dev, in wilc_parse_gpios()
177 if (IS_ERR(gpios->reset)) { in wilc_parse_gpios()
178 dev_err(&spi->dev, "missing reset gpio.\n"); in wilc_parse_gpios()
179 return PTR_ERR(gpios->reset); in wilc_parse_gpios()
182 gpios->reset = devm_gpiod_get_optional(&spi->dev, in wilc_parse_gpios()
190 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_wlan_power()
191 struct wilc_gpios *gpios = &spi_priv->gpios; in wilc_wlan_power()
195 gpiod_set_value(gpios->enable, 1); in wilc_wlan_power()
198 gpiod_set_value(gpios->reset, 0); in wilc_wlan_power()
201 gpiod_set_value(gpios->reset, 1); in wilc_wlan_power()
203 gpiod_set_value(gpios->enable, 0); in wilc_wlan_power()
216 return -ENOMEM; in wilc_bus_probe()
218 ret = wilc_cfg80211_init(&wilc, &spi->dev, WILC_HIF_SPI, &wilc_hif_spi); in wilc_bus_probe()
223 wilc->dev = &spi->dev; in wilc_bus_probe()
224 wilc->bus_data = spi_priv; in wilc_bus_probe()
225 wilc->dev_irq_num = spi->irq; in wilc_bus_probe()
231 wilc->rtc_clk = devm_clk_get_optional_enabled(&spi->dev, "rtc"); in wilc_bus_probe()
232 if (IS_ERR(wilc->rtc_clk)) { in wilc_bus_probe()
233 ret = PTR_ERR(wilc->rtc_clk); in wilc_bus_probe()
237 dev_info(&spi->dev, "Selected CRC config: crc7=%s, crc16=%s\n", in wilc_bus_probe()
279 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_bus_remove()
312 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_tx()
320 .delay = { in wilc_spi_tx()
328 return -ENOMEM; in wilc_spi_tx()
331 dev_dbg(&spi->dev, "Request writing %d bytes\n", len); in wilc_spi_tx()
339 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_tx()
343 dev_err(&spi->dev, in wilc_spi_tx()
346 ret = -EINVAL; in wilc_spi_tx()
354 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_rx()
362 .delay = { in wilc_spi_rx()
371 return -ENOMEM; in wilc_spi_rx()
381 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_rx()
384 dev_err(&spi->dev, in wilc_spi_rx()
387 ret = -EINVAL; in wilc_spi_rx()
395 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_tx_rx()
405 .delay = { in wilc_spi_tx_rx()
417 dev_err(&spi->dev, "SPI transaction failed\n"); in wilc_spi_tx_rx()
419 dev_err(&spi->dev, in wilc_spi_tx_rx()
422 ret = -EINVAL; in wilc_spi_tx_rx()
430 struct spi_device *spi = to_spi_device(wilc->dev); in spi_data_write()
431 struct wilc_spi *spi_priv = wilc->bus_data; in spi_data_write()
434 u8 cmd, order, crc[2]; in spi_data_write() local
456 cmd = 0xf0; in spi_data_write()
457 cmd |= order; in spi_data_write()
459 if (wilc_spi_tx(wilc, &cmd, 1)) { in spi_data_write()
460 dev_err(&spi->dev, in spi_data_write()
461 "Failed data block cmd write, bus error...\n"); in spi_data_write()
462 result = -EINVAL; in spi_data_write()
470 dev_err(&spi->dev, in spi_data_write()
472 result = -EINVAL; in spi_data_write()
479 if (spi_priv->crc16_enabled) { in spi_data_write()
484 dev_err(&spi->dev, "Failed data block crc write, bus error...\n"); in spi_data_write()
485 result = -EINVAL; in spi_data_write()
494 sz -= nbytes; in spi_data_write()
510 static int wilc_spi_single_read(struct wilc *wilc, u8 cmd, u32 adr, void *b, in wilc_spi_single_read() argument
513 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_single_read()
514 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_single_read()
525 c->cmd_type = cmd; in wilc_spi_single_read()
526 if (cmd == CMD_SINGLE_READ) { in wilc_spi_single_read()
527 c->u.simple_cmd.addr[0] = adr >> 16; in wilc_spi_single_read()
528 c->u.simple_cmd.addr[1] = adr >> 8; in wilc_spi_single_read()
529 c->u.simple_cmd.addr[2] = adr; in wilc_spi_single_read()
530 } else if (cmd == CMD_INTERNAL_READ) { in wilc_spi_single_read()
531 c->u.simple_cmd.addr[0] = adr >> 8; in wilc_spi_single_read()
533 c->u.simple_cmd.addr[0] |= BIT(7); in wilc_spi_single_read()
534 c->u.simple_cmd.addr[1] = adr; in wilc_spi_single_read()
535 c->u.simple_cmd.addr[2] = 0x0; in wilc_spi_single_read()
537 dev_err(&spi->dev, "cmd [%x] not supported\n", cmd); in wilc_spi_single_read()
538 return -EINVAL; in wilc_spi_single_read()
544 if (spi_priv->crc7_enabled) { in wilc_spi_single_read()
545 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_single_read()
551 dev_err(&spi->dev, in wilc_spi_single_read()
554 return -EINVAL; in wilc_spi_single_read()
558 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_single_read()
559 return -EINVAL; in wilc_spi_single_read()
563 if (r->rsp_cmd_type != cmd && !clockless) { in wilc_spi_single_read()
564 if (!spi_priv->probing_crc) in wilc_spi_single_read()
565 dev_err(&spi->dev, in wilc_spi_single_read()
566 "Failed cmd, cmd (%02x), resp (%02x)\n", in wilc_spi_single_read()
567 cmd, r->rsp_cmd_type); in wilc_spi_single_read()
568 return -EINVAL; in wilc_spi_single_read()
571 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { in wilc_spi_single_read()
572 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_single_read()
573 r->status); in wilc_spi_single_read()
574 return -EINVAL; in wilc_spi_single_read()
578 if (WILC_GET_RESP_HDR_START(r->data[i]) == 0xf) in wilc_spi_single_read()
582 dev_err(&spi->dev, "Error, data start missing\n"); in wilc_spi_single_read()
583 return -EINVAL; in wilc_spi_single_read()
586 r_data = (struct wilc_spi_read_rsp_data *)&r->data[i]; in wilc_spi_single_read()
589 memcpy(b, r_data->data, 4); in wilc_spi_single_read()
591 if (!clockless && spi_priv->crc16_enabled) { in wilc_spi_single_read()
592 crc_recv = (r_data->crc[0] << 8) | r_data->crc[1]; in wilc_spi_single_read()
593 crc_calc = crc_itu_t(0xffff, r_data->data, 4); in wilc_spi_single_read()
595 dev_err(&spi->dev, "%s: bad CRC 0x%04x " in wilc_spi_single_read()
598 return -EINVAL; in wilc_spi_single_read()
605 static int wilc_spi_write_cmd(struct wilc *wilc, u8 cmd, u32 adr, u32 data, in wilc_spi_write_cmd() argument
608 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write_cmd()
609 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_write_cmd()
618 c->cmd_type = cmd; in wilc_spi_write_cmd()
619 if (cmd == CMD_INTERNAL_WRITE) { in wilc_spi_write_cmd()
620 c->u.internal_w_cmd.addr[0] = adr >> 8; in wilc_spi_write_cmd()
622 c->u.internal_w_cmd.addr[0] |= BIT(7); in wilc_spi_write_cmd()
624 c->u.internal_w_cmd.addr[1] = adr; in wilc_spi_write_cmd()
625 c->u.internal_w_cmd.data = cpu_to_be32(data); in wilc_spi_write_cmd()
627 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
628 c->u.internal_w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_write_cmd()
629 } else if (cmd == CMD_SINGLE_WRITE) { in wilc_spi_write_cmd()
630 c->u.w_cmd.addr[0] = adr >> 16; in wilc_spi_write_cmd()
631 c->u.w_cmd.addr[1] = adr >> 8; in wilc_spi_write_cmd()
632 c->u.w_cmd.addr[2] = adr; in wilc_spi_write_cmd()
633 c->u.w_cmd.data = cpu_to_be32(data); in wilc_spi_write_cmd()
635 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
636 c->u.w_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_write_cmd()
638 dev_err(&spi->dev, "write cmd [%x] not supported\n", cmd); in wilc_spi_write_cmd()
639 return -EINVAL; in wilc_spi_write_cmd()
642 if (spi_priv->crc7_enabled) in wilc_spi_write_cmd()
648 dev_err(&spi->dev, in wilc_spi_write_cmd()
651 return -EINVAL; in wilc_spi_write_cmd()
655 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_write_cmd()
656 return -EINVAL; in wilc_spi_write_cmd()
664 if (r->rsp_cmd_type != cmd && !clockless) { in wilc_spi_write_cmd()
665 dev_err(&spi->dev, in wilc_spi_write_cmd()
666 "Failed cmd response, cmd (%02x), resp (%02x)\n", in wilc_spi_write_cmd()
667 cmd, r->rsp_cmd_type); in wilc_spi_write_cmd()
668 return -EINVAL; in wilc_spi_write_cmd()
671 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS && !clockless) { in wilc_spi_write_cmd()
672 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_write_cmd()
673 r->status); in wilc_spi_write_cmd()
674 return -EINVAL; in wilc_spi_write_cmd()
680 static int wilc_spi_dma_rw(struct wilc *wilc, u8 cmd, u32 adr, u8 *b, u32 sz) in wilc_spi_dma_rw() argument
682 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_dma_rw()
683 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_dma_rw()
695 c->cmd_type = cmd; in wilc_spi_dma_rw()
696 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_READ) { in wilc_spi_dma_rw()
697 c->u.dma_cmd.addr[0] = adr >> 16; in wilc_spi_dma_rw()
698 c->u.dma_cmd.addr[1] = adr >> 8; in wilc_spi_dma_rw()
699 c->u.dma_cmd.addr[2] = adr; in wilc_spi_dma_rw()
700 c->u.dma_cmd.size[0] = sz >> 8; in wilc_spi_dma_rw()
701 c->u.dma_cmd.size[1] = sz; in wilc_spi_dma_rw()
703 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
704 c->u.dma_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_dma_rw()
705 } else if (cmd == CMD_DMA_EXT_WRITE || cmd == CMD_DMA_EXT_READ) { in wilc_spi_dma_rw()
706 c->u.dma_cmd_ext.addr[0] = adr >> 16; in wilc_spi_dma_rw()
707 c->u.dma_cmd_ext.addr[1] = adr >> 8; in wilc_spi_dma_rw()
708 c->u.dma_cmd_ext.addr[2] = adr; in wilc_spi_dma_rw()
709 c->u.dma_cmd_ext.size[0] = sz >> 16; in wilc_spi_dma_rw()
710 c->u.dma_cmd_ext.size[1] = sz >> 8; in wilc_spi_dma_rw()
711 c->u.dma_cmd_ext.size[2] = sz; in wilc_spi_dma_rw()
713 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
714 c->u.dma_cmd_ext.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_dma_rw()
716 dev_err(&spi->dev, "dma read write cmd [%x] not supported\n", in wilc_spi_dma_rw()
717 cmd); in wilc_spi_dma_rw()
718 return -EINVAL; in wilc_spi_dma_rw()
720 if (spi_priv->crc7_enabled) in wilc_spi_dma_rw()
726 dev_err(&spi->dev, "spi buffer size too small (%d)(%d) (%zu)\n", in wilc_spi_dma_rw()
728 return -EINVAL; in wilc_spi_dma_rw()
732 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_dma_rw()
733 return -EINVAL; in wilc_spi_dma_rw()
737 if (r->rsp_cmd_type != cmd) { in wilc_spi_dma_rw()
738 dev_err(&spi->dev, in wilc_spi_dma_rw()
739 "Failed cmd response, cmd (%02x), resp (%02x)\n", in wilc_spi_dma_rw()
740 cmd, r->rsp_cmd_type); in wilc_spi_dma_rw()
741 return -EINVAL; in wilc_spi_dma_rw()
744 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { in wilc_spi_dma_rw()
745 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_dma_rw()
746 r->status); in wilc_spi_dma_rw()
747 return -EINVAL; in wilc_spi_dma_rw()
750 if (cmd == CMD_DMA_WRITE || cmd == CMD_DMA_EXT_WRITE) in wilc_spi_dma_rw()
765 dev_err(&spi->dev, in wilc_spi_dma_rw()
767 return -EINVAL; in wilc_spi_dma_rw()
771 } while (retry--); in wilc_spi_dma_rw()
777 dev_err(&spi->dev, in wilc_spi_dma_rw()
779 return -EINVAL; in wilc_spi_dma_rw()
785 if (spi_priv->crc16_enabled) { in wilc_spi_dma_rw()
787 dev_err(&spi->dev, in wilc_spi_dma_rw()
789 return -EINVAL; in wilc_spi_dma_rw()
794 dev_err(&spi->dev, "%s: bad CRC 0x%04x " in wilc_spi_dma_rw()
797 return -EINVAL; in wilc_spi_dma_rw()
802 sz -= nbytes; in wilc_spi_dma_rw()
807 static int wilc_spi_special_cmd(struct wilc *wilc, u8 cmd) in wilc_spi_special_cmd() argument
809 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_special_cmd()
810 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_special_cmd()
816 if (cmd != CMD_TERMINATE && cmd != CMD_REPEAT && cmd != CMD_RESET) in wilc_spi_special_cmd()
817 return -EINVAL; in wilc_spi_special_cmd()
822 c->cmd_type = cmd; in wilc_spi_special_cmd()
824 if (cmd == CMD_RESET) in wilc_spi_special_cmd()
825 memset(c->u.simple_cmd.addr, 0xFF, 3); in wilc_spi_special_cmd()
830 if (spi_priv->crc7_enabled) { in wilc_spi_special_cmd()
831 c->u.simple_cmd.crc[0] = wilc_get_crc7(wb, cmd_len); in wilc_spi_special_cmd()
835 dev_err(&spi->dev, "spi buffer size too small (%d) (%d) (%zu)\n", in wilc_spi_special_cmd()
837 return -EINVAL; in wilc_spi_special_cmd()
841 dev_err(&spi->dev, "Failed cmd write, bus error...\n"); in wilc_spi_special_cmd()
842 return -EINVAL; in wilc_spi_special_cmd()
846 if (r->rsp_cmd_type != cmd) { in wilc_spi_special_cmd()
847 if (!spi_priv->probing_crc) in wilc_spi_special_cmd()
848 dev_err(&spi->dev, in wilc_spi_special_cmd()
849 "Failed cmd response, cmd (%02x), resp (%02x)\n", in wilc_spi_special_cmd()
850 cmd, r->rsp_cmd_type); in wilc_spi_special_cmd()
851 return -EINVAL; in wilc_spi_special_cmd()
854 if (r->status != WILC_SPI_COMMAND_STAT_SUCCESS) { in wilc_spi_special_cmd()
855 dev_err(&spi->dev, "Failed cmd state response state (%02x)\n", in wilc_spi_special_cmd()
856 r->status); in wilc_spi_special_cmd()
857 return -EINVAL; in wilc_spi_special_cmd()
864 struct spi_device *spi = to_spi_device(wl->dev); in wilc_spi_reset_cmd_sequence()
865 struct wilc_spi *spi_priv = wl->bus_data; in wilc_spi_reset_cmd_sequence()
867 if (!spi_priv->probing_crc) in wilc_spi_reset_cmd_sequence()
868 dev_err(&spi->dev, "Reset and retry %d %x\n", attempt, addr); in wilc_spi_reset_cmd_sequence()
877 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_read_reg()
879 u8 cmd = CMD_SINGLE_READ; in wilc_spi_read_reg() local
885 cmd = CMD_INTERNAL_READ; in wilc_spi_read_reg()
890 result = wilc_spi_single_read(wilc, cmd, addr, data, clockless); in wilc_spi_read_reg()
900 dev_err(&spi->dev, "Failed cmd, read reg (%08x)...\n", addr); in wilc_spi_read_reg()
909 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_read()
914 return -EINVAL; in wilc_spi_read()
922 dev_err(&spi->dev, "Failed cmd, read block (%08x)...\n", addr); in wilc_spi_read()
930 static int spi_internal_write(struct wilc *wilc, u32 adr, u32 dat) in spi_internal_write() argument
932 struct spi_device *spi = to_spi_device(wilc->dev); in spi_internal_write()
938 dat, 0); in spi_internal_write()
941 dev_err(&spi->dev, "Failed internal write cmd...\n"); in spi_internal_write()
951 struct spi_device *spi = to_spi_device(wilc->dev); in spi_internal_read()
952 struct wilc_spi *spi_priv = wilc->bus_data; in spi_internal_read()
963 if (!spi_priv->probing_crc) in spi_internal_read()
964 dev_err(&spi->dev, "Failed internal read cmd...\n"); in spi_internal_read()
980 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write_reg()
982 u8 cmd = CMD_SINGLE_WRITE; in wilc_spi_write_reg() local
988 cmd = CMD_INTERNAL_WRITE; in wilc_spi_write_reg()
993 result = wilc_spi_write_cmd(wilc, cmd, addr, data, clockless); in wilc_spi_write_reg()
997 dev_err(&spi->dev, "Failed cmd, write reg (%08x)...\n", addr); in wilc_spi_write_reg()
1007 static int spi_data_rsp(struct wilc *wilc, u8 cmd) in spi_data_rsp() argument
1009 struct spi_device *spi = to_spi_device(wilc->dev); in spi_data_rsp()
1019 * second-to-last packet before the one for the final packet. in spi_data_rsp()
1027 dev_err(&spi->dev, "Failed bus error...\n"); in spi_data_rsp()
1031 for (i = sizeof(rsp) - 2; i >= 0; --i) in spi_data_rsp()
1036 dev_err(&spi->dev, in spi_data_rsp()
1039 return -1; in spi_data_rsp()
1046 dev_err(&spi->dev, "Data response error (%02x %02x)\n", in spi_data_rsp()
1048 return -1; in spi_data_rsp()
1055 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_write()
1063 return -EINVAL; in wilc_spi_write()
1069 dev_err(&spi->dev, in wilc_spi_write()
1070 "Failed cmd, write block (%08x)...\n", addr); in wilc_spi_write()
1080 dev_err(&spi->dev, "Failed block data write...\n"); in wilc_spi_write()
1090 dev_err(&spi->dev, "Failed block data rsp...\n"); in wilc_spi_write()
1107 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_reset()
1108 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_reset()
1112 if (result && !spi_priv->probing_crc) in wilc_spi_reset()
1113 dev_err(&spi->dev, "Failed cmd reset\n"); in wilc_spi_reset()
1120 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_is_init()
1122 return spi_priv->isinit; in wilc_spi_is_init()
1127 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_deinit()
1129 spi_priv->isinit = false; in wilc_spi_deinit()
1136 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_init()
1139 if (spi_priv->isinit) { in wilc_spi_init()
1153 spi_priv->isinit = true; in wilc_spi_init()
1160 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_configure_bus_protocol()
1161 struct wilc_spi *spi_priv = wilc->bus_data; in wilc_spi_configure_bus_protocol()
1170 spi_priv->probing_crc = true; in wilc_spi_configure_bus_protocol()
1171 spi_priv->crc7_enabled = enable_crc7; in wilc_spi_configure_bus_protocol()
1172 spi_priv->crc16_enabled = false; /* don't check CRC16 during probing */ in wilc_spi_configure_bus_protocol()
1177 spi_priv->crc7_enabled = !enable_crc7; in wilc_spi_configure_bus_protocol()
1180 dev_err(&spi->dev, "Failed with CRC7 on and off.\n"); in wilc_spi_configure_bus_protocol()
1196 DATA_PKT_LOG_SZ - DATA_PKT_LOG_SZ_MIN); in wilc_spi_configure_bus_protocol()
1201 dev_err(&spi->dev, in wilc_spi_configure_bus_protocol()
1207 spi_priv->crc7_enabled = enable_crc7; in wilc_spi_configure_bus_protocol()
1208 spi_priv->crc16_enabled = enable_crc16; in wilc_spi_configure_bus_protocol()
1210 /* re-read to make sure new settings are in effect: */ in wilc_spi_configure_bus_protocol()
1213 spi_priv->probing_crc = false; in wilc_spi_configure_bus_protocol()
1220 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_validate_chipid()
1229 dev_err(&spi->dev, "Fail cmd read chip id...\n"); in wilc_validate_chipid()
1233 dev_err(&spi->dev, "Unknown chip id 0x%x\n", chipid); in wilc_validate_chipid()
1234 return -ENODEV; in wilc_validate_chipid()
1244 WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, size); in wilc_spi_read_size()
1252 return spi_internal_read(wilc, WILC_SPI_INT_STATUS - WILC_SPI_REG_BASE, in wilc_spi_read_int()
1264 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, in wilc_spi_clear_int_ext()
1270 WILC_SPI_INT_CLEAR - WILC_SPI_REG_BASE, in wilc_spi_clear_int_ext()
1275 retry--; in wilc_spi_clear_int_ext()
1282 struct spi_device *spi = to_spi_device(wilc->dev); in wilc_spi_sync_ext()
1287 dev_err(&spi->dev, "Too many interrupts (%d)...\n", nint); in wilc_spi_sync_ext()
1288 return -EINVAL; in wilc_spi_sync_ext()
1292 * interrupt pin mux select in wilc_spi_sync_ext()
1296 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1303 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()
1313 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1318 for (i = 0; (i < 5) && (nint > 0); i++, nint--) in wilc_spi_sync_ext()
1323 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()
1330 dev_err(&spi->dev, "Failed read reg (%08x)...\n", in wilc_spi_sync_ext()
1335 for (i = 0; (i < 3) && (nint > 0); i++, nint--) in wilc_spi_sync_ext()
1340 dev_err(&spi->dev, "Failed write reg (%08x)...\n", in wilc_spi_sync_ext()