Lines Matching +full:8 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
18 #define MT_CMB_CTRL_XTAL_RDY BIT(22)
19 #define MT_CMB_CTRL_PLL_LD BIT(23)
24 #define MT_EFUSE_CTRL_LDO_OFF_TIME GENMASK(13, 8)
27 #define MT_EFUSE_CTRL_KICK BIT(30)
28 #define MT_EFUSE_CTRL_SEL BIT(31)
34 #define MT_COEXCFG0_COEX_EN BIT(0)
37 #define MT_WLAN_FUN_CTRL_WLAN_EN BIT(0)
38 #define MT_WLAN_FUN_CTRL_WLAN_CLK_EN BIT(1)
39 #define MT_WLAN_FUN_CTRL_WLAN_RESET_RF BIT(2)
41 #define MT_WLAN_FUN_CTRL_WLAN_RESET BIT(3) /* MT76x0 */
42 #define MT_WLAN_FUN_CTRL_CSR_F20M_CKEN BIT(3) /* MT76x2 */
44 #define MT_WLAN_FUN_CTRL_PCIE_CLK_REQ BIT(4)
45 #define MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL BIT(5)
46 #define MT_WLAN_FUN_CTRL_INV_ANT_SEL BIT(6)
47 #define MT_WLAN_FUN_CTRL_WAKE_HOST BIT(7)
49 #define MT_WLAN_FUN_CTRL_THERM_RST BIT(8) /* MT76x2 */
50 #define MT_WLAN_FUN_CTRL_THERM_CKEN BIT(9) /* MT76x2 */
52 #define MT_WLAN_FUN_CTRL_GPIO_IN GENMASK(15, 8) /* MT76x0 */
63 #define MT_XO_CTRL5_C2_VAL GENMASK(14, 8)
66 #define MT_XO_CTRL6_C2_CTRL GENMASK(14, 8)
71 #define MT_WLAN_MTC_CTRL_MTCMOS_PWR_UP BIT(0)
72 #define MT_WLAN_MTC_CTRL_PWR_ACK BIT(12)
73 #define MT_WLAN_MTC_CTRL_PWR_ACK_S BIT(13)
75 #define MT_WLAN_MTC_CTRL_PBF_MEM_PD BIT(20)
76 #define MT_WLAN_MTC_CTRL_FCE_MEM_PD BIT(21)
77 #define MT_WLAN_MTC_CTRL_TSO_MEM_PD BIT(22)
78 #define MT_WLAN_MTC_CTRL_BBP_MEM_RB BIT(24)
79 #define MT_WLAN_MTC_CTRL_PBF_MEM_RB BIT(25)
80 #define MT_WLAN_MTC_CTRL_FCE_MEM_RB BIT(26)
81 #define MT_WLAN_MTC_CTRL_TSO_MEM_RB BIT(27)
82 #define MT_WLAN_MTC_CTRL_STATE_UP BIT(28)
87 #define MT_INT_RX_DONE(_n) BIT(_n)
90 #define MT_INT_TX_DONE(_n) BIT(_n + 4)
91 #define MT_INT_RX_COHERENT BIT(16)
92 #define MT_INT_TX_COHERENT BIT(17)
93 #define MT_INT_ANY_COHERENT BIT(18)
94 #define MT_INT_MCU_CMD BIT(19)
95 #define MT_INT_TBTT BIT(20)
96 #define MT_INT_PRE_TBTT BIT(21)
97 #define MT_INT_TX_STAT BIT(22)
98 #define MT_INT_AUTO_WAKEUP BIT(23)
99 #define MT_INT_GPTIMER BIT(24)
100 #define MT_INT_RXDELAYINT BIT(26)
101 #define MT_INT_TXDELAYINT BIT(27)
104 #define MT_WPDMA_GLO_CFG_TX_DMA_EN BIT(0)
105 #define MT_WPDMA_GLO_CFG_TX_DMA_BUSY BIT(1)
106 #define MT_WPDMA_GLO_CFG_RX_DMA_EN BIT(2)
107 #define MT_WPDMA_GLO_CFG_RX_DMA_BUSY BIT(3)
109 #define MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE BIT(6)
110 #define MT_WPDMA_GLO_CFG_BIG_ENDIAN BIT(7)
111 #define MT_WPDMA_GLO_CFG_HDR_SEG_LEN GENMASK(15, 8)
112 #define MT_WPDMA_GLO_CFG_CLK_GATE_DIS BIT(30)
113 #define MT_WPDMA_GLO_CFG_RX_2B_OFFSET BIT(31)
141 #define MT_USB_DMA_CFG_RX_BULK_AGG_LMT GENMASK(15, 8)
142 #define MT_USB_DMA_CFG_PHY_CLR BIT(16)
143 #define MT_USB_DMA_CFG_TX_CLR BIT(19)
144 #define MT_USB_DMA_CFG_TXOP_HALT BIT(20)
145 #define MT_USB_DMA_CFG_RX_BULK_AGG_EN BIT(21)
146 #define MT_USB_DMA_CFG_RX_BULK_EN BIT(22)
147 #define MT_USB_DMA_CFG_TX_BULK_EN BIT(23)
148 #define MT_USB_DMA_CFG_UDMA_RX_WL_DROP BIT(25)
150 #define MT_USB_DMA_CFG_RX_BUSY BIT(30)
151 #define MT_USB_DMA_CFG_TX_BUSY BIT(31)
163 #define MT_TX_HW_QUEUE_MCU 8
167 #define MT_PBF_SYS_CTRL_MCU_RESET BIT(0)
168 #define MT_PBF_SYS_CTRL_DMA_RESET BIT(1)
169 #define MT_PBF_SYS_CTRL_MAC_RESET BIT(2)
170 #define MT_PBF_SYS_CTRL_PBF_RESET BIT(3)
171 #define MT_PBF_SYS_CTRL_ASY_RESET BIT(4)
174 #define MT_PBF_CFG_TX0Q_EN BIT(0)
175 #define MT_PBF_CFG_TX1Q_EN BIT(1)
176 #define MT_PBF_CFG_TX2Q_EN BIT(2)
177 #define MT_PBF_CFG_TX3Q_EN BIT(3)
178 #define MT_PBF_CFG_RX0Q_EN BIT(4)
179 #define MT_PBF_CFG_RX_DROP_EN BIT(8)
192 #define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8)
194 #define MT_RF_CSR_CFG_WR BIT(30)
195 #define MT_RF_CSR_CFG_KICK BIT(31)
205 #define MT_RF_CTRL_WRITE BIT(12)
206 #define MT_RF_CTRL_BUSY BIT(13)
207 #define MT_RF_CTRL_IDX BIT(16)
216 #define MT_FCE_L2_STUFF_HT_L2_EN BIT(0)
217 #define MT_FCE_L2_STUFF_QOS_L2_EN BIT(1)
218 #define MT_FCE_L2_STUFF_RX_STUFF_EN BIT(2)
219 #define MT_FCE_L2_STUFF_TX_STUFF_EN BIT(3)
220 #define MT_FCE_L2_STUFF_WR_MPDU_LEN_EN BIT(4)
221 #define MT_FCE_L2_STUFF_MVINV_BSWAP BIT(5)
222 #define MT_FCE_L2_STUFF_TS_CMD_QSEL_EN GENMASK(15, 8)
241 #define MT_MAC_SYS_CTRL_RESET_CSR BIT(0)
242 #define MT_MAC_SYS_CTRL_RESET_BBP BIT(1)
243 #define MT_MAC_SYS_CTRL_ENABLE_TX BIT(2)
244 #define MT_MAC_SYS_CTRL_ENABLE_RX BIT(3)
255 #define MT_MAC_BSSID_DW1_MBSS_LOCAL_BIT BIT(21)
256 #define MT_MAC_BSSID_DW1_MBSS_MODE_B2 BIT(22)
257 #define MT_MAC_BSSID_DW1_MBEACON_N_B3 BIT(23)
265 #define MT_BBP_CSR_CFG_REG_NUM GENMASK(15, 8)
266 #define MT_BBP_CSR_CFG_READ BIT(16)
267 #define MT_BBP_CSR_CFG_BUSY BIT(17)
268 #define MT_BBP_CSR_CFG_PAR_DUR BIT(18)
269 #define MT_BBP_CSR_CFG_RW_MODE BIT(19)
279 #define MT_WCID_DROP_MASK(_n) BIT((_n) % 32)
284 #define MT_MAC_APC_BSSID_L(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8))
285 #define MT_MAC_APC_BSSID_H(_n) (MT_MAC_APC_BSSID_BASE + ((_n) * 8 + 4))
287 #define MT_MAC_APC_BSSID0_H_EN BIT(16)
291 #define MT_XIFS_TIME_CFG_OFDM_SIFS GENMASK(15, 8)
294 #define MT_XIFS_TIME_CFG_BB_RXEND_EN BIT(29)
298 #define MT_BKOFF_SLOT_CFG_CC_DELAY GENMASK(11, 8)
302 #define MT_BEACON_TIME_CFG_TIMER_EN BIT(16)
304 #define MT_BEACON_TIME_CFG_TBTT_EN BIT(19)
305 #define MT_BEACON_TIME_CFG_BEACON_TX BIT(20)
316 #define MT_INT_TIMER_EN_PRE_TBTT_EN BIT(0)
317 #define MT_INT_TIMER_EN_GP_TIMER_EN BIT(1)
320 #define MT_MAC_STATUS_TX BIT(0)
321 #define MT_MAC_STATUS_RX BIT(1)
339 #define MT_EDCA_CFG_AIFSN GENMASK(11, 8)
350 #define MT_TX_BAND_CFG_UPPER_40M BIT(0)
351 #define MT_TX_BAND_CFG_5G BIT(1)
352 #define MT_TX_BAND_CFG_2G BIT(2)
367 #define MT_TXOP_EXT_CCA_DLY GENMASK(15, 8)
372 #define MT_TX_RTS_CFG_THRESH GENMASK(23, 8)
373 #define MT_TX_RTS_FALLBACK BIT(24)
391 #define MT_PROT_CTRL_RTS_CTS BIT(16)
392 #define MT_PROT_CTRL_CTS2SELF BIT(17)
393 #define MT_PROT_NAV_SHORT BIT(18)
394 #define MT_PROT_NAV_LONG BIT(19)
395 #define MT_PROT_TXOP_ALLOW_CCK BIT(20)
396 #define MT_PROT_TXOP_ALLOW_OFDM BIT(21)
397 #define MT_PROT_TXOP_ALLOW_MM20 BIT(22)
398 #define MT_PROT_TXOP_ALLOW_MM40 BIT(23)
399 #define MT_PROT_TXOP_ALLOW_GF20 BIT(24)
400 #define MT_PROT_TXOP_ALLOW_GF40 BIT(25)
401 #define MT_PROT_RTS_THR_EN BIT(26)
418 #define MT_TX_FBK_LIMIT_AMPDU_FBK GENMASK(15, 8)
419 #define MT_TX_FBK_LIMIT_MPDU_UP_CLEAR BIT(16)
420 #define MT_TX_FBK_LIMIT_AMPDU_UP_CLEAR BIT(17)
421 #define MT_TX_FBK_LIMIT_RATE_LUT BIT(18)
429 #define MT_TX_ALC_CFG_0_CH_INIT_1 GENMASK(13, 8)
451 #define MT_RX_FILTR_CFG_CRC_ERR BIT(0)
452 #define MT_RX_FILTR_CFG_PHY_ERR BIT(1)
453 #define MT_RX_FILTR_CFG_PROMISC BIT(2)
454 #define MT_RX_FILTR_CFG_OTHER_BSS BIT(3)
455 #define MT_RX_FILTR_CFG_VER_ERR BIT(4)
456 #define MT_RX_FILTR_CFG_MCAST BIT(5)
457 #define MT_RX_FILTR_CFG_BCAST BIT(6)
458 #define MT_RX_FILTR_CFG_DUP BIT(7)
459 #define MT_RX_FILTR_CFG_CFACK BIT(8)
460 #define MT_RX_FILTR_CFG_CFEND BIT(9)
461 #define MT_RX_FILTR_CFG_ACK BIT(10)
462 #define MT_RX_FILTR_CFG_CTS BIT(11)
463 #define MT_RX_FILTR_CFG_RTS BIT(12)
464 #define MT_RX_FILTR_CFG_PSPOLL BIT(13)
465 #define MT_RX_FILTR_CFG_BA BIT(14)
466 #define MT_RX_FILTR_CFG_BAR BIT(15)
467 #define MT_RX_FILTR_CFG_CTRL_RSV BIT(16)
471 #define MT_AUTO_RSP_PREAMB_SHORT BIT(4)
477 #define MT_RX_PARSER_RX_SET_NAV_ALL BIT(0)
484 #define MT_EXT_CCA_CFG_CCA_MASK GENMASK(11, 8)
504 * MT_TX_STAT_FIFO_ETXBF BIT(27)
505 * MT_TX_STAT_FIFO_SND BIT(28)
506 * MT_TX_STAT_FIFO_ITXBF BIT(29)
507 * However, tests show that b16-31 have the same layout as TXWI rate_ctl
511 #define MT_TX_STAT_FIFO_VALID BIT(0)
513 #define MT_TX_STAT_FIFO_SUCCESS BIT(5)
514 #define MT_TX_STAT_FIFO_AGGR BIT(6)
515 #define MT_TX_STAT_FIFO_ACKREQ BIT(7)
516 #define MT_TX_STAT_FIFO_WCID GENMASK(15, 8)
527 #define MT_TX_AGG_CNT(_id) ((_id) < 8 ? \
529 MT_TX_AGG_CNT_BASE1 + ((_id - 8) << 2))
553 #define MT_BBP_AGC_R0_CTRL_CHAN GENMASK(9, 8)
560 #define MT_BBP_AGC_GAIN GENMASK(14, 8)
563 #define MT_BBP_AGC20_RSSI1 GENMASK(15, 8)
568 #define MT_WCID_ADDR(_n) (MT_WCID_ADDR_BASE + (_n) * 8)
576 #define MT_WCID_IV(_n) (MT_WCID_IV_BASE + (_n) * 8)
581 #define MT_WCID_ATTR_PAIRWISE BIT(0)
585 #define MT_WCID_ATTR_PKEY_MODE_EXT BIT(10)
586 #define MT_WCID_ATTR_BSS_IDX_EXT BIT(11)
587 #define MT_WCID_ATTR_WAPI_MCBC BIT(15)
597 ((_bss & 8) ? MT_SKEY_1(_bss, _idx) : MT_SKEY_0(_bss, _idx))
606 ((_bss & 8) ? MT_SKEY_MODE_1(_bss) : MT_SKEY_MODE_0(_bss))