383 	mdev->q_rx[MT_RXQ_RRO_IND].flags = MT_WED_RRO_Q_IND;  in mt7996_dma_rro_init()
384 	mdev->q_rx[MT_RXQ_RRO_IND].wed = &mdev->mmio.wed;  in mt7996_dma_rro_init()
385 	ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_RRO_IND],  in mt7996_dma_rro_init()
393 	mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND0].flags =  in mt7996_dma_rro_init()
395 	mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND0].wed = &mdev->mmio.wed;  in mt7996_dma_rro_init()
396 	ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND0],  in mt7996_dma_rro_init()
406 		mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND1].flags =  in mt7996_dma_rro_init()
408 		mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND1].wed = &mdev->mmio.wed;  in mt7996_dma_rro_init()
409 		ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND1],  in mt7996_dma_rro_init()
420 		mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND2].flags =  in mt7996_dma_rro_init()
422 		mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND2].wed = &mdev->mmio.wed;  in mt7996_dma_rro_init()
423 		ret = mt76_queue_alloc(dev, &mdev->q_rx[MT_RXQ_MSDU_PAGE_BAND2],  in mt7996_dma_rro_init()
493 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU],  in mt7996_dma_init()
502 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MCU_WA],  in mt7996_dma_init()
512 		dev->mt76.q_rx[MT_RXQ_MAIN].flags = MT_WED_Q_RX(0);  in mt7996_dma_init()
513 		dev->mt76.q_rx[MT_RXQ_MAIN].wed = wed;  in mt7996_dma_init()
516 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN],  in mt7996_dma_init()
526 		dev->mt76.q_rx[MT_RXQ_MAIN_WA].flags = MT_WED_Q_TXFREE;  in mt7996_dma_init()
527 		dev->mt76.q_rx[MT_RXQ_MAIN_WA].wed = wed;  in mt7996_dma_init()
530 	ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_MAIN_WA],  in mt7996_dma_init()
541 		ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2],  in mt7996_dma_init()
553 			dev->mt76.q_rx[MT_RXQ_BAND2_WA].flags = MT_WED_Q_TXFREE;  in mt7996_dma_init()
554 			dev->mt76.q_rx[MT_RXQ_BAND2_WA].wed = wed_hif2;  in mt7996_dma_init()
557 		ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND2_WA],  in mt7996_dma_init()
567 		ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1],  in mt7996_dma_init()
577 		ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_BAND1_WA],  in mt7996_dma_init()
589 		dev->mt76.q_rx[MT_RXQ_RRO_BAND0].flags =  in mt7996_dma_init()
591 		dev->mt76.q_rx[MT_RXQ_RRO_BAND0].wed = wed;  in mt7996_dma_init()
592 		ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_RRO_BAND0],  in mt7996_dma_init()
601 		dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].flags = MT_WED_Q_TXFREE;  in mt7996_dma_init()
602 		dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0].wed = wed;  in mt7996_dma_init()
604 		ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_TXFREE_BAND0],  in mt7996_dma_init()
614 			dev->mt76.q_rx[MT_RXQ_RRO_BAND2].flags =  in mt7996_dma_init()
616 			dev->mt76.q_rx[MT_RXQ_RRO_BAND2].wed = wed;  in mt7996_dma_init()
617 			ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_RRO_BAND2],  in mt7996_dma_init()
627 				dev->mt76.q_rx[MT_RXQ_TXFREE_BAND2].flags = MT_WED_Q_TXFREE;  in mt7996_dma_init()
628 				dev->mt76.q_rx[MT_RXQ_TXFREE_BAND2].wed = wed_hif2;  in mt7996_dma_init()
630 			ret = mt76_queue_alloc(dev, &dev->mt76.q_rx[MT_RXQ_TXFREE_BAND2],  in mt7996_dma_init()
683 		mt76_queue_rx_cleanup(dev, &dev->mt76.q_rx[i]);  in mt7996_dma_reset()
714 			if (mt76_queue_is_wed_rro(&dev->mt76.q_rx[i]) ||  in mt7996_dma_reset()
715 			    mt76_queue_is_wed_tx_free(&dev->mt76.q_rx[i]))  in mt7996_dma_reset()
718 		mt76_queue_reset(dev, &dev->mt76.q_rx[i]);  in mt7996_dma_reset()