176 	u32 hif1_ofs = 0;  in mt7996_dma_disable()  local
179 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);  in mt7996_dma_disable()
191 			mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs,  in mt7996_dma_disable()
195 			mt76_set(dev, MT_WFDMA0_RST + hif1_ofs,  in mt7996_dma_disable()
210 		mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,  in mt7996_dma_disable()
222 	u32 hif1_ofs = 0;  in mt7996_dma_start()  local
226 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);  in mt7996_dma_start()
244 			mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,  in mt7996_dma_start()
280 	u32 hif1_ofs = 0;  in mt7996_dma_enable()  local
283 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);  in mt7996_dma_enable()
288 		mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0);  in mt7996_dma_enable()
296 		mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0);  in mt7996_dma_enable()
297 		mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG1 + hif1_ofs, 0);  in mt7996_dma_enable()
298 		mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG2 + hif1_ofs, 0);  in mt7996_dma_enable()
311 		mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs,  in mt7996_dma_enable()
336 		mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT0 + hif1_ofs,  in mt7996_dma_enable()
341 		mt76_set(dev, WF_WFDMA0_GLO_CFG_EXT1 + hif1_ofs,  in mt7996_dma_enable()
353 		mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_45_TH + hif1_ofs, 0xc000c);  in mt7996_dma_enable()
354 		mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_67_TH + hif1_ofs, 0x10008);  in mt7996_dma_enable()
355 		mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_89_TH + hif1_ofs, 0x10008);  in mt7996_dma_enable()
356 		mt76_wr(dev, MT_WFDMA0_PAUSE_RX_Q_RRO_TH + hif1_ofs, 0x20);  in mt7996_dma_enable()
365 			mt76_set(dev, MT_WFDMA0_RX_INT_PCIE_SEL + hif1_ofs,  in mt7996_dma_enable()
447 	u32 hif1_ofs = 0;  in mt7996_dma_init()  local
455 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);  in mt7996_dma_init()
540 		rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND2) + hif1_ofs;  in mt7996_dma_init()
566 		rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1) + hif1_ofs;  in mt7996_dma_init()
576 		rx_base = MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs;  in mt7996_dma_init()
621 					       MT_RXQ_RING_BASE(MT_RXQ_RRO_BAND2) + hif1_ofs);  in mt7996_dma_init()
634 					       MT_RXQ_RING_BASE(MT_RXQ_TXFREE_BAND2) + hif1_ofs);  in mt7996_dma_init()
657 	u32 hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);  in mt7996_dma_reset()  local
665 		mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,  in mt7996_dma_reset()