Lines Matching +full:0 +full:x644
8 #define MT_MCU_WFDMA1_BASE 0x3000
11 #define MT_MCU_INT_EVENT MT_MCU_WFDMA1(0x108)
12 #define MT_MCU_INT_EVENT_DMA_STOPPED BIT(0)
17 #define MT_PLE_BASE 0x820c0000
20 #define MT_PLE_FL_Q0_CTRL MT_PLE(0x3e0)
21 #define MT_PLE_FL_Q1_CTRL MT_PLE(0x3e4)
22 #define MT_PLE_FL_Q2_CTRL MT_PLE(0x3e8)
23 #define MT_PLE_FL_Q3_CTRL MT_PLE(0x3ec)
25 #define MT_PLE_AC_QEMPTY(_n) MT_PLE(0x500 + 0x40 * (_n))
26 #define MT_PLE_AMSDU_PACK_MSDU_CNT(n) MT_PLE(0x10e0 + ((n) << 2))
28 /* TMAC: band 0(0x21000), band 1(0xa1000) */
29 #define MT_WF_TMAC_BASE(_band) ((_band) ? 0x820f4000 : 0x820e4000)
32 #define MT_TMAC_TCR0(_band) MT_WF_TMAC(_band, 0)
35 #define MT_TMAC_CDTR(_band) MT_WF_TMAC(_band, 0x090)
36 #define MT_TMAC_ODTR(_band) MT_WF_TMAC(_band, 0x094)
37 #define MT_TIMEOUT_VAL_PLCP GENMASK(15, 0)
40 #define MT_TMAC_ICR0(_band) MT_WF_TMAC(_band, 0x0a4)
41 #define MT_IFS_EIFS GENMASK(8, 0)
46 #define MT_TMAC_CTCR0(_band) MT_WF_TMAC(_band, 0x0f4)
47 #define MT_TMAC_CTCR0_INS_DDLMT_REFTIME GENMASK(5, 0)
51 #define MT_TMAC_TRCR0(_band) MT_WF_TMAC(_band, 0x09c)
52 #define MT_TMAC_TFCR0(_band) MT_WF_TMAC(_band, 0x1e0)
54 #define MT_WF_DMA_BASE(_band) ((_band) ? 0x820f7000 : 0x820e7000)
57 #define MT_DMA_DCR0(_band) MT_WF_DMA(_band, 0x000)
61 /* WTBLOFF TOP: band 0(0x820e9000),band 1(0x820f9000) */
62 #define MT_WTBLOFF_TOP_BASE(_band) ((_band) ? 0x820f9000 : 0x820e9000)
65 #define MT_WTBLOFF_TOP_RSCR(_band) MT_WTBLOFF_TOP(_band, 0x008)
69 /* LPON: band 0(0x24200), band 1(0xa4200) */
70 #define MT_WF_LPON_BASE(_band) ((_band) ? 0x820fb000 : 0x820eb000)
73 #define MT_LPON_UTTR0(_band) MT_WF_LPON(_band, 0x080)
74 #define MT_LPON_UTTR1(_band) MT_WF_LPON(_band, 0x084)
76 #define MT_LPON_TCR(_band, n) MT_WF_LPON(_band, 0x0a8 + (n) * 4)
77 #define MT_LPON_TCR_SW_MODE GENMASK(1, 0)
78 #define MT_LPON_TCR_SW_WRITE BIT(0)
80 /* ETBF: band 0(0x24000), band 1(0xa4000) */
81 #define MT_WF_ETBF_BASE(_band) ((_band) ? 0x820fa000 : 0x820ea000)
84 #define MT_ETBF_TX_APP_CNT(_band) MT_WF_ETBF(_band, 0x150)
86 #define MT_ETBF_TX_EBF_CNT GENMASK(15, 0)
88 #define MT_ETBF_RX_FB_CNT(_band) MT_WF_ETBF(_band, 0x158)
92 #define MT_ETBF_RX_FB_HT GENMASK(7, 0)
94 /* MIB: band 0(0x24800), band 1(0xa4800) */
95 #define MT_WF_MIB_BASE(_band) ((_band) ? 0x820fd000 : 0x820ed000)
98 #define MT_MIB_SCR1(_band) MT_WF_MIB(_band, 0x004)
102 #define MT_MIB_SDR3(_band) MT_WF_MIB(_band, 0x698)
105 #define MT_MIB_SDR5(_band) MT_WF_MIB(_band, 0x780)
107 #define MT_MIB_SDR9(_band) MT_WF_MIB(_band, 0x02c)
108 #define MT_MIB_SDR9_BUSY_MASK GENMASK(23, 0)
110 #define MT_MIB_SDR12(_band) MT_WF_MIB(_band, 0x558)
111 #define MT_MIB_SDR14(_band) MT_WF_MIB(_band, 0x564)
112 #define MT_MIB_SDR15(_band) MT_WF_MIB(_band, 0x568)
114 #define MT_MIB_SDR16(_band) MT_WF_MIB(_band, 0x048)
115 #define MT_MIB_SDR16_BUSY_MASK GENMASK(23, 0)
117 #define MT_MIB_SDR22(_band) MT_WF_MIB(_band, 0x770)
118 #define MT_MIB_SDR23(_band) MT_WF_MIB(_band, 0x774)
119 #define MT_MIB_SDR31(_band) MT_WF_MIB(_band, 0x55c)
121 #define MT_MIB_SDR32(_band) MT_WF_MIB(_band, 0x7a8)
123 #define MT_MIB_SDR9_EBF_CNT_MASK GENMASK(15, 0)
125 #define MT_MIB_SDR34(_band) MT_WF_MIB(_band, 0x090)
126 #define MT_MIB_MU_BF_TX_CNT GENMASK(15, 0)
128 #define MT_MIB_SDR36(_band) MT_WF_MIB(_band, 0x054)
129 #define MT_MIB_SDR36_TXTIME_MASK GENMASK(23, 0)
130 #define MT_MIB_SDR37(_band) MT_WF_MIB(_band, 0x058)
131 #define MT_MIB_SDR37_RXTIME_MASK GENMASK(23, 0)
133 #define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0)
134 #define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4)
135 #define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc)
137 #define MT_MIB_MB_SDR0(_band, n) MT_WF_MIB(_band, 0x100 + ((n) << 4))
140 #define MT_MIB_MB_BSDR0(_band) MT_WF_MIB(_band, 0x688)
141 #define MT_MIB_RTS_COUNT_MASK GENMASK(15, 0)
142 #define MT_MIB_MB_BSDR1(_band) MT_WF_MIB(_band, 0x690)
143 #define MT_MIB_RTS_FAIL_COUNT_MASK GENMASK(15, 0)
144 #define MT_MIB_MB_BSDR2(_band) MT_WF_MIB(_band, 0x518)
145 #define MT_MIB_BA_FAIL_COUNT_MASK GENMASK(15, 0)
146 #define MT_MIB_MB_BSDR3(_band) MT_WF_MIB(_band, 0x520)
147 #define MT_MIB_ACK_FAIL_COUNT_MASK GENMASK(15, 0)
149 #define MT_MIB_MB_SDR2(_band, n) MT_WF_MIB(_band, 0x108 + ((n) << 4))
150 #define MT_MIB_FRAME_RETRIES_COUNT_MASK GENMASK(15, 0)
152 #define MT_TX_AGG_CNT(_band, n) MT_WF_MIB(_band, 0x7dc + ((n) << 2))
153 #define MT_TX_AGG_CNT2(_band, n) MT_WF_MIB(_band, 0x7ec + ((n) << 2))
154 #define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x0b0 + ((n) << 2))
155 #define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
157 #define MT_WTBLON_TOP_BASE 0x820d4000
162 #define MT_WTBL_ITCR MT_WTBLON_TOP(0x3b0)
165 #define MT_WTBL_ITDR0 MT_WTBLON_TOP(0x3b8)
166 #define MT_WTBL_ITDR1 MT_WTBLON_TOP(0x3bc)
169 #define MT_WTBL_BASE 0x820d8000
176 /* AGG: band 0(0x20800), band 1(0xa0800) */
177 #define MT_WF_AGG_BASE(_band) ((_band) ? 0x820f2000 : 0x820e2000)
180 #define MT_AGG_AWSCR0(_band, _n) MT_WF_AGG(_band, 0x05c + (_n) * 4)
181 #define MT_AGG_PCR0(_band, _n) MT_WF_AGG(_band, 0x06c + (_n) * 4)
182 #define MT_AGG_PCR0_MM_PROT BIT(0)
192 #define MT_AGG_PCR1_RTS0_LEN_THRES GENMASK(19, 0)
194 #define MT_AGG_ACR0(_band) MT_WF_AGG(_band, 0x084)
195 #define MT_AGG_ACR_CFEND_RATE GENMASK(13, 0)
198 #define MT_AGG_MRCR(_band) MT_WF_AGG(_band, 0x098)
204 #define MT_AGG_ATCR1(_band) MT_WF_AGG(_band, 0x0f0)
205 #define MT_AGG_ATCR3(_band) MT_WF_AGG(_band, 0x0f4)
207 /* ARB: band 0(0x20c00), band 1(0xa0c00) */
208 #define MT_WF_ARB_BASE(_band) ((_band) ? 0x820f3000 : 0x820e3000)
211 #define MT_ARB_SCR(_band) MT_WF_ARB(_band, 0x080)
215 #define MT_ARB_DRNGR0(_band, _n) MT_WF_ARB(_band, 0x194 + (_n) * 4)
217 /* RMAC: band 0(0x21400), band 1(0xa1400) */
218 #define MT_WF_RMAC_BASE(_band) ((_band) ? 0x820f5000 : 0x820e5000)
221 #define MT_WF_RFCR(_band) MT_WF_RMAC(_band, 0x000)
222 #define MT_WF_RFCR_DROP_STBC_MULTI BIT(0)
244 #define MT_WF_RFCR1(_band) MT_WF_RMAC(_band, 0x004)
251 #define MT_WF_RMAC_MIB_TIME0(_band) MT_WF_RMAC(_band, 0x03c4)
255 #define MT_WF_RMAC_MIB_AIRTIME14(_band) MT_WF_RMAC(_band, 0x03b8)
256 #define MT_MIB_OBSSTIME_MASK GENMASK(23, 0)
257 #define MT_WF_RMAC_MIB_AIRTIME0(_band) MT_WF_RMAC(_band, 0x0380)
260 #define MT_WFDMA0_BASE 0xd4000
263 #define MT_WFDMA0_RST MT_WFDMA0(0x100)
267 #define MT_WFDMA0_BUSY_ENA MT_WFDMA0(0x13c)
268 #define MT_WFDMA0_BUSY_ENA_TX_FIFO0 BIT(0)
272 #define MT_MCU_CMD MT_WFDMA0(0x1f0)
273 #define MT_MCU_CMD_WAKE_RX_PCIE BIT(0)
281 #define MT_MCU2HOST_SW_INT_ENA MT_WFDMA0(0x1f4)
283 #define MT_WFDMA0_HOST_INT_STA MT_WFDMA0(0x200)
284 #define HOST_RX_DONE_INT_STS0 BIT(0) /* Rx mcu */
290 #define MT_WFDMA0_GLO_CFG MT_WFDMA0(0x208)
291 #define MT_WFDMA0_GLO_CFG_TX_DMA_EN BIT(0)
307 #define HOST_RX_DONE_INT_ENA0 BIT(0)
326 #define MT_WFDMA0_RST_DTX_PTR MT_WFDMA0(0x20c)
327 #define MT_WFDMA0_RST_DRX_PTR MT_WFDMA0(0x280)
328 #define MT_WFDMA0_INT_RX_PRI MT_WFDMA0(0x298)
329 #define MT_WFDMA0_INT_TX_PRI MT_WFDMA0(0x29c)
330 #define MT_WFDMA0_GLO_CFG_EXT0 MT_WFDMA0(0x2b0)
332 #define MT_WFDMA0_PRI_DLY_INT_CFG0 MT_WFDMA0(0x2f0)
334 #define MT_WFDMA0_TX_RING0_EXT_CTRL MT_WFDMA0(0x600)
335 #define MT_WFDMA0_TX_RING1_EXT_CTRL MT_WFDMA0(0x604)
336 #define MT_WFDMA0_TX_RING2_EXT_CTRL MT_WFDMA0(0x608)
337 #define MT_WFDMA0_TX_RING3_EXT_CTRL MT_WFDMA0(0x60c)
338 #define MT_WFDMA0_TX_RING4_EXT_CTRL MT_WFDMA0(0x610)
339 #define MT_WFDMA0_TX_RING5_EXT_CTRL MT_WFDMA0(0x614)
340 #define MT_WFDMA0_TX_RING6_EXT_CTRL MT_WFDMA0(0x618)
341 #define MT_WFDMA0_TX_RING15_EXT_CTRL MT_WFDMA0(0x63c)
342 #define MT_WFDMA0_TX_RING16_EXT_CTRL MT_WFDMA0(0x640)
343 #define MT_WFDMA0_TX_RING17_EXT_CTRL MT_WFDMA0(0x644)
345 #define MT_WPDMA0_MAX_CNT_MASK GENMASK(7, 0)
348 #define MT_WFDMA0_RX_RING0_EXT_CTRL MT_WFDMA0(0x680)
349 #define MT_WFDMA0_RX_RING1_EXT_CTRL MT_WFDMA0(0x684)
350 #define MT_WFDMA0_RX_RING2_EXT_CTRL MT_WFDMA0(0x688)
351 #define MT_WFDMA0_RX_RING3_EXT_CTRL MT_WFDMA0(0x68c)
352 #define MT_WFDMA0_RX_RING4_EXT_CTRL MT_WFDMA0(0x690)
353 #define MT_WFDMA0_RX_RING5_EXT_CTRL MT_WFDMA0(0x694)
354 #define MT_WFDMA0_RX_RING6_EXT_CTRL MT_WFDMA0(0x698)
355 #define MT_WFDMA0_RX_RING7_EXT_CTRL MT_WFDMA0(0x69c)
357 #define MT_TX_RING_BASE MT_WFDMA0(0x300)
358 #define MT_RX_EVENT_RING_BASE MT_WFDMA0(0x500)
361 #define MT_WFDMA_EXT_CSR_BASE 0xd7000
363 #define MT_WFDMA_EXT_CSR_HIF_MISC MT_WFDMA_EXT_CSR(0x44)
364 #define MT_WFDMA_EXT_CSR_HIF_MISC_BUSY BIT(0)
366 #define MT_SWDEF_BASE 0x41f200
368 #define MT_SWDEF_MODE MT_SWDEF(0x3c)
369 #define MT_SWDEF_NORMAL_MODE 0
373 #define MT_TOP_BASE 0x18060000
376 #define MT_TOP_LPCR_HOST_BAND0 MT_TOP(0x10)
377 #define MT_TOP_LPCR_HOST_FW_OWN BIT(0)
380 #define MT_TOP_MISC MT_TOP(0xf0)
381 #define MT_TOP_MISC_FW_STATE GENMASK(2, 0)
383 #define MT_MCU_WPDMA0_BASE 0x54000000
386 #define MT_WFDMA_DUMMY_CR MT_MCU_WPDMA0(0x120)
389 #define MT_CBTOP_RGU(ofs) (0x70002000 + (ofs))
390 #define MT_CBTOP_RGU_WF_SUBSYS_RST MT_CBTOP_RGU(0x600)
391 #define MT_CBTOP_RGU_WF_SUBSYS_RST_WF_WHOLE_PATH BIT(0)
393 #define MT_HW_BOUND 0x70010020
394 #define MT_HW_CHIPID 0x70010200
395 #define MT_HW_REV 0x70010204
397 #define MT_HW_EMI_CTL 0x18011100
400 #define MT_PCIE_MAC_BASE 0x10000
402 #define MT_PCIE_MAC_INT_ENABLE MT_PCIE_MAC(0x188)
403 #define MT_PCIE_MAC_PM MT_PCIE_MAC(0x194)
406 #define MT_DMA_SHDL(ofs) (0x7c026000 + (ofs))
407 #define MT_DMASHDL_SW_CONTROL MT_DMA_SHDL(0x004)
409 #define MT_DMASHDL_OPTIONAL MT_DMA_SHDL(0x008)
410 #define MT_DMASHDL_PAGE MT_DMA_SHDL(0x00c)
412 #define MT_DMASHDL_REFILL MT_DMA_SHDL(0x010)
414 #define MT_DMASHDL_PKT_MAX_SIZE MT_DMA_SHDL(0x01c)
415 #define MT_DMASHDL_PKT_MAX_SIZE_PLE GENMASK(11, 0)
418 #define MT_DMASHDL_GROUP_QUOTA(_n) MT_DMA_SHDL(0x020 + ((_n) << 2))
419 #define MT_DMASHDL_GROUP_QUOTA_MIN GENMASK(11, 0)
422 #define MT_DMASHDL_Q_MAP(_n) MT_DMA_SHDL(0x060 + ((_n) << 2))
423 #define MT_DMASHDL_Q_MAP_MASK GENMASK(3, 0)
426 #define MT_DMASHDL_SCHED_SET(_n) MT_DMA_SHDL(0x070 + ((_n) << 2))
428 #define MT_WFDMA_HOST_CONFIG 0x7c027030
431 #define MT_UMAC(ofs) (0x74000000 + (ofs))
432 #define MT_UDMA_TX_QSEL MT_UMAC(0x008)
435 #define MT_UDMA_WLCFG_1 MT_UMAC(0x00c)
436 #define MT_WL_RX_AGG_PKT_LMT GENMASK(7, 0)
439 #define MT_UDMA_WLCFG_0 MT_UMAC(0x18)
440 #define MT_WL_RX_AGG_TO GENMASK(7, 0)
453 #define MT_UDMA_CONN_INFRA_STATUS MT_UMAC(0xa20)
455 #define MT_UDMA_CONN_INFRA_STATUS_SEL MT_UMAC(0xa24)
457 #define MT_SSUSB_EPCTL_CSR(ofs) (0x74011800 + (ofs))
458 #define MT_SSUSB_EPCTL_CSR_EP_RST_OPT MT_SSUSB_EPCTL_CSR(0x090)
460 #define MT_UWFDMA0(ofs) (0x7c024000 + (ofs))
461 #define MT_UWFDMA0_GLO_CFG MT_UWFDMA0(0x208)
462 #define MT_UWFDMA0_GLO_CFG_EXT0 MT_UWFDMA0(0x2b0)
463 #define MT_UWFDMA0_GLO_CFG_EXT1 MT_UWFDMA0(0x2b4)
464 #define MT_UWFDMA0_TX_RING_EXT_CTRL(_n) MT_UWFDMA0(0x600 + ((_n) << 2))
466 #define MT_CONN_STATUS 0x7c053c10
467 #define MT_WIFI_PATCH_DL_STATE BIT(0)
469 #define MT_CONN_ON_LPCTL 0x7c060010
470 #define PCIE_LPCR_HOST_SET_OWN BIT(0)
474 #define MT_CONN_ON_MISC 0x7c0600f0
475 #define MT_TOP_MISC2_FW_PWR_ON BIT(0)
477 #define MT_TOP_MISC2_FW_N9_RDY GENMASK(1, 0)
479 #define MT_WF_SW_DEF_CR(ofs) (0x401a00 + (ofs))
480 #define MT_WF_SW_DEF_CR_USB_MCU_EVENT MT_WF_SW_DEF_CR(0x028)
484 #define WFSYS_SW_RST_B BIT(0)