17 #define MT7981_CON_INFRA_VERSION 0x02090000
18 #define MT7986_CON_INFRA_VERSION 0x02070000
21 #define MT_INFRACFG_CONN2AP_SLPPROT	0x0d0
22 #define MT_INFRACFG_AP2CONN_SLPPROT	0x0d4
26 #define MT_INFRACFG_TX_EN_MASK		BIT(0)
29 #define MT_TOP_POS_FAST_CTRL		0x114
32 #define MT_TOP_POS_SKU			0x21c
55 	mt76_wr(dev, MT_TOP_SPI_WRITE_DATA_CR(adie), 0);  in mt76_wmac_spi_read()
65 	return 0;  in mt76_wmac_spi_read()
117 	ret = mt76_wmac_spi_rmw(dev, adie, MT_ADIE_EFUSE2_CTRL, BIT(30), 0x0);  in mt7986_wmac_adie_efuse_read()
123 	val = FIELD_PREP(MT_ADIE_EFUSE_MODE_MASK, 0) |  in mt7986_wmac_adie_efuse_read()
191 		      FIELD_PREP(MT_TOP_POS_FAST_EN_MASK, 0x1));  in mt7986_wmac_consys_reset()
229 	return 0;  in mt7986_wmac_gpio_setup()
262 	return 0;  in mt7986_wmac_consys_lockup()
291 	np = of_parse_phandle(pdev->of_node, "memory-region", 0);  in mt798x_wmac_coninfra_setup()
305 			       MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1);  in mt798x_wmac_coninfra_setup()
307 			       MT_INFRA_CKGEN_BUS_RDY_SEL_MASK, 0x1);  in mt798x_wmac_coninfra_setup()
315 			       MT_TOP_WF_AP_PERI_BASE_MASK, 0x300d0000 >> 16);  in mt798x_wmac_coninfra_setup()
318 			       MT_TOP_EFUSE_BASE_MASK, 0x11f20000 >> 16);  in mt798x_wmac_coninfra_setup()
327 	mt76_wr(dev, MT_TOP_RGU_SYSRAM_PDN, 0);  in mt798x_wmac_coninfra_setup()
330 	return 0;  in mt798x_wmac_coninfra_setup()
336 	u32 adie_main = 0, adie_ext = 0;  in mt798x_wmac_sku_setup()
339 		       MT_CONN_INFRA_ADIE1_RESET_MASK, 0x1);  in mt798x_wmac_sku_setup()
343 			       MT_CONN_INFRA_ADIE2_RESET_MASK, 0x1);  in mt798x_wmac_sku_setup()
348 	ret = mt76_wmac_spi_read(dev, 0, MT_ADIE_CHIP_ID, &adie_main);  in mt798x_wmac_sku_setup()
364 	return 0;  in mt798x_wmac_sku_setup()
369 	if (adie == 0)  in mt7986_adie_idx()
377 	return mt7986_adie_idx(adie, adie_type) == 0x7975;  in is_7975()
382 	return mt7986_adie_idx(adie, adie_type) == 0x7976;  in is_7976()
418 	return 0;  in mt7986_wmac_adie_thermal_cal()
449 		*result = max(0, min(127, *result));  in mt7986_read_efuse_xo_trim_7976()
452 	return 0;  in mt7986_read_efuse_xo_trim_7976()
463 		return 0;  in mt7986_wmac_adie_xtal_trim_7976()
478 	if (!mode || mode == 0x2) {  in mt7986_wmac_adie_xtal_trim_7976()
488 	} else if (mode == 0x3 || mode == 0x4 || mode == 0x6) {  in mt7986_wmac_adie_xtal_trim_7976()
514 	ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_RG_TOP_THADC, 0x4a563b00);  in mt798x_wmac_adie_patch_7976()
518 	if (version == 0x8a00 || version == 0x8a10 ||  in mt798x_wmac_adie_patch_7976()
519 	    version == 0x8b00 || version == 0x8c10) {  in mt798x_wmac_adie_patch_7976()
520 		rg_xo_01 = 0x1d59080f;  in mt798x_wmac_adie_patch_7976()
521 		rg_xo_03 = 0x34c00fe0;  in mt798x_wmac_adie_patch_7976()
524 			rg_xo_01 = 0x1959c80f;  in mt798x_wmac_adie_patch_7976()
526 			rg_xo_01 = 0x1959f80f;  in mt798x_wmac_adie_patch_7976()
531 		rg_xo_03 = 0x34d00fe0;  in mt798x_wmac_adie_patch_7976()
561 	return 0;  in mt7986_read_efuse_xo_trim_7975()
567 	u32 data, result = 0, value;  in mt7986_wmac_adie_xtal_trim_7975()
572 		return 0;  in mt7986_wmac_adie_xtal_trim_7975()
611 					MT_ADIE_7975_XO_2_FIX_EN, 0x0);  in mt7986_wmac_adie_xtal_trim_7975()
617 				 MT_ADIE_7975_XO_CTRL6_MASK, 0x1);  in mt7986_wmac_adie_xtal_trim_7975()
625 	ret = mt76_wmac_spi_write(dev, adie, 0x348, 0x00000002);  in mt7986_wmac_adie_patch_7975()
629 	ret = mt76_wmac_spi_write(dev, adie, 0x378, 0x00000002);  in mt7986_wmac_adie_patch_7975()
633 	ret = mt76_wmac_spi_write(dev, adie, 0x3a8, 0x00000002);  in mt7986_wmac_adie_patch_7975()
637 	ret = mt76_wmac_spi_write(dev, adie, 0x3d8, 0x00000002);  in mt7986_wmac_adie_patch_7975()
642 	ret = mt76_wmac_spi_write(dev, adie, 0xa1c, 0x30000aaa);  in mt7986_wmac_adie_patch_7975()
647 	ret = mt76_wmac_spi_write(dev, adie, 0xa84, 0x8470008a);  in mt7986_wmac_adie_patch_7975()
653 		ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000007);  in mt7986_wmac_adie_patch_7975()
655 		ret = mt76_wmac_spi_write(dev, adie, 0x074, 0x00000002);  in mt7986_wmac_adie_patch_7975()
665 	ret = mt76_wmac_spi_write(dev, adie, 0xaa4, 0x01001fc0);  in mt7986_wmac_adie_patch_7975()
670 	ret = mt76_wmac_spi_write(dev, adie, 0x070, 0x00000005);  in mt7986_wmac_adie_patch_7975()
675 	ret = mt76_wmac_spi_write(dev, adie, 0x344, 0x00000088);  in mt7986_wmac_adie_patch_7975()
679 	ret = mt76_wmac_spi_write(dev, adie, 0x374, 0x00000088);  in mt7986_wmac_adie_patch_7975()
683 	ret = mt76_wmac_spi_write(dev, adie, 0x3a4, 0x00000088);  in mt7986_wmac_adie_patch_7975()
687 	ret = mt76_wmac_spi_write(dev, adie, 0x3d4, 0x00000088);  in mt7986_wmac_adie_patch_7975()
692 	ret = mt76_wmac_spi_write(dev, adie, 0xa80, 0x44d07000);  in mt7986_wmac_adie_patch_7975()
697 	ret = mt76_wmac_spi_write(dev, adie, 0xa88, 0x3900aaaa);  in mt7986_wmac_adie_patch_7975()
702 	ret = mt76_wmac_spi_write(dev, adie, 0x2c4, 0x00000000);  in mt7986_wmac_adie_patch_7975()
708 		return mt76_wmac_spi_write(dev, adie, 0x2c8, 0x00000072);  in mt7986_wmac_adie_patch_7975()
718 	ret = mt76_wmac_spi_write(dev, adie, MT_ADIE_CLK_EN, ~0);  in mt7986_wmac_adie_cfg()
724 					BIT(1), 0x1);  in mt7986_wmac_adie_cfg()
740 						  MT_ADIE_WRI_CK_SEL, 0x1c);  in mt7986_wmac_adie_cfg()
772 					  0x80000000);  in mt7986_wmac_afe_cal()
776 					  0x88888005);  in mt7986_wmac_afe_cal()
783 		       MT_AFE_RG_WBG_EN_RCK_MASK, 0x1);  in mt7986_wmac_afe_cal()
787 		 MT_AFE_RG_WBG_EN_RCK_MASK, 0x0);  in mt7986_wmac_afe_cal()
790 		       MT_AFE_RG_WBG_EN_BPLL_UP_MASK, 0x1);  in mt7986_wmac_afe_cal()
794 		       MT_AFE_RG_WBG_EN_WPLL_UP_MASK, 0x1);  in mt7986_wmac_afe_cal()
810 		 MT_AFE_RG_WBG_EN_PLL_UP_MASK, 0x0);  in mt7986_wmac_afe_cal()
813 				  0x5);  in mt7986_wmac_afe_cal()
836 	mt7986_wmac_subsys_pll_initial(dev, 0);  in mt7986_wmac_subsys_setting()
841 		 MT_CONN_INFRA_OSC_RC_EN_MASK, 0x0);  in mt7986_wmac_subsys_setting()
843 		 MT_CONN_INFRA_OSC_STB_TIME_MASK, 0x80706);  in mt7986_wmac_subsys_setting()
854 		       MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0x2);  in mt7986_wmac_bus_timeout()
857 		       MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf);  in mt7986_wmac_bus_timeout()
860 		       MT_INFRA_BUS_TIMEOUT_LIMIT_MASK, 0xc);  in mt7986_wmac_bus_timeout()
863 		       MT_INFRA_BUS_TIMEOUT_EN_MASK, 0xf);  in mt7986_wmac_bus_timeout()
873 		       MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1);  in mt7986_wmac_clock_enable()
876 		       MT_INFRA_CKGEN_DIV_SEL_MASK, 0x1);  in mt7986_wmac_clock_enable()
879 		       MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);  in mt7986_wmac_clock_enable()
882 		       MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);  in mt7986_wmac_clock_enable()
885 		       MT_INFRA_CKGEN_DIV_SEL_MASK, 0x8);  in mt7986_wmac_clock_enable()
888 		       MT_INFRA_CKGEN_DIV_EN_MASK, 0x1);  in mt7986_wmac_clock_enable()
891 		       MT_INFRA_CKGEN_BUS_CLK_SEL_MASK, 0x0);  in mt7986_wmac_clock_enable()
894 		       MT_CONN_INFRA_HW_CTRL_MASK, 0x1);  in mt7986_wmac_clock_enable()
897 		 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x1);  in mt7986_wmac_clock_enable()
902 	if (is_7975(dev, 0, adie_type) || is_7976(dev, 0, adie_type)) {  in mt7986_wmac_clock_enable()
903 		mt76_rmw_field(dev, MT_ADIE_SLP_CTRL_CK0(0),  in mt7986_wmac_clock_enable()
904 			       MT_SLP_CTRL_EN_MASK, 0x1);  in mt7986_wmac_clock_enable()
908 				  dev, MT_ADIE_SLP_CTRL_CK0(0));  in mt7986_wmac_clock_enable()
912 			       MT_SLP_CTRL_EN_MASK, 0x1);  in mt7986_wmac_clock_enable()
916 				  dev, MT_ADIE_SLP_CTRL_CK0(0));  in mt7986_wmac_clock_enable()
921 		 MT_TOP_CONN_INFRA_WAKEUP_MASK, 0x0);  in mt7986_wmac_clock_enable()
933 		return 0;  in mt7986_wmac_top_wfsys_wakeup()
943 		mt76_wr(dev, MT_CONNINFRA_SKU_DEC_ADDR, 0);  in mt7986_wmac_wm_enable()
948 		return 0;  in mt7986_wmac_wm_enable()
950 	return read_poll_timeout(mt76_rr, cur, (cur == 0x1d1e),  in mt7986_wmac_wm_enable()
976 		 MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x0);  in mt7986_wmac_wfsys_setting()
997 	return read_poll_timeout(mt76_rr, cur, (cur == 0x02060000),  in mt7986_wmac_wfsys_setting()
1013 	mt76_wr(dev, MT_MCU_BUS_REMAP, 0x810f0000);  in mt7986_wmac_wfsys_set_timeout()
1018 	val = FIELD_PREP(MT_MCU_BUS_DBG_TIMEOUT_SET_MASK, 0x3aa) |  in mt7986_wmac_wfsys_set_timeout()
1029 	if (is_7976(dev, 0, adie_type) && is_7976(dev, 1, adie_type))  in mt7986_wmac_sku_update()
1030 		val = 0xf;  in mt7986_wmac_sku_update()
1031 	else if (is_7975(dev, 0, adie_type) && is_7975(dev, 1, adie_type))  in mt7986_wmac_sku_update()
1032 		val = 0xd;  in mt7986_wmac_sku_update()
1033 	else if (is_7976(dev, 0, adie_type))  in mt7986_wmac_sku_update()
1034 		val = 0x7;  in mt7986_wmac_sku_update()
1036 		val = 0x8;  in mt7986_wmac_sku_update()
1038 		val = 0xa;  in mt7986_wmac_sku_update()
1047 	return 0;  in mt7986_wmac_sku_update()
1056 		return 0;  in mt7986_wmac_adie_setup()
1084 	return 0;  in mt7986_wmac_subsys_powerup()
1133 	ret = mt7986_wmac_adie_setup(dev, 0, adie_type);  in mt7986_wmac_enable()
1167 		       MT_CONN_INFRA_WF_SLP_PROT_MASK, 0x1);  in mt7986_wmac_disable()
1177 	mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_MCU_BPLL_CFG_MASK, 0x2);  in mt7986_wmac_disable()
1178 	mt76_rmw_field(dev, MT_AFE_DIG_EN_02(0), MT_AFE_WPLL_CFG_MASK, 0x2);  in mt7986_wmac_disable()
1182 		       MT_CONN_INFRA_EMI_REQ_MASK, 0x1);  in mt7986_wmac_disable()
1184 		       MT_CONN_INFRA_EMI_REQ_MASK, 0x0);  in mt7986_wmac_disable()
1186 		       MT_CONN_INFRA_INFRA_REQ_MASK, 0x1);  in mt7986_wmac_disable()
1188 		       MT_CONN_INFRA_INFRA_REQ_MASK, 0x0);  in mt7986_wmac_disable()
1235 	mem_base = devm_platform_ioremap_resource(pdev, 0);  in mt798x_wmac_probe()
1247 	if (ret < 0)  in mt798x_wmac_probe()
1251 		irq = platform_get_irq(pdev, 0);  in mt798x_wmac_probe()
1252 		if (irq < 0) {  in mt798x_wmac_probe()
1273 	return 0;  in mt798x_wmac_probe()
1293 	{ .compatible = "mediatek,mt7981-wmac", .data = (u32 *)0x7981 },
1294 	{ .compatible = "mediatek,mt7986-wmac", .data = (u32 *)0x7986 },