175 	u32 hif1_ofs = 0;  in mt7915_dma_disable()  local
178 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);  in mt7915_dma_disable()
201 			mt76_clear(dev, MT_WFDMA0_RST + hif1_ofs,  in mt7915_dma_disable()
205 			mt76_set(dev, MT_WFDMA0_RST + hif1_ofs,  in mt7915_dma_disable()
210 				mt76_clear(dev, MT_WFDMA1_RST + hif1_ofs,  in mt7915_dma_disable()
214 				mt76_set(dev, MT_WFDMA1_RST + hif1_ofs,  in mt7915_dma_disable()
238 		mt76_clear(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,  in mt7915_dma_disable()
246 			mt76_clear(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,  in mt7915_dma_disable()
258 	u32 hif1_ofs = 0;  in mt7915_dma_start()  local
262 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);  in mt7915_dma_start()
280 			mt76_set(dev, MT_WFDMA0_GLO_CFG + hif1_ofs,  in mt7915_dma_start()
287 				mt76_set(dev, MT_WFDMA1_GLO_CFG + hif1_ofs,  in mt7915_dma_start()
337 	u32 hif1_ofs = 0;  in mt7915_dma_enable()  local
340 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);  in mt7915_dma_enable()
347 		mt76_wr(dev, MT_WFDMA0_RST_DTX_PTR + hif1_ofs, ~0);  in mt7915_dma_enable()
349 			mt76_wr(dev, MT_WFDMA1_RST_DTX_PTR + hif1_ofs, ~0);  in mt7915_dma_enable()
362 		mt76_wr(dev, MT_WFDMA0_PRI_DLY_INT_CFG0 + hif1_ofs, 0);  in mt7915_dma_enable()
365 				hif1_ofs, 0);  in mt7915_dma_enable()
368 				hif1_ofs, 0);  in mt7915_dma_enable()
370 				hif1_ofs, 0);  in mt7915_dma_enable()
390 		mt76_set(dev, MT_WFDMA0_BUSY_ENA + hif1_ofs,  in mt7915_dma_enable()
396 			mt76_set(dev, MT_WFDMA1_BUSY_ENA + hif1_ofs,  in mt7915_dma_enable()
412 	u32 hif1_ofs = 0;  in mt7915_dma_init()  local
420 		hif1_ofs = MT_WFDMA0_PCIE1(0) - MT_WFDMA0(0);  in mt7915_dma_init()
563 				       MT_RXQ_RING_BASE(MT_RXQ_BAND1) + hif1_ofs);  in mt7915_dma_init()
572 				       MT_RXQ_RING_BASE(MT_RXQ_BAND1_WA) + hif1_ofs);  in mt7915_dma_init()