Lines Matching +full:16 +full:- +full:bit
1 /* SPDX-License-Identifier: ISC */
45 #define MT_TX_FREE_MSDU_ID GENMASK(30, 16)
46 #define MT_TX_FREE_PAIR BIT(31)
52 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
55 #define MT_TXD1_LONG_FORMAT BIT(31)
56 #define MT_TXD1_TGID BIT(30)
58 #define MT_TXD1_AMSDU BIT(23)
61 #define MT_TXD1_HDR_FORMAT GENMASK(17, 16)
63 #define MT_TXD1_ETH_802_3 BIT(15)
64 #define MT_TXD1_VTA BIT(10)
67 #define MT_TXD2_FIX_RATE BIT(31)
68 #define MT_TXD2_FIXED_RATE BIT(30)
70 #define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
72 #define MT_TXD2_HTC_VLD BIT(13)
73 #define MT_TXD2_DURATION BIT(12)
74 #define MT_TXD2_BIP BIT(11)
75 #define MT_TXD2_MULTICAST BIT(10)
76 #define MT_TXD2_RTS BIT(9)
77 #define MT_TXD2_SOUNDING BIT(8)
78 #define MT_TXD2_NDPA BIT(7)
79 #define MT_TXD2_NDP BIT(6)
83 #define MT_TXD3_SN_VALID BIT(31)
84 #define MT_TXD3_PN_VALID BIT(30)
85 #define MT_TXD3_SW_POWER_MGMT BIT(29)
86 #define MT_TXD3_BA_DISABLE BIT(28)
87 #define MT_TXD3_SEQ GENMASK(27, 16)
90 #define MT_TXD3_TIMING_MEASURE BIT(5)
91 #define MT_TXD3_DAS BIT(4)
92 #define MT_TXD3_EEOSP BIT(3)
93 #define MT_TXD3_EMRD BIT(2)
94 #define MT_TXD3_PROTECT_FRAME BIT(1)
95 #define MT_TXD3_NO_ACK BIT(0)
99 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
100 #define MT_TXD5_MD BIT(15)
101 #define MT_TXD5_ADD_BA BIT(14)
102 #define MT_TXD5_TX_STATUS_HOST BIT(10)
103 #define MT_TXD5_TX_STATUS_MCU BIT(9)
104 #define MT_TXD5_TX_STATUS_FMT BIT(8)
107 #define MT_TXD6_TX_IBF BIT(31)
108 #define MT_TXD6_TX_EBF BIT(30)
109 #define MT_TXD6_TX_RATE GENMASK(29, 16)
112 #define MT_TXD6_LDPC BIT(11)
113 #define MT_TXD6_SPE_ID_IDX BIT(10)
115 #define MT_TXD6_DYN_BW BIT(3)
116 #define MT_TXD6_FIXED_BW BIT(2)
120 #define MT_TXD7_UDP_TCP_SUM BIT(29)
121 #define MT_TXD7_IP_SUM BIT(28)
123 #define MT_TXD7_SUB_TYPE GENMASK(19, 16)
125 #define MT_TXD7_PSE_FID GENMASK(27, 16)
127 #define MT_TXD7_HW_AMSDU BIT(10)
133 #define MT_TX_RATE_STBC BIT(13)
136 #define MT_TX_RATE_SU_EXT_TONE BIT(5)
137 #define MT_TX_RATE_DCM BIT(4)
138 /* VHT/HE only use bits 0-3 */
141 #define MT_TXS0_FIXED_RATE BIT(31)
144 #define MT_TXS0_AMPDU BIT(25)
146 #define MT_TXS0_BA_ERROR BIT(22)
147 #define MT_TXS0_PS_FLAG BIT(21)
148 #define MT_TXS0_TXOP_TIMEOUT BIT(20)
149 #define MT_TXS0_BIP_ERROR BIT(19)
151 #define MT_TXS0_QUEUE_TIMEOUT BIT(18)
152 #define MT_TXS0_RTS_TIMEOUT BIT(17)
153 #define MT_TXS0_ACK_TIMEOUT BIT(16)
154 #define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)
156 #define MT_TXS0_TX_STATUS_HOST BIT(15)
157 #define MT_TXS0_TX_STATUS_MCU BIT(14)
161 #define MT_TXS1_RESP_RATE GENMASK(19, 16)
167 #define MT_TXS2_SHARED_ANTENNA BIT(26)
168 #define MT_TXS2_WCID GENMASK(25, 16)
186 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
189 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
190 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
191 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
195 #define MT_RXD1_NORMAL_GROUP_1 BIT(11)
196 #define MT_RXD1_NORMAL_GROUP_2 BIT(12)
197 #define MT_RXD1_NORMAL_GROUP_3 BIT(13)
198 #define MT_RXD1_NORMAL_GROUP_4 BIT(14)
199 #define MT_RXD1_NORMAL_GROUP_5 BIT(15)
200 #define MT_RXD1_NORMAL_SEC_MODE GENMASK(20, 16)
202 #define MT_RXD1_NORMAL_CM BIT(23)
203 #define MT_RXD1_NORMAL_CLM BIT(24)
204 #define MT_RXD1_NORMAL_ICV_ERR BIT(25)
205 #define MT_RXD1_NORMAL_TKIP_MIC_ERR BIT(26)
206 #define MT_RXD1_NORMAL_FCS_ERR BIT(27)
207 #define MT_RXD1_NORMAL_BAND_IDX BIT(28)
208 #define MT_RXD1_NORMAL_SPP_EN BIT(29)
209 #define MT_RXD1_NORMAL_ADD_OM BIT(30)
210 #define MT_RXD1_NORMAL_SEC_DONE BIT(31)
214 #define MT_RXD2_NORMAL_CO_ANT BIT(6)
215 #define MT_RXD2_NORMAL_BF_CQI BIT(7)
217 #define MT_RXD2_NORMAL_HDR_TRANS BIT(13)
219 #define MT_RXD2_NORMAL_TID GENMASK(19, 16)
220 #define MT_RXD2_NORMAL_MU_BAR BIT(21)
221 #define MT_RXD2_NORMAL_SW_BIT BIT(22)
222 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
223 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
224 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
225 #define MT_RXD2_NORMAL_INT_FRAME BIT(26)
226 #define MT_RXD2_NORMAL_FRAG BIT(27)
227 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
228 #define MT_RXD2_NORMAL_NDATA BIT(29)
229 #define MT_RXD2_NORMAL_NON_AMPDU BIT(30)
230 #define MT_RXD2_NORMAL_BF_REPORT BIT(31)
235 #define MT_RXD4_MID_AMSDU_FRAME BIT(1)
236 #define MT_RXD4_LAST_AMSDU_FRAME BIT(0)
237 #define MT_RXD4_NORMAL_PATTERN_DROP BIT(9)
238 #define MT_RXD4_NORMAL_CLS BIT(10)
240 #define MT_RXD4_NORMAL_MAGIC_PKT BIT(13)
243 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
246 #define MT_RXV_HDR_BAND_IDX BIT(24)
251 #define MT_RXD3_NORMAL_ADDR_TYPE GENMASK(17, 16)
252 #define MT_RXD3_NORMAL_U2M BIT(0)
253 #define MT_RXD3_NORMAL_HTC_VLD BIT(0)
254 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(19)
255 #define MT_RXD3_NORMAL_BEACON_MC BIT(20)
256 #define MT_RXD3_NORMAL_BEACON_UC BIT(21)
257 #define MT_RXD3_NORMAL_AMSDU BIT(22)
258 #define MT_RXD3_NORMAL_MESH BIT(23)
259 #define MT_RXD3_NORMAL_MHCP BIT(24)
260 #define MT_RXD3_NORMAL_NO_INFO_WB BIT(25)
261 #define MT_RXD3_NORMAL_DISABLE_RX_HDR_TRANS BIT(26)
262 #define MT_RXD3_NORMAL_POWER_SAVE_STAT BIT(27)
263 #define MT_RXD3_NORMAL_MORE BIT(28)
264 #define MT_RXD3_NORMAL_UNWANT BIT(29)
265 #define MT_RXD3_NORMAL_RX_DROP BIT(30)
266 #define MT_RXD3_NORMAL_VLAN2ETH BIT(31)
270 #define MT_RXD6_TA_LO GENMASK(31, 16)
275 #define MT_RXD8_QOS_CTL GENMASK(31, 16)
279 /* P-RXV DW0 */
281 #define MT_PRXV_TX_DCM BIT(4)
282 #define MT_PRXV_TX_ER_SU_106T BIT(5)
284 #define MT_PRXV_TXBF BIT(10)
285 #define MT_PRXV_HT_AD_CODE BIT(11)
289 #define MT_PRXV_HT_SGI GENMASK(16, 15)
292 #define MT_PRXV_DCM BIT(17)
293 #define MT_PRXV_NUM_RX BIT(20, 18)
295 /* P-RXV DW1 */
297 #define MT_PRXV_RCPI2 GENMASK(23, 16)
302 /* C-RXV */
308 #define MT_CRXV_HE_LDPC_EXT_SYM BIT(20)
309 #define MT_CRXV_HE_PE_DISAMBIG BIT(23)
311 #define MT_CRXV_HE_UPLINK BIT(31)
315 #define MT_CRXV_HE_RU2 GENMASK(23, 16)
321 #define MT_CRXV_HE_SR1_MASK GENMASK(16, 12)
327 #define MT_CRXV_HE_BEAM_CHNG BIT(13)
328 #define MT_CRXV_HE_DOPPLER BIT(16)
338 #define MT_CT_INFO_APPLY_TXD BIT(0)
339 #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
340 #define MT_CT_INFO_MGMT_FRAME BIT(2)
341 #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
342 #define MT_CT_INFO_HSR2_TX BIT(4)
343 #define MT_CT_INFO_FROM_HOST BIT(7)