Lines Matching +full:7 +full:- +full:31
1 /* SPDX-License-Identifier: ISC */
12 #define MT_RXD0_PKT_TYPE GENMASK(31, 29)
22 #define MT_RXD1_NORMAL_BSSID GENMASK(31, 26)
31 #define MT_RXD1_NORMAL_KEY_ID GENMASK(7, 6)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
59 #define MT_RXD2_NORMAL_WLAN_IDX GENMASK(7, 0)
61 #define MT_RXD3_NORMAL_PF_STS GENMASK(31, 30)
70 #define MT_RXD3_NORMAL_RXV_SEQ GENMASK(7, 0)
75 #define MT_RXD6_QOS_CTL GENMASK(31, 16)
77 #define MT_RXD7_HT_CONTROL GENMASK(31, 0)
79 #define MT_RXV1_ACID_DET_H BIT(31)
92 #define MT_RXV1_HT_STBC GENMASK(8, 7)
95 #define MT_RXV2_SEL_ANT BIT(31)
101 #define MT_RXV3_WB_RSSI GENMASK(31, 24)
104 #define MT_RXV4_RCPI3 GENMASK(31, 24)
107 #define MT_RXV4_RCPI0 GENMASK(7, 0)
111 #define MT_RXV6_NF3 GENMASK(31, 24)
114 #define MT_RXV6_NF0 GENMASK(7, 0)
156 #define MT_TXD0_P_IDX BIT(31)
163 #define MT_TXD1_OWN_MAC GENMASK(31, 26)
173 #define MT_TXD1_WLAN_IDX GENMASK(7, 0)
175 #define MT_TXD2_FIX_RATE BIT(31)
187 #define MT_TXD2_NDPA BIT(7)
192 #define MT_TXD3_SN_VALID BIT(31)
200 #define MT_TXD4_PN_LOW GENMASK(31, 0)
202 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
208 #define MT_TXD5_PID GENMASK(7, 0)
210 #define MT_TXD6_FIXED_RATE BIT(31)
220 /* MT7663 DW7 HW-AMSDU */
237 #define MT_TXS0_PID GENMASK(31, 24)
254 #define MT_TXS1_ANT_ID GENMASK(31, 20)
261 #define MT_TXS1_ACKED_MPDU BIT(7)
264 #define MT_TXS2_WCID GENMASK(31, 24)
268 #define MT_TXS3_LAST_TX_RATE GENMASK(31, 29)
274 #define MT_TXS4_F0_TIMESTAMP GENMASK(31, 0)
281 #define MT_TXS5_F1_NOISE_0 GENMASK(7, 0)
283 #define MT_TXS6_F1_RCPI_3 GENMASK(31, 24)
286 #define MT_TXS6_F1_RCPI_0 GENMASK(7, 0)