Lines Matching +full:20 +full:us
52 #define MT_RXD2_NORMAL_ICV_ERR BIT(20)
84 #define MT_RXV1_HT_SMOOTH BIT(20)
99 #define MT_RXV2_LENGTH GENMASK(20, 0)
166 #define MT_TXD1_AMSDU BIT(20)
222 #define MT_TXD7_TYPE GENMASK(21, 20)
240 #define MT_TXS0_TXOP_TIMEOUT BIT(20)
254 #define MT_TXS1_ANT_ID GENMASK(31, 20)
289 u32 max_width; /* us */
292 u32 min_stgr_pri; /* us */
293 u32 max_stgr_pri; /* us */
294 u32 min_cr_pri; /* us */
295 u32 max_cr_pri; /* us */