Lines Matching +full:16 +full:- +full:bit
1 /* SPDX-License-Identifier: ISC */
11 #define MT_RXD0_PKT_FLAG GENMASK(19, 16)
14 #define MT_RXD0_NORMAL_ETH_TYPE_OFS GENMASK(22, 16)
15 #define MT_RXD0_NORMAL_IP_SUM BIT(23)
16 #define MT_RXD0_NORMAL_UDP_TCP_SUM BIT(24)
17 #define MT_RXD0_NORMAL_GROUP_1 BIT(25)
18 #define MT_RXD0_NORMAL_GROUP_2 BIT(26)
19 #define MT_RXD0_NORMAL_GROUP_3 BIT(27)
20 #define MT_RXD0_NORMAL_GROUP_4 BIT(28)
25 #define MT_RXD1_MID_AMSDU_FRAME BIT(1)
26 #define MT_RXD1_LAST_AMSDU_FRAME BIT(0)
27 #define MT_RXD1_NORMAL_HDR_TRANS BIT(23)
28 #define MT_RXD1_NORMAL_HDR_OFFSET BIT(22)
29 #define MT_RXD1_NORMAL_MAC_HDR_LEN GENMASK(21, 16)
32 #define MT_RXD1_NORMAL_BEACON_UC BIT(5)
33 #define MT_RXD1_NORMAL_BEACON_MC BIT(4)
34 #define MT_RXD1_NORMAL_BF_REPORT BIT(3)
37 #define MT_RXD1_NORMAL_MCAST BIT(2)
38 #define MT_RXD1_NORMAL_U2M BIT(1)
39 #define MT_RXD1_NORMAL_HTC_VLD BIT(0)
41 #define MT_RXD2_NORMAL_NON_AMPDU BIT(31)
42 #define MT_RXD2_NORMAL_NON_AMPDU_SUB BIT(30)
43 #define MT_RXD2_NORMAL_NDATA BIT(29)
44 #define MT_RXD2_NORMAL_NULL_FRAME BIT(28)
45 #define MT_RXD2_NORMAL_FRAG BIT(27)
46 #define MT_RXD2_NORMAL_INT_FRAME BIT(26)
47 #define MT_RXD2_NORMAL_HDR_TRANS_ERROR BIT(25)
48 #define MT_RXD2_NORMAL_MAX_LEN_ERROR BIT(24)
49 #define MT_RXD2_NORMAL_AMSDU_ERR BIT(23)
50 #define MT_RXD2_NORMAL_LEN_MISMATCH BIT(22)
51 #define MT_RXD2_NORMAL_TKIP_MIC_ERR BIT(21)
52 #define MT_RXD2_NORMAL_ICV_ERR BIT(20)
53 #define MT_RXD2_NORMAL_CLM BIT(19)
54 #define MT_RXD2_NORMAL_CM BIT(18)
55 #define MT_RXD2_NORMAL_FCS_ERR BIT(17)
56 #define MT_RXD2_NORMAL_SW_BIT BIT(16)
62 #define MT_RXD3_NORMAL_PF_MODE BIT(29)
65 #define MT_RXD3_NORMAL_MAGIC_PKT BIT(13)
67 #define MT_RXD3_NORMAL_CLS BIT(10)
68 #define MT_RXD3_NORMAL_PATTERN_DROP BIT(9)
69 #define MT_RXD3_NORMAL_TSF_COMPARE_LOSS BIT(8)
75 #define MT_RXD6_QOS_CTL GENMASK(31, 16)
79 #define MT_RXV1_ACID_DET_H BIT(31)
80 #define MT_RXV1_ACID_DET_L BIT(30)
83 #define MT_RXV1_HT_NO_SOUND BIT(21)
84 #define MT_RXV1_HT_SMOOTH BIT(20)
85 #define MT_RXV1_HT_SHORT_GI BIT(19)
86 #define MT_RXV1_HT_AGGR BIT(18)
87 #define MT_RXV1_VHTA1_B22 BIT(17)
88 #define MT_RXV1_FRAME_MODE GENMASK(16, 15)
91 #define MT_RXV1_HT_AD_CODE BIT(9)
95 #define MT_RXV2_SEL_ANT BIT(31)
96 #define MT_RXV2_VALID_BIT BIT(30)
102 #define MT_RXV3_IB_RSSI GENMASK(23, 16)
105 #define MT_RXV4_RCPI2 GENMASK(23, 16)
112 #define MT_RXV6_NF2 GENMASK(23, 16)
150 #define MT_CT_INFO_APPLY_TXD BIT(0)
151 #define MT_CT_INFO_COPY_HOST_TXD_ALL BIT(1)
152 #define MT_CT_INFO_MGMT_FRAME BIT(2)
153 #define MT_CT_INFO_NONE_CIPHER_FRAME BIT(3)
154 #define MT_CT_INFO_HSR2_TX BIT(4)
156 #define MT_TXD0_P_IDX BIT(31)
158 #define MT_TXD0_UDP_TCP_SUM BIT(24)
159 #define MT_TXD0_IP_SUM BIT(23)
160 #define MT_TXD0_ETH_TYPE_OFFSET GENMASK(22, 16)
166 #define MT_TXD1_AMSDU BIT(20)
167 #define MT_TXD1_UNXV BIT(19)
169 #define MT_TXD1_TXD_LEN BIT(16)
170 #define MT_TXD1_LONG_FORMAT BIT(15)
175 #define MT_TXD2_FIX_RATE BIT(31)
176 #define MT_TXD2_TIMING_MEASURE BIT(30)
177 #define MT_TXD2_BA_DISABLE BIT(29)
179 #define MT_TXD2_MAX_TX_TIME GENMASK(23, 16)
181 #define MT_TXD2_HTC_VLD BIT(13)
182 #define MT_TXD2_DURATION BIT(12)
183 #define MT_TXD2_BIP BIT(11)
184 #define MT_TXD2_MULTICAST BIT(10)
185 #define MT_TXD2_RTS BIT(9)
186 #define MT_TXD2_SOUNDING BIT(8)
187 #define MT_TXD2_NDPA BIT(7)
188 #define MT_TXD2_NDP BIT(6)
192 #define MT_TXD3_SN_VALID BIT(31)
193 #define MT_TXD3_PN_VALID BIT(30)
194 #define MT_TXD3_SEQ GENMASK(27, 16)
197 #define MT_TXD3_PROTECT_FRAME BIT(1)
198 #define MT_TXD3_NO_ACK BIT(0)
202 #define MT_TXD5_PN_HIGH GENMASK(31, 16)
203 #define MT_TXD5_SW_POWER_MGMT BIT(13)
204 #define MT_TXD5_DA_SELECT BIT(11)
205 #define MT_TXD5_TX_STATUS_HOST BIT(10)
206 #define MT_TXD5_TX_STATUS_MCU BIT(9)
207 #define MT_TXD5_TX_STATUS_FMT BIT(8)
210 #define MT_TXD6_FIXED_RATE BIT(31)
211 #define MT_TXD6_SGI BIT(30)
212 #define MT_TXD6_LDPC BIT(29)
213 #define MT_TXD6_TX_BF BIT(28)
214 #define MT_TXD6_TX_RATE GENMASK(27, 16)
216 #define MT_TXD6_DYN_BW BIT(3)
217 #define MT_TXD6_FIXED_BW BIT(2)
220 /* MT7663 DW7 HW-AMSDU */
221 #define MT_TXD7_HW_AMSDU_CAP BIT(30)
223 #define MT_TXD7_SUB_TYPE GENMASK(19, 16)
225 #define MT_TXD7_SPE_IDX_SLE BIT(10)
230 #define MT_TX_RATE_STBC BIT(11)
238 #define MT_TXS0_BA_ERROR BIT(22)
239 #define MT_TXS0_PS_FLAG BIT(21)
240 #define MT_TXS0_TXOP_TIMEOUT BIT(20)
241 #define MT_TXS0_BIP_ERROR BIT(19)
243 #define MT_TXS0_QUEUE_TIMEOUT BIT(18)
244 #define MT_TXS0_RTS_TIMEOUT BIT(17)
245 #define MT_TXS0_ACK_TIMEOUT BIT(16)
246 #define MT_TXS0_ACK_ERROR_MASK GENMASK(18, 16)
248 #define MT_TXS0_TX_STATUS_HOST BIT(15)
249 #define MT_TXS0_TX_STATUS_MCU BIT(14)
250 #define MT_TXS0_TXS_FORMAT BIT(13)
251 #define MT_TXS0_FIXED_RATE BIT(12)
255 #define MT_TXS1_RESP_RATE GENMASK(19, 16)
257 #define MT_TXS1_I_TXBF BIT(13)
258 #define MT_TXS1_E_TXBF BIT(12)
260 #define MT_TXS1_AMPDU BIT(8)
261 #define MT_TXS1_ACKED_MPDU BIT(7)
265 #define MT_TXS2_RXV_SEQNO GENMASK(23, 16)
279 #define MT_TXS5_F1_NOISE_2 GENMASK(23, 16)
284 #define MT_TXS6_F1_RCPI_2 GENMASK(23, 16)
317 struct mt7615_dfs_pattern radar_pattern[16];