marvell/libertas/if_spi.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
40 /* SPI register offsets. 4-byte aligned. */
46 #define IF_SPI_CMD_READBASE_REG 0x10	/* Read command base reg */
47 #define IF_SPI_CMD_WRITEBASE_REG 0x14	/* Write command base reg */
48 #define IF_SPI_CMD_RDWRPORT_REG 0x18	/* Read/Write command port reg */
62 #define IF_SPI_HOST_INT_CTRL_REG 0x40	/* Host interrupt controller reg */
71 #define IF_SPI_HOST_INT_CAUSE_REG 0x58	/* Host interrupt cause reg */
72 #define IF_SPI_HOST_INT_STATUS_REG 0x5C	/* Host interrupt status reg */
73 #define IF_SPI_HOST_INT_EVENT_MASK_REG 0x60 /* Host interrupt event mask */
74 #define IF_SPI_HOST_INT_STATUS_MASK_REG	0x64 /* Host interrupt status mask */
75 #define IF_SPI_HOST_INT_RESET_SELECT_REG 0x68 /* Host interrupt reset select */
85 /* Host Interrupt Control bit : Wake up */
87 /* Host Interrupt Control bit : WLAN ready */
92 /* Host Interrupt Control bit : Tx auto download */
94 /* Host Interrupt Control bit : Rx auto upload */
96 /* Host Interrupt Control bit : Command auto download */
98 /* Host Interrupt Control bit : Command auto upload */
106 /* Card Interrupt Case bit : Command download over */
108 /* Card Interrupt Case bit : Host event */
110 /* Card Interrupt Case bit : Command upload over */
137 /* Host Interrupt Status bit : Tx download ready */
139 /* Host Interrupt Status bit : Rx upload ready */
141 /* Host Interrupt Status bit : Command download ready */
143 /* Host Interrupt Status bit : Card event */
145 /* Host Interrupt Status bit : Command upload ready */
147 /* Host Interrupt Status bit : I/O write FIFO overflow */
149 /* Host Interrupt Status bit : I/O read FIFO underflow */
151 /* Host Interrupt Status bit : Data write FIFO overflow */
153 /* Host Interrupt Status bit : Data read FIFO underflow */
155 /* Host Interrupt Status bit : Command write FIFO overflow */
157 /* Host Interrupt Status bit : Command read FIFO underflow */
161 /* Host Interrupt Status Mask bit : Tx download ready */
163 /* Host Interrupt Status Mask bit : Rx upload ready */
165 /* Host Interrupt Status Mask bit : Command download ready */
167 /* Host Interrupt Status Mask bit : Card event */
169 /* Host Interrupt Status Mask bit : Command upload ready */
171 /* Host Interrupt Status Mask bit : I/O write FIFO overflow */
173 /* Host Interrupt Status Mask bit : I/O read FIFO underflow */
175 /* Host Interrupt Status Mask bit : Data write FIFO overflow */
177 /* Host Interrupt Status Mask bit : Data write FIFO underflow */
179 /* Host Interrupt Status Mask bit : Command write FIFO overflow */
181 /* Host Interrupt Status Mask bit : Command write FIFO underflow */