Lines Matching +full:0 +full:x00008000

19 #define SPI_ADRS_READ_BIT_15		0x8000
21 #define SPI_ADRS_ARM_INTERRUPTS		0x00
22 #define SPI_ADRS_ARM_INT_EN		0x04
24 #define SPI_ADRS_HOST_INTERRUPTS	0x08
25 #define SPI_ADRS_HOST_INT_EN		0x0c
26 #define SPI_ADRS_HOST_INT_ACK		0x10
28 #define SPI_ADRS_GEN_PURP_1		0x14
29 #define SPI_ADRS_GEN_PURP_2		0x18
31 #define SPI_ADRS_DEV_CTRL_STAT		0x26    /* high word */
33 #define SPI_ADRS_DMA_DATA		0x28
35 #define SPI_ADRS_DMA_WRITE_CTRL		0x2c
36 #define SPI_ADRS_DMA_WRITE_LEN		0x2e
37 #define SPI_ADRS_DMA_WRITE_BASE		0x30
39 #define SPI_ADRS_DMA_READ_CTRL		0x34
40 #define SPI_ADRS_DMA_READ_LEN		0x36
41 #define SPI_ADRS_DMA_READ_BASE		0x38
43 #define SPI_CTRL_STAT_HOST_OVERRIDE	0x8000
44 #define SPI_CTRL_STAT_START_HALTED	0x4000
45 #define SPI_CTRL_STAT_RAM_BOOT		0x2000
46 #define SPI_CTRL_STAT_HOST_RESET	0x1000
47 #define SPI_CTRL_STAT_HOST_CPU_EN	0x0800
49 #define SPI_DMA_WRITE_CTRL_ENABLE	0x0001
50 #define SPI_DMA_READ_CTRL_ENABLE	0x0001
59 #define SPI_TARGET_INT_WAKEUP		0x00000001
60 #define SPI_TARGET_INT_SLEEP		0x00000002
61 #define SPI_TARGET_INT_RDDONE		0x00000004
63 #define SPI_TARGET_INT_CTS		0x00004000
64 #define SPI_TARGET_INT_DR		0x00008000
66 #define SPI_HOST_INT_READY		0x00000001
67 #define SPI_HOST_INT_WR_READY		0x00000002
68 #define SPI_HOST_INT_SW_UPDATE		0x00000004
69 #define SPI_HOST_INT_UPDATE		0x10000000
72 #define SPI_HOST_INT_CR			0x00004000
75 #define SPI_HOST_INT_DR			0x00008000