Lines Matching +full:msi +full:- +full:base +full:- +full:vec
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
3 * Copyright (C) 2007-2015, 2018-2024 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
18 #include "iwl-drv.h"
19 #include "iwl-trans.h"
20 #include "iwl-csr.h"
21 #include "iwl-prph.h"
22 #include "iwl-scd.h"
23 #include "iwl-agn-hw.h"
24 #include "fw/error-dump.h"
27 #include "mei/iwl-mei.h"
29 #include "iwl-fh.h"
30 #include "iwl-context-info-gen3.h"
43 struct pci_dev *pdev = trans_pcie->pci_dev; in iwl_trans_pcie_dump_regs()
47 if (trans_pcie->pcie_dbg_dumped_once) in iwl_trans_pcie_dump_regs()
64 prefix = (char *)buf + alloc_size - PREFIX_LEN; in iwl_trans_pcie_dump_regs()
92 if (!pdev->bus->self) in iwl_trans_pcie_dump_regs()
95 pdev = pdev->bus->self; in iwl_trans_pcie_dump_regs()
126 trans_pcie->pcie_dbg_dumped_once = 1; in iwl_trans_pcie_dump_regs()
132 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ in iwl_trans_pcie_sw_reset()
133 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_trans_pcie_sw_reset()
151 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_free_fw_monitor()
153 if (!fw_mon->size) in iwl_pcie_free_fw_monitor()
156 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, in iwl_pcie_free_fw_monitor()
157 fw_mon->physical); in iwl_pcie_free_fw_monitor()
159 fw_mon->block = NULL; in iwl_pcie_free_fw_monitor()
160 fw_mon->physical = 0; in iwl_pcie_free_fw_monitor()
161 fw_mon->size = 0; in iwl_pcie_free_fw_monitor()
167 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_alloc_fw_monitor_block()
173 if (fw_mon->size) { in iwl_pcie_alloc_fw_monitor_block()
174 memset(fw_mon->block, 0, fw_mon->size); in iwl_pcie_alloc_fw_monitor_block()
179 for (power = max_power; power >= 11; power--) { in iwl_pcie_alloc_fw_monitor_block()
181 block = dma_alloc_coherent(trans->dev, size, &physical, in iwl_pcie_alloc_fw_monitor_block()
197 "Sorry - debug buffer is only %luK while you requested %luK\n", in iwl_pcie_alloc_fw_monitor_block()
198 (unsigned long)BIT(power - 10), in iwl_pcie_alloc_fw_monitor_block()
199 (unsigned long)BIT(max_power - 10)); in iwl_pcie_alloc_fw_monitor_block()
201 fw_mon->block = block; in iwl_pcie_alloc_fw_monitor_block()
202 fw_mon->physical = physical; in iwl_pcie_alloc_fw_monitor_block()
203 fw_mon->size = size; in iwl_pcie_alloc_fw_monitor_block()
239 if (trans->cfg->apmg_not_supported) in iwl_pcie_set_pwr()
242 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) in iwl_pcie_set_pwr()
268 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); in iwl_pcie_apm_config()
269 trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); in iwl_pcie_apm_config()
271 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); in iwl_pcie_apm_config()
272 trans->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; in iwl_pcie_apm_config()
273 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", in iwl_pcie_apm_config()
275 trans->ltr_enabled ? "En" : "Dis"); in iwl_pcie_apm_config()
295 if (trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_8000) in iwl_pcie_apm_init()
311 * wake device's PCI Express link L1a -> L0s in iwl_pcie_apm_init()
318 /* Configure analog phase-lock-loop before activating to D0A */ in iwl_pcie_apm_init()
319 if (trans->trans_cfg->base_params->pll_cfg) in iwl_pcie_apm_init()
326 if (trans->cfg->host_interrupt_operation_mode) { in iwl_pcie_apm_init()
328 * This is a bit of an abuse - This is needed for 7260 / 3160 in iwl_pcie_apm_init()
333 * consumes slightly more power (100uA) - but allows to be sure in iwl_pcie_apm_init()
355 if (!trans->cfg->apmg_not_supported) { in iwl_pcie_apm_init()
360 /* Disable L1-Active */ in iwl_pcie_apm_init()
369 set_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_init()
446 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. in iwl_pcie_apm_lp_xtal_enable()
471 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_pcie_apm_stop_master()
499 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_apm_stop()
503 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) in iwl_pcie_apm_stop()
506 else if (trans->trans_cfg->device_family >= in iwl_pcie_apm_stop()
520 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); in iwl_pcie_apm_stop()
525 if (trans->cfg->lp_xtal_workaround) { in iwl_pcie_apm_stop()
534 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. in iwl_pcie_apm_stop()
545 spin_lock_bh(&trans_pcie->irq_lock); in iwl_pcie_nic_init()
547 spin_unlock_bh(&trans_pcie->irq_lock); in iwl_pcie_nic_init()
554 iwl_op_mode_nic_config(trans->op_mode); in iwl_pcie_nic_init()
564 return -ENOMEM; in iwl_pcie_nic_init()
567 if (trans->trans_cfg->base_params->shadow_reg_enable) { in iwl_pcie_nic_init()
599 /* Note: returns standard 0/-ERROR code */
610 trans->csme_own = false; in iwl_pcie_prepare_card_hw()
628 trans->csme_own = false; in iwl_pcie_prepare_card_hw()
635 trans->csme_own = true; in iwl_pcie_prepare_card_hw()
636 if (trans->trans_cfg->device_family != in iwl_pcie_prepare_card_hw()
641 return -EBUSY; in iwl_pcie_prepare_card_hw()
693 trans_pcie->ucode_write_complete = false; in iwl_pcie_load_firmware_chunk()
696 return -EIO; in iwl_pcie_load_firmware_chunk()
702 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, in iwl_pcie_load_firmware_chunk()
703 trans_pcie->ucode_write_complete, 5 * HZ); in iwl_pcie_load_firmware_chunk()
707 return -ETIMEDOUT; in iwl_pcie_load_firmware_chunk()
718 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); in iwl_pcie_load_section()
724 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, in iwl_pcie_load_section()
729 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, in iwl_pcie_load_section()
732 return -ENOMEM; in iwl_pcie_load_section()
735 for (offset = 0; offset < section->len; offset += chunk_sz) { in iwl_pcie_load_section()
739 copy_size = min_t(u32, chunk_sz, section->len - offset); in iwl_pcie_load_section()
740 dst_addr = section->offset + offset; in iwl_pcie_load_section()
750 memcpy(v_addr, (const u8 *)section->data + offset, copy_size); in iwl_pcie_load_section()
766 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); in iwl_pcie_load_section()
787 for (i = *first_ucode_section; i < image->num_sec; i++) { in iwl_pcie_load_cpu_sections_8000()
791 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections_8000()
793 * PAGING_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections_8000()
796 if (!image->sec[i].data || in iwl_pcie_load_cpu_sections_8000()
797 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || in iwl_pcie_load_cpu_sections_8000()
798 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { in iwl_pcie_load_cpu_sections_8000()
805 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections_8000()
821 if (trans->trans_cfg->gen2) { in iwl_pcie_load_cpu_sections_8000()
853 for (i = *first_ucode_section; i < image->num_sec; i++) { in iwl_pcie_load_cpu_sections()
857 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections()
859 * PAGING_SEPARATOR_SECTION delimiter - separate between in iwl_pcie_load_cpu_sections()
862 if (!image->sec[i].data || in iwl_pcie_load_cpu_sections()
863 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || in iwl_pcie_load_cpu_sections()
864 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { in iwl_pcie_load_cpu_sections()
871 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); in iwl_pcie_load_cpu_sections()
885 &trans->dbg.fw_mon_cfg[alloc_id]; in iwl_pcie_apply_destination_ini()
891 if (le32_to_cpu(fw_mon_cfg->buf_location) == in iwl_pcie_apply_destination_ini()
901 if (le32_to_cpu(fw_mon_cfg->buf_location) != in iwl_pcie_apply_destination_ini()
903 !trans->dbg.fw_mon_ini[alloc_id].num_frags) in iwl_pcie_apply_destination_ini()
906 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; in iwl_pcie_apply_destination_ini()
912 frag->physical >> MON_BUFF_SHIFT_VER2); in iwl_pcie_apply_destination_ini()
914 (frag->physical + frag->size - 256) >> in iwl_pcie_apply_destination_ini()
920 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; in iwl_pcie_apply_destination()
921 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_pcie_apply_destination()
930 get_fw_dbg_mode_string(dest->monitor_mode)); in iwl_pcie_apply_destination()
932 if (dest->monitor_mode == EXTERNAL_MODE) in iwl_pcie_apply_destination()
933 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); in iwl_pcie_apply_destination()
937 for (i = 0; i < trans->dbg.n_dest_reg; i++) { in iwl_pcie_apply_destination()
938 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); in iwl_pcie_apply_destination()
939 u32 val = le32_to_cpu(dest->reg_ops[i].val); in iwl_pcie_apply_destination()
941 switch (dest->reg_ops[i].op) { in iwl_pcie_apply_destination()
969 IWL_ERR(trans, "FW debug - unknown OP %d\n", in iwl_pcie_apply_destination()
970 dest->reg_ops[i].op); in iwl_pcie_apply_destination()
976 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { in iwl_pcie_apply_destination()
977 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), in iwl_pcie_apply_destination()
978 fw_mon->physical >> dest->base_shift); in iwl_pcie_apply_destination()
979 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_pcie_apply_destination()
980 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
981 (fw_mon->physical + fw_mon->size - in iwl_pcie_apply_destination()
982 256) >> dest->end_shift); in iwl_pcie_apply_destination()
984 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), in iwl_pcie_apply_destination()
985 (fw_mon->physical + fw_mon->size) >> in iwl_pcie_apply_destination()
986 dest->end_shift); in iwl_pcie_apply_destination()
997 image->is_dual_cpus ? "Dual" : "Single"); in iwl_pcie_load_given_ucode()
1004 if (image->is_dual_cpus) { in iwl_pcie_load_given_ucode()
1035 image->is_dual_cpus ? "Dual" : "Single"); in iwl_pcie_load_given_ucode_8000()
1069 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1073 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1074 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1076 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_pcie_check_hw_rf_kill()
1077 if (trans_pcie->opmode_down) in iwl_pcie_check_hw_rf_kill()
1078 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1081 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_pcie_check_hw_rf_kill()
1100 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \
1147 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; in iwl_pcie_map_non_rx_causes()
1151 * the first interrupt vector will serve non-RX and FBQ causes. in iwl_pcie_map_non_rx_causes()
1155 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_pcie_map_non_rx_causes()
1167 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; in iwl_pcie_map_rx_causes()
1171 * The first RX queue - fallback queue, which is designated for in iwl_pcie_map_rx_causes()
1174 * the other (N - 2) interrupt vectors. in iwl_pcie_map_rx_causes()
1177 for (idx = 1; idx < trans->num_rx_queues; idx++) { in iwl_pcie_map_rx_causes()
1179 MSIX_FH_INT_CAUSES_Q(idx - offset)); in iwl_pcie_map_rx_causes()
1185 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) in iwl_pcie_map_rx_causes()
1189 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) in iwl_pcie_map_rx_causes()
1195 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_conf_msix_hw()
1197 if (!trans_pcie->msix_enabled) { in iwl_pcie_conf_msix_hw()
1198 if (trans->trans_cfg->mq_rx_supported && in iwl_pcie_conf_msix_hw()
1199 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1209 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) in iwl_pcie_conf_msix_hw()
1226 struct iwl_trans *trans = trans_pcie->trans; in iwl_pcie_init_msix()
1230 if (!trans_pcie->msix_enabled) in iwl_pcie_init_msix()
1233 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); in iwl_pcie_init_msix()
1234 trans_pcie->fh_mask = trans_pcie->fh_init_mask; in iwl_pcie_init_msix()
1235 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); in iwl_pcie_init_msix()
1236 trans_pcie->hw_mask = trans_pcie->hw_init_mask; in iwl_pcie_init_msix()
1243 lockdep_assert_held(&trans_pcie->mutex); in _iwl_trans_pcie_stop_device()
1245 if (trans_pcie->is_down) in _iwl_trans_pcie_stop_device()
1248 trans_pcie->is_down = true; in _iwl_trans_pcie_stop_device()
1263 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { in _iwl_trans_pcie_stop_device()
1272 /* Power-down device's busmaster DMA clocks */ in _iwl_trans_pcie_stop_device()
1273 if (!trans->cfg->apmg_not_supported) { in _iwl_trans_pcie_stop_device()
1281 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in _iwl_trans_pcie_stop_device()
1291 /* re-take ownership to prevent other users from stealing the device */ in _iwl_trans_pcie_stop_device()
1295 * Upon stop, the IVAR table gets erased, so msi-x won't in _iwl_trans_pcie_stop_device()
1296 * work. This causes a bug in RF-KILL flows, since the interrupt in _iwl_trans_pcie_stop_device()
1308 * should be masked. Re-ACK all the interrupts here. in _iwl_trans_pcie_stop_device()
1313 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); in _iwl_trans_pcie_stop_device()
1314 clear_bit(STATUS_INT_ENABLED, &trans->status); in _iwl_trans_pcie_stop_device()
1315 clear_bit(STATUS_TPOWER_PMI, &trans->status); in _iwl_trans_pcie_stop_device()
1328 if (trans_pcie->msix_enabled) { in iwl_pcie_synchronize_irqs()
1331 for (i = 0; i < trans_pcie->alloc_vecs; i++) in iwl_pcie_synchronize_irqs()
1332 synchronize_irq(trans_pcie->msix_entries[i].vector); in iwl_pcie_synchronize_irqs()
1334 synchronize_irq(trans_pcie->pci_dev->irq); in iwl_pcie_synchronize_irqs()
1348 return -EIO; in iwl_trans_pcie_start_fw()
1356 * We enabled the RF-Kill interrupt and the handler may very in iwl_trans_pcie_start_fw()
1365 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_start_fw()
1370 ret = -ERFKILL; in iwl_trans_pcie_start_fw()
1375 if (trans_pcie->is_down) { in iwl_trans_pcie_start_fw()
1378 ret = -EIO; in iwl_trans_pcie_start_fw()
1398 * by the RF-Kill interrupt (hence mask all the interrupt besides the in iwl_trans_pcie_start_fw()
1400 * RF-Kill switch is toggled, we will find out after having loaded in iwl_trans_pcie_start_fw()
1410 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_start_fw()
1415 /* re-check RF-Kill state since we may have missed the interrupt */ in iwl_trans_pcie_start_fw()
1418 ret = -ERFKILL; in iwl_trans_pcie_start_fw()
1421 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_start_fw()
1450 set_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1451 set_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1453 clear_bit(STATUS_RFKILL_HW, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1454 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_handle_stop_rfkill()
1465 iwl_op_mode_time_point(trans->op_mode, in iwl_trans_pcie_stop_device()
1469 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_stop_device()
1470 trans_pcie->opmode_down = true; in iwl_trans_pcie_stop_device()
1471 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); in iwl_trans_pcie_stop_device()
1474 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_stop_device()
1482 lockdep_assert_held(&trans_pcie->mutex); in iwl_trans_pcie_rf_kill()
1486 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state) && in iwl_trans_pcie_rf_kill()
1487 !WARN_ON(trans->trans_cfg->gen2)) in iwl_trans_pcie_rf_kill()
1507 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in iwl_pcie_d3_complete_suspend()
1521 * reset TX queues -- some of their registers reset during S3 in iwl_pcie_d3_complete_suspend()
1536 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_AX210) in iwl_pcie_d3_handshake()
1540 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_pcie_d3_handshake()
1547 ret = wait_event_timeout(trans_pcie->sx_waitq, in iwl_pcie_d3_handshake()
1548 trans_pcie->sx_complete, 2 * HZ); in iwl_pcie_d3_handshake()
1551 trans_pcie->sx_complete = false; in iwl_pcie_d3_handshake()
1556 return -ETIMEDOUT; in iwl_pcie_d3_handshake()
1595 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_d3_resume()
1608 * MSI mode since HW reset erased it. in iwl_trans_pcie_d3_resume()
1609 * Also enables interrupts - none will happen as in iwl_trans_pcie_d3_resume()
1614 if (!trans_pcie->msix_enabled) in iwl_trans_pcie_d3_resume()
1660 if (!cfg_trans->mq_rx_supported) in iwl_pcie_set_interrupt_capa()
1663 if (cfg_trans->device_family <= IWL_DEVICE_FAMILY_9000) in iwl_pcie_set_interrupt_capa()
1668 trans_pcie->msix_entries[i].entry = i; in iwl_pcie_set_interrupt_capa()
1670 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, in iwl_pcie_set_interrupt_capa()
1675 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", in iwl_pcie_set_interrupt_capa()
1679 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; in iwl_pcie_set_interrupt_capa()
1682 "MSI-X enabled. %d interrupt vectors were allocated\n", in iwl_pcie_set_interrupt_capa()
1692 if (num_irqs <= max_irqs - 2) { in iwl_pcie_set_interrupt_capa()
1693 trans_pcie->trans->num_rx_queues = num_irqs + 1; in iwl_pcie_set_interrupt_capa()
1694 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | in iwl_pcie_set_interrupt_capa()
1696 } else if (num_irqs == max_irqs - 1) { in iwl_pcie_set_interrupt_capa()
1697 trans_pcie->trans->num_rx_queues = num_irqs; in iwl_pcie_set_interrupt_capa()
1698 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; in iwl_pcie_set_interrupt_capa()
1700 trans_pcie->trans->num_rx_queues = num_irqs - 1; in iwl_pcie_set_interrupt_capa()
1704 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", in iwl_pcie_set_interrupt_capa()
1705 trans_pcie->trans->num_rx_queues, trans_pcie->shared_vec_mask); in iwl_pcie_set_interrupt_capa()
1707 WARN_ON(trans_pcie->trans->num_rx_queues > IWL_MAX_RX_HW_QUEUES); in iwl_pcie_set_interrupt_capa()
1709 trans_pcie->alloc_vecs = num_irqs; in iwl_pcie_set_interrupt_capa()
1710 trans_pcie->msix_enabled = true; in iwl_pcie_set_interrupt_capa()
1716 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); in iwl_pcie_set_interrupt_capa()
1732 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; in iwl_pcie_irq_set_affinity()
1733 iter_rx_q = trans_pcie->trans->num_rx_queues - 1 + i; in iwl_pcie_irq_set_affinity()
1738 * (i.e. return will be > i - 1). in iwl_pcie_irq_set_affinity()
1740 cpu = cpumask_next(i - offset, cpu_online_mask); in iwl_pcie_irq_set_affinity()
1741 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); in iwl_pcie_irq_set_affinity()
1742 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, in iwl_pcie_irq_set_affinity()
1743 &trans_pcie->affinity_mask[i]); in iwl_pcie_irq_set_affinity()
1745 IWL_ERR(trans_pcie->trans, in iwl_pcie_irq_set_affinity()
1747 trans_pcie->msix_entries[i].vector); in iwl_pcie_irq_set_affinity()
1757 for (i = 0; i < trans_pcie->alloc_vecs; i++) { in iwl_pcie_init_msix_handler()
1760 const char *qname = queue_name(&pdev->dev, trans_pcie, i); in iwl_pcie_init_msix_handler()
1763 return -ENOMEM; in iwl_pcie_init_msix_handler()
1765 msix_entry = &trans_pcie->msix_entries[i]; in iwl_pcie_init_msix_handler()
1766 ret = devm_request_threaded_irq(&pdev->dev, in iwl_pcie_init_msix_handler()
1767 msix_entry->vector, in iwl_pcie_init_msix_handler()
1769 (i == trans_pcie->def_irq) ? in iwl_pcie_init_msix_handler()
1776 IWL_ERR(trans_pcie->trans, in iwl_pcie_init_msix_handler()
1782 iwl_pcie_irq_set_affinity(trans_pcie->trans); in iwl_pcie_init_msix_handler()
1791 switch (trans->trans_cfg->device_family) { in iwl_trans_pcie_clear_persistence_bit()
1809 return -EPERM; in iwl_trans_pcie_clear_persistence_bit()
1844 lockdep_assert_held(&trans_pcie->mutex); in _iwl_trans_pcie_start_hw()
1860 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_22000 && in _iwl_trans_pcie_start_hw()
1861 trans->trans_cfg->integrated) { in _iwl_trans_pcie_start_hw()
1876 trans_pcie->opmode_down = false; in _iwl_trans_pcie_start_hw()
1879 trans_pcie->is_down = false; in _iwl_trans_pcie_start_hw()
1892 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_start_hw()
1894 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_start_hw()
1903 mutex_lock(&trans_pcie->mutex); in iwl_trans_pcie_op_mode_leave()
1905 /* disable interrupts - don't enable HW RF kill interrupt */ in iwl_trans_pcie_op_mode_leave()
1914 mutex_unlock(&trans_pcie->mutex); in iwl_trans_pcie_op_mode_leave()
1921 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write8()
1926 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_write32()
1931 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); in iwl_trans_pcie_read32()
1936 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_prph_msk()
1965 /* free all first - we might be reconfigured for a different size */ in iwl_trans_pcie_configure()
1968 trans_pcie->txqs.cmd.q_id = trans_cfg->cmd_queue; in iwl_trans_pcie_configure()
1969 trans_pcie->txqs.cmd.fifo = trans_cfg->cmd_fifo; in iwl_trans_pcie_configure()
1970 trans_pcie->txqs.page_offs = trans_cfg->cb_data_offs; in iwl_trans_pcie_configure()
1971 trans_pcie->txqs.dev_cmd_offs = trans_cfg->cb_data_offs + sizeof(void *); in iwl_trans_pcie_configure()
1972 trans_pcie->txqs.queue_alloc_cmd_ver = trans_cfg->queue_alloc_cmd_ver; in iwl_trans_pcie_configure()
1974 if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS)) in iwl_trans_pcie_configure()
1975 trans_pcie->n_no_reclaim_cmds = 0; in iwl_trans_pcie_configure()
1977 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds; in iwl_trans_pcie_configure()
1978 if (trans_pcie->n_no_reclaim_cmds) in iwl_trans_pcie_configure()
1979 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds, in iwl_trans_pcie_configure()
1980 trans_pcie->n_no_reclaim_cmds * sizeof(u8)); in iwl_trans_pcie_configure()
1982 trans_pcie->rx_buf_size = trans_cfg->rx_buf_size; in iwl_trans_pcie_configure()
1983 trans_pcie->rx_page_order = in iwl_trans_pcie_configure()
1984 iwl_trans_get_rb_size_order(trans_pcie->rx_buf_size); in iwl_trans_pcie_configure()
1985 trans_pcie->rx_buf_bytes = in iwl_trans_pcie_configure()
1986 iwl_trans_get_rb_size(trans_pcie->rx_buf_size); in iwl_trans_pcie_configure()
1987 trans_pcie->supported_dma_mask = DMA_BIT_MASK(12); in iwl_trans_pcie_configure()
1988 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_configure()
1989 trans_pcie->supported_dma_mask = DMA_BIT_MASK(11); in iwl_trans_pcie_configure()
1991 trans_pcie->txqs.bc_table_dword = trans_cfg->bc_table_dword; in iwl_trans_pcie_configure()
1992 trans_pcie->scd_set_active = trans_cfg->scd_set_active; in iwl_trans_pcie_configure()
1994 trans->command_groups = trans_cfg->command_groups; in iwl_trans_pcie_configure()
1995 trans->command_groups_size = trans_cfg->command_groups_size; in iwl_trans_pcie_configure()
1998 trans_pcie->fw_reset_handshake = trans_cfg->fw_reset_handshake; in iwl_trans_pcie_configure()
2005 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; in iwl_trans_pcie_free_pnvm_dram_regions()
2008 for (i = 0; i < dram_regions->n_regions; i++) { in iwl_trans_pcie_free_pnvm_dram_regions()
2009 dma_free_coherent(dev, dram_regions->drams[i].size, in iwl_trans_pcie_free_pnvm_dram_regions()
2010 dram_regions->drams[i].block, in iwl_trans_pcie_free_pnvm_dram_regions()
2011 dram_regions->drams[i].physical); in iwl_trans_pcie_free_pnvm_dram_regions()
2013 dram_regions->n_regions = 0; in iwl_trans_pcie_free_pnvm_dram_regions()
2016 if (desc_dram->block) { in iwl_trans_pcie_free_pnvm_dram_regions()
2017 dma_free_coherent(dev, desc_dram->size, in iwl_trans_pcie_free_pnvm_dram_regions()
2018 desc_dram->block, in iwl_trans_pcie_free_pnvm_dram_regions()
2019 desc_dram->physical); in iwl_trans_pcie_free_pnvm_dram_regions()
2026 iwl_pcie_free_dma_ptr(trans, &trans->invalid_tx_cmd); in iwl_pcie_free_invalid_tx_cmd()
2040 ret = iwl_pcie_alloc_dma_ptr(trans, &trans->invalid_tx_cmd, in iwl_pcie_alloc_invalid_tx_cmd()
2044 memcpy(trans->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd)); in iwl_pcie_alloc_invalid_tx_cmd()
2055 if (trans->trans_cfg->gen2) in iwl_trans_pcie_free()
2061 if (trans_pcie->rba.alloc_wq) { in iwl_trans_pcie_free()
2062 destroy_workqueue(trans_pcie->rba.alloc_wq); in iwl_trans_pcie_free()
2063 trans_pcie->rba.alloc_wq = NULL; in iwl_trans_pcie_free()
2066 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_free()
2067 for (i = 0; i < trans_pcie->alloc_vecs; i++) { in iwl_trans_pcie_free()
2069 trans_pcie->msix_entries[i].vector, in iwl_trans_pcie_free()
2073 trans_pcie->msix_enabled = false; in iwl_trans_pcie_free()
2078 free_netdev(trans_pcie->napi_dev); in iwl_trans_pcie_free()
2084 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data, in iwl_trans_pcie_free()
2085 trans->dev); in iwl_trans_pcie_free()
2086 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data, in iwl_trans_pcie_free()
2087 trans->dev); in iwl_trans_pcie_free()
2089 mutex_destroy(&trans_pcie->mutex); in iwl_trans_pcie_free()
2091 if (trans_pcie->txqs.tso_hdr_page) { in iwl_trans_pcie_free()
2094 per_cpu_ptr(trans_pcie->txqs.tso_hdr_page, i); in iwl_trans_pcie_free()
2096 if (p && p->page) in iwl_trans_pcie_free()
2097 __free_page(p->page); in iwl_trans_pcie_free()
2100 free_percpu(trans_pcie->txqs.tso_hdr_page); in iwl_trans_pcie_free()
2116 struct pci_dev *pdev = removal->pdev; in iwl_trans_pcie_removal_wk()
2122 bus = pdev->bus; in iwl_trans_pcie_removal_wk()
2127 dev_err(&pdev->dev, "Device gone - attempting removal\n"); in iwl_trans_pcie_removal_wk()
2129 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); in iwl_trans_pcie_removal_wk()
2134 if (removal->rescan) { in iwl_trans_pcie_removal_wk()
2135 if (bus->parent) in iwl_trans_pcie_removal_wk()
2136 bus = bus->parent; in iwl_trans_pcie_removal_wk()
2151 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_remove()
2154 IWL_ERR(trans, "Device gone - scheduling removal!\n"); in iwl_trans_pcie_remove()
2165 "Module is being unloaded - abort\n"); in iwl_trans_pcie_remove()
2178 set_bit(STATUS_TRANS_DEAD, &trans->status); in iwl_trans_pcie_remove()
2180 removal->pdev = to_pci_dev(trans->dev); in iwl_trans_pcie_remove()
2181 removal->rescan = rescan; in iwl_trans_pcie_remove()
2182 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); in iwl_trans_pcie_remove()
2183 pci_dev_get(removal->pdev); in iwl_trans_pcie_remove()
2184 schedule_work(&removal->work); in iwl_trans_pcie_remove()
2201 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in __iwl_trans_pcie_grab_nic_access()
2204 spin_lock(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2206 if (trans_pcie->cmd_hold_nic_awake) in __iwl_trans_pcie_grab_nic_access()
2209 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { in __iwl_trans_pcie_grab_nic_access()
2217 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_8000) in __iwl_trans_pcie_grab_nic_access()
2225 * host DRAM when sleeping/waking for power-saving. in __iwl_trans_pcie_grab_nic_access()
2237 * 5000 series and later (including 1000 series) have non-volatile SRAM, in __iwl_trans_pcie_grab_nic_access()
2256 spin_unlock(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2262 * Fool sparse by faking we release the lock - sparse will in __iwl_trans_pcie_grab_nic_access()
2265 __release(&trans_pcie->reg_lock); in __iwl_trans_pcie_grab_nic_access()
2287 lockdep_assert_held(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2290 * Fool sparse by faking we acquiring the lock - sparse will in iwl_trans_pcie_release_nic_access()
2293 __acquire(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2295 if (trans_pcie->cmd_hold_nic_awake) in iwl_trans_pcie_release_nic_access()
2297 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_release_nic_access()
2310 spin_unlock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_release_nic_access()
2341 return -EIO; in iwl_trans_pcie_read_mem()
2356 return -EBUSY; in iwl_trans_pcie_read_mem()
2376 ret = -EBUSY; in iwl_trans_pcie_write_mem()
2384 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, in iwl_trans_pcie_read_config32()
2395 if (queue >= trans->num_rx_queues || !trans_pcie->rxq) in iwl_trans_pcie_rxq_dma_data()
2396 return -EINVAL; in iwl_trans_pcie_rxq_dma_data()
2398 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; in iwl_trans_pcie_rxq_dma_data()
2399 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; in iwl_trans_pcie_rxq_dma_data()
2400 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; in iwl_trans_pcie_rxq_dma_data()
2401 data->fr_bd_wid = 0; in iwl_trans_pcie_rxq_dma_data()
2415 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) in iwl_trans_pcie_wait_txq_empty()
2416 return -ENODEV; in iwl_trans_pcie_wait_txq_empty()
2418 if (!test_bit(txq_idx, trans_pcie->txqs.queue_used)) in iwl_trans_pcie_wait_txq_empty()
2419 return -EINVAL; in iwl_trans_pcie_wait_txq_empty()
2422 txq = trans_pcie->txqs.txq[txq_idx]; in iwl_trans_pcie_wait_txq_empty()
2424 spin_lock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2425 overflow_tx = txq->overflow_tx || in iwl_trans_pcie_wait_txq_empty()
2426 !skb_queue_empty(&txq->overflow_q); in iwl_trans_pcie_wait_txq_empty()
2427 spin_unlock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2429 wr_ptr = READ_ONCE(txq->write_ptr); in iwl_trans_pcie_wait_txq_empty()
2431 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || in iwl_trans_pcie_wait_txq_empty()
2435 u8 write_ptr = READ_ONCE(txq->write_ptr); in iwl_trans_pcie_wait_txq_empty()
2443 "WR pointer moved while flushing %d -> %d\n", in iwl_trans_pcie_wait_txq_empty()
2445 return -ETIMEDOUT; in iwl_trans_pcie_wait_txq_empty()
2450 spin_lock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2451 overflow_tx = txq->overflow_tx || in iwl_trans_pcie_wait_txq_empty()
2452 !skb_queue_empty(&txq->overflow_q); in iwl_trans_pcie_wait_txq_empty()
2453 spin_unlock_bh(&txq->lock); in iwl_trans_pcie_wait_txq_empty()
2456 if (txq->read_ptr != txq->write_ptr) { in iwl_trans_pcie_wait_txq_empty()
2460 return -ETIMEDOUT; in iwl_trans_pcie_wait_txq_empty()
2476 cnt < trans->trans_cfg->base_params->num_of_queues; in iwl_trans_pcie_wait_txqs_empty()
2479 if (cnt == trans_pcie->txqs.cmd.q_id) in iwl_trans_pcie_wait_txqs_empty()
2481 if (!test_bit(cnt, trans_pcie->txqs.queue_used)) in iwl_trans_pcie_wait_txqs_empty()
2499 spin_lock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_set_bits_mask()
2501 spin_unlock_bh(&trans_pcie->reg_lock); in iwl_trans_pcie_set_bits_mask()
2617 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_start()
2620 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_start()
2626 state->pos = *pos; in iwl_dbgfs_tx_queue_seq_start()
2633 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_next()
2636 *pos = ++state->pos; in iwl_dbgfs_tx_queue_seq_next()
2638 if (*pos >= priv->trans->trans_cfg->base_params->num_of_queues) in iwl_dbgfs_tx_queue_seq_next()
2651 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; in iwl_dbgfs_tx_queue_seq_show()
2653 struct iwl_trans *trans = priv->trans; in iwl_dbgfs_tx_queue_seq_show()
2655 struct iwl_txq *txq = trans_pcie->txqs.txq[state->pos]; in iwl_dbgfs_tx_queue_seq_show()
2658 (unsigned int)state->pos, in iwl_dbgfs_tx_queue_seq_show()
2659 !!test_bit(state->pos, trans_pcie->txqs.queue_used), in iwl_dbgfs_tx_queue_seq_show()
2660 !!test_bit(state->pos, trans_pcie->txqs.queue_stopped)); in iwl_dbgfs_tx_queue_seq_show()
2664 txq->read_ptr, txq->write_ptr, in iwl_dbgfs_tx_queue_seq_show()
2665 txq->need_update, txq->frozen, in iwl_dbgfs_tx_queue_seq_show()
2666 txq->n_window, txq->ampdu); in iwl_dbgfs_tx_queue_seq_show()
2670 if (state->pos == trans_pcie->txqs.cmd.q_id) in iwl_dbgfs_tx_queue_seq_show()
2692 return -ENOMEM; in iwl_dbgfs_tx_queue_open()
2694 priv->trans = inode->i_private; in iwl_dbgfs_tx_queue_open()
2702 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rx_queue_read()
2708 bufsz = sizeof(char) * 121 * trans->num_rx_queues; in iwl_dbgfs_rx_queue_read()
2710 if (!trans_pcie->rxq) in iwl_dbgfs_rx_queue_read()
2711 return -EAGAIN; in iwl_dbgfs_rx_queue_read()
2715 return -ENOMEM; in iwl_dbgfs_rx_queue_read()
2717 for (i = 0; i < trans->num_rx_queues && pos < bufsz; i++) { in iwl_dbgfs_rx_queue_read()
2718 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; in iwl_dbgfs_rx_queue_read()
2720 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", in iwl_dbgfs_rx_queue_read()
2722 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", in iwl_dbgfs_rx_queue_read()
2723 rxq->read); in iwl_dbgfs_rx_queue_read()
2724 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", in iwl_dbgfs_rx_queue_read()
2725 rxq->write); in iwl_dbgfs_rx_queue_read()
2726 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", in iwl_dbgfs_rx_queue_read()
2727 rxq->write_actual); in iwl_dbgfs_rx_queue_read()
2728 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", in iwl_dbgfs_rx_queue_read()
2729 rxq->need_update); in iwl_dbgfs_rx_queue_read()
2730 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", in iwl_dbgfs_rx_queue_read()
2731 rxq->free_count); in iwl_dbgfs_rx_queue_read()
2732 if (rxq->rb_stts) { in iwl_dbgfs_rx_queue_read()
2734 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_rx_queue_read()
2737 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_rx_queue_read()
2751 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_read()
2753 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; in iwl_dbgfs_interrupt_read()
2762 return -ENOMEM; in iwl_dbgfs_interrupt_read()
2764 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2767 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
2768 isr_stats->hw); in iwl_dbgfs_interrupt_read()
2769 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
2770 isr_stats->sw); in iwl_dbgfs_interrupt_read()
2771 if (isr_stats->sw || isr_stats->hw) { in iwl_dbgfs_interrupt_read()
2772 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2774 isr_stats->err_code); in iwl_dbgfs_interrupt_read()
2777 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2778 isr_stats->sch); in iwl_dbgfs_interrupt_read()
2779 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2780 isr_stats->alive); in iwl_dbgfs_interrupt_read()
2782 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2783 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); in iwl_dbgfs_interrupt_read()
2785 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", in iwl_dbgfs_interrupt_read()
2786 isr_stats->ctkill); in iwl_dbgfs_interrupt_read()
2788 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2789 isr_stats->wakeup); in iwl_dbgfs_interrupt_read()
2791 pos += scnprintf(buf + pos, bufsz - pos, in iwl_dbgfs_interrupt_read()
2792 "Rx command responses:\t\t %u\n", isr_stats->rx); in iwl_dbgfs_interrupt_read()
2794 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2795 isr_stats->tx); in iwl_dbgfs_interrupt_read()
2797 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", in iwl_dbgfs_interrupt_read()
2798 isr_stats->unhandled); in iwl_dbgfs_interrupt_read()
2809 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_interrupt_write()
2811 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; in iwl_dbgfs_interrupt_write()
2828 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_csr_write()
2839 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_fh_reg_read()
2847 return -EINVAL; in iwl_dbgfs_fh_reg_read()
2857 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_read()
2863 trans_pcie->debug_rfkill, in iwl_dbgfs_rfkill_read()
2874 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rfkill_write()
2882 if (new_value == trans_pcie->debug_rfkill) in iwl_dbgfs_rfkill_write()
2884 IWL_WARN(trans, "changing debug rfkill %d->%d\n", in iwl_dbgfs_rfkill_write()
2885 trans_pcie->debug_rfkill, new_value); in iwl_dbgfs_rfkill_write()
2886 trans_pcie->debug_rfkill = new_value; in iwl_dbgfs_rfkill_write()
2895 struct iwl_trans *trans = inode->i_private; in iwl_dbgfs_monitor_data_open()
2898 if (!trans->dbg.dest_tlv || in iwl_dbgfs_monitor_data_open()
2899 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { in iwl_dbgfs_monitor_data_open()
2901 return -ENOENT; in iwl_dbgfs_monitor_data_open()
2904 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) in iwl_dbgfs_monitor_data_open()
2905 return -EBUSY; in iwl_dbgfs_monitor_data_open()
2907 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; in iwl_dbgfs_monitor_data_open()
2915 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); in iwl_dbgfs_monitor_data_release()
2917 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) in iwl_dbgfs_monitor_data_release()
2918 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; in iwl_dbgfs_monitor_data_release()
2926 ssize_t buf_size_left = count - *bytes_copied; in iwl_write_to_user_buf()
2928 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); in iwl_write_to_user_buf()
2932 *size -= copy_to_user(user_buf, buf, *size); in iwl_write_to_user_buf()
2944 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_monitor_data_read()
2946 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; in iwl_dbgfs_monitor_data_read()
2947 struct cont_rec *data = &trans_pcie->fw_mon_data; in iwl_dbgfs_monitor_data_read()
2952 if (trans->dbg.dest_tlv) { in iwl_dbgfs_monitor_data_read()
2954 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_dbgfs_monitor_data_read()
2955 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_dbgfs_monitor_data_read()
2961 if (unlikely(!trans->dbg.rec_on)) in iwl_dbgfs_monitor_data_read()
2964 mutex_lock(&data->mutex); in iwl_dbgfs_monitor_data_read()
2965 if (data->state == in iwl_dbgfs_monitor_data_read()
2967 mutex_unlock(&data->mutex); in iwl_dbgfs_monitor_data_read()
2975 if (data->prev_wrap_cnt == wrap_cnt) { in iwl_dbgfs_monitor_data_read()
2976 size = write_ptr - data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2977 curr_buf = cpu_addr + data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2981 data->prev_wr_ptr += size; in iwl_dbgfs_monitor_data_read()
2983 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && in iwl_dbgfs_monitor_data_read()
2984 write_ptr < data->prev_wr_ptr) { in iwl_dbgfs_monitor_data_read()
2985 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2986 curr_buf = cpu_addr + data->prev_wr_ptr; in iwl_dbgfs_monitor_data_read()
2990 data->prev_wr_ptr += size; in iwl_dbgfs_monitor_data_read()
2997 data->prev_wr_ptr = size; in iwl_dbgfs_monitor_data_read()
2998 data->prev_wrap_cnt++; in iwl_dbgfs_monitor_data_read()
3001 if (data->prev_wrap_cnt == wrap_cnt - 1 && in iwl_dbgfs_monitor_data_read()
3002 write_ptr > data->prev_wr_ptr) in iwl_dbgfs_monitor_data_read()
3005 else if (!unlikely(data->prev_wrap_cnt == 0 && in iwl_dbgfs_monitor_data_read()
3006 data->prev_wr_ptr == 0)) in iwl_dbgfs_monitor_data_read()
3014 data->prev_wr_ptr = size; in iwl_dbgfs_monitor_data_read()
3015 data->prev_wrap_cnt = wrap_cnt; in iwl_dbgfs_monitor_data_read()
3018 mutex_unlock(&data->mutex); in iwl_dbgfs_monitor_data_read()
3027 struct iwl_trans *trans = file->private_data; in iwl_dbgfs_rf_read()
3030 if (!trans_pcie->rf_name[0]) in iwl_dbgfs_rf_read()
3031 return -ENODEV; in iwl_dbgfs_rf_read()
3034 trans_pcie->rf_name, in iwl_dbgfs_rf_read()
3035 strlen(trans_pcie->rf_name)); in iwl_dbgfs_rf_read()
3062 struct dentry *dir = trans->dbgfs_dir; in iwl_trans_pcie_dbgfs_register()
3077 struct cont_rec *data = &trans_pcie->fw_mon_data; in iwl_trans_pcie_debugfs_cleanup()
3079 mutex_lock(&data->mutex); in iwl_trans_pcie_debugfs_cleanup()
3080 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; in iwl_trans_pcie_debugfs_cleanup()
3081 mutex_unlock(&data->mutex); in iwl_trans_pcie_debugfs_cleanup()
3091 for (i = 0; i < trans_pcie->txqs.tfd.max_tbs; i++) in iwl_trans_pcie_get_cmdlen()
3102 int max_len = trans_pcie->rx_buf_bytes; in iwl_trans_pcie_dump_rbs()
3103 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ in iwl_trans_pcie_dump_rbs()
3104 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; in iwl_trans_pcie_dump_rbs()
3107 spin_lock_bh(&rxq->lock); in iwl_trans_pcie_dump_rbs()
3111 for (i = rxq->read, j = 0; in iwl_trans_pcie_dump_rbs()
3114 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; in iwl_trans_pcie_dump_rbs()
3117 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, in iwl_trans_pcie_dump_rbs()
3122 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); in iwl_trans_pcie_dump_rbs()
3123 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); in iwl_trans_pcie_dump_rbs()
3124 rb = (void *)(*data)->data; in iwl_trans_pcie_dump_rbs()
3125 rb->index = cpu_to_le32(i); in iwl_trans_pcie_dump_rbs()
3126 memcpy(rb->data, page_address(rxb->page), max_len); in iwl_trans_pcie_dump_rbs()
3131 spin_unlock_bh(&rxq->lock); in iwl_trans_pcie_dump_rbs()
3144 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); in iwl_trans_pcie_dump_csr()
3145 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); in iwl_trans_pcie_dump_csr()
3146 val = (void *)(*data)->data; in iwl_trans_pcie_dump_csr()
3159 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; in iwl_trans_pcie_fh_regs_dump()
3166 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); in iwl_trans_pcie_fh_regs_dump()
3167 (*data)->len = cpu_to_le32(fh_regs_len); in iwl_trans_pcie_fh_regs_dump()
3168 val = (void *)(*data)->data; in iwl_trans_pcie_fh_regs_dump()
3170 if (!trans->trans_cfg->gen2) in iwl_trans_pcie_fh_regs_dump()
3194 u32 *buffer = (u32 *)fw_mon_data->data; in iwl_trans_pci_dump_marbh_monitor()
3215 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; in iwl_trans_pcie_dump_pointers() local
3217 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3218 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; in iwl_trans_pcie_dump_pointers()
3222 } else if (trans->dbg.dest_tlv) { in iwl_trans_pcie_dump_pointers()
3223 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); in iwl_trans_pcie_dump_pointers()
3224 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); in iwl_trans_pcie_dump_pointers()
3225 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_pcie_dump_pointers()
3227 base = MON_BUFF_BASE_ADDR; in iwl_trans_pcie_dump_pointers()
3233 fw_mon_data->fw_mon_cycle_cnt = in iwl_trans_pcie_dump_pointers()
3235 fw_mon_data->fw_mon_base_ptr = in iwl_trans_pcie_dump_pointers()
3236 cpu_to_le32(iwl_read_prph(trans, base)); in iwl_trans_pcie_dump_pointers()
3237 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { in iwl_trans_pcie_dump_pointers()
3238 fw_mon_data->fw_mon_base_high_ptr = in iwl_trans_pcie_dump_pointers()
3244 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); in iwl_trans_pcie_dump_pointers()
3252 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; in iwl_trans_pcie_dump_monitor()
3255 if (trans->dbg.dest_tlv || in iwl_trans_pcie_dump_monitor()
3256 (fw_mon->size && in iwl_trans_pcie_dump_monitor()
3257 (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000 || in iwl_trans_pcie_dump_monitor()
3258 trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { in iwl_trans_pcie_dump_monitor()
3261 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); in iwl_trans_pcie_dump_monitor()
3262 fw_mon_data = (void *)(*data)->data; in iwl_trans_pcie_dump_monitor()
3267 if (fw_mon->size) { in iwl_trans_pcie_dump_monitor()
3268 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); in iwl_trans_pcie_dump_monitor()
3269 monitor_len = fw_mon->size; in iwl_trans_pcie_dump_monitor()
3270 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { in iwl_trans_pcie_dump_monitor()
3271 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); in iwl_trans_pcie_dump_monitor() local
3276 if (trans->dbg.dest_tlv->version) { in iwl_trans_pcie_dump_monitor()
3277 base = (iwl_read_prph(trans, base) & in iwl_trans_pcie_dump_monitor()
3279 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3280 base *= IWL_M2S_UNIT_SIZE; in iwl_trans_pcie_dump_monitor()
3281 base += trans->cfg->smem_offset; in iwl_trans_pcie_dump_monitor()
3283 base = iwl_read_prph(trans, base) << in iwl_trans_pcie_dump_monitor()
3284 trans->dbg.dest_tlv->base_shift; in iwl_trans_pcie_dump_monitor()
3287 iwl_trans_read_mem(trans, base, fw_mon_data->data, in iwl_trans_pcie_dump_monitor()
3289 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { in iwl_trans_pcie_dump_monitor()
3295 /* Didn't match anything - output no monitor data */ in iwl_trans_pcie_dump_monitor()
3300 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); in iwl_trans_pcie_dump_monitor()
3308 if (trans->dbg.fw_mon.size) { in iwl_trans_get_fw_monitor_len()
3311 trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3312 return trans->dbg.fw_mon.size; in iwl_trans_get_fw_monitor_len()
3313 } else if (trans->dbg.dest_tlv) { in iwl_trans_get_fw_monitor_len()
3314 u32 base, end, cfg_reg, monitor_len; in iwl_trans_get_fw_monitor_len() local
3316 if (trans->dbg.dest_tlv->version == 1) { in iwl_trans_get_fw_monitor_len()
3317 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3319 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << in iwl_trans_get_fw_monitor_len()
3320 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3321 base *= IWL_M2S_UNIT_SIZE; in iwl_trans_get_fw_monitor_len()
3322 base += trans->cfg->smem_offset; in iwl_trans_get_fw_monitor_len()
3326 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3329 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); in iwl_trans_get_fw_monitor_len()
3330 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); in iwl_trans_get_fw_monitor_len()
3332 base = iwl_read_prph(trans, base) << in iwl_trans_get_fw_monitor_len()
3333 trans->dbg.dest_tlv->base_shift; in iwl_trans_get_fw_monitor_len()
3335 trans->dbg.dest_tlv->end_shift; in iwl_trans_get_fw_monitor_len()
3338 if (trans->trans_cfg->device_family >= in iwl_trans_get_fw_monitor_len()
3340 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) in iwl_trans_get_fw_monitor_len()
3341 end += (1 << trans->dbg.dest_tlv->end_shift); in iwl_trans_get_fw_monitor_len()
3342 monitor_len = end - base; in iwl_trans_get_fw_monitor_len()
3359 struct iwl_txq *cmdq = trans_pcie->txqs.txq[trans_pcie->txqs.cmd.q_id]; in iwl_trans_pcie_dump_data()
3364 bool dump_rbs = test_bit(STATUS_FW_ERROR, &trans->status) && in iwl_trans_pcie_dump_data()
3365 !trans->trans_cfg->mq_rx_supported && in iwl_trans_pcie_dump_data()
3377 cmdq->n_window * (sizeof(*txcmd) + in iwl_trans_pcie_dump_data()
3390 if (trans->trans_cfg->gen2) in iwl_trans_pcie_dump_data()
3392 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - in iwl_trans_pcie_dump_data()
3396 (FH_MEM_UPPER_BOUND - in iwl_trans_pcie_dump_data()
3401 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ in iwl_trans_pcie_dump_data()
3402 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; in iwl_trans_pcie_dump_data()
3405 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; in iwl_trans_pcie_dump_data()
3408 (PAGE_SIZE << trans_pcie->rx_page_order)); in iwl_trans_pcie_dump_data()
3412 if (trans->trans_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) in iwl_trans_pcie_dump_data()
3413 for (i = 0; i < trans->init_dram.paging_cnt; i++) in iwl_trans_pcie_dump_data()
3416 trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3423 data = (void *)dump_data->data; in iwl_trans_pcie_dump_data()
3426 u16 tfd_size = trans_pcie->txqs.tfd.size; in iwl_trans_pcie_dump_data()
3428 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); in iwl_trans_pcie_dump_data()
3429 txcmd = (void *)data->data; in iwl_trans_pcie_dump_data()
3430 spin_lock_bh(&cmdq->lock); in iwl_trans_pcie_dump_data()
3431 ptr = cmdq->write_ptr; in iwl_trans_pcie_dump_data()
3432 for (i = 0; i < cmdq->n_window; i++) { in iwl_trans_pcie_dump_data()
3437 if (trans->trans_cfg->gen2) in iwl_trans_pcie_dump_data()
3443 (u8 *)cmdq->tfds + in iwl_trans_pcie_dump_data()
3449 txcmd->cmdlen = cpu_to_le32(cmdlen); in iwl_trans_pcie_dump_data()
3450 txcmd->caplen = cpu_to_le32(caplen); in iwl_trans_pcie_dump_data()
3451 memcpy(txcmd->data, cmdq->entries[idx].cmd, in iwl_trans_pcie_dump_data()
3453 if (sanitize_ops && sanitize_ops->frob_hcmd) in iwl_trans_pcie_dump_data()
3454 sanitize_ops->frob_hcmd(sanitize_ctx, in iwl_trans_pcie_dump_data()
3455 txcmd->data, in iwl_trans_pcie_dump_data()
3457 txcmd = (void *)((u8 *)txcmd->data + caplen); in iwl_trans_pcie_dump_data()
3462 spin_unlock_bh(&cmdq->lock); in iwl_trans_pcie_dump_data()
3464 data->len = cpu_to_le32(len); in iwl_trans_pcie_dump_data()
3477 if (trans->trans_cfg->gen2 && in iwl_trans_pcie_dump_data()
3479 for (i = 0; i < trans->init_dram.paging_cnt; i++) { in iwl_trans_pcie_dump_data()
3481 u32 page_len = trans->init_dram.paging[i].size; in iwl_trans_pcie_dump_data()
3483 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); in iwl_trans_pcie_dump_data()
3484 data->len = cpu_to_le32(sizeof(*paging) + page_len); in iwl_trans_pcie_dump_data()
3485 paging = (void *)data->data; in iwl_trans_pcie_dump_data()
3486 paging->index = cpu_to_le32(i); in iwl_trans_pcie_dump_data()
3487 memcpy(paging->data, in iwl_trans_pcie_dump_data()
3488 trans->init_dram.paging[i].block, page_len); in iwl_trans_pcie_dump_data()
3497 dump_data->len = len; in iwl_trans_pcie_dump_data()
3515 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_sync_nmi()
3517 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_sync_nmi()
3551 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, in iwl_trans_pcie_alloc()
3554 return ERR_PTR(-ENOMEM); in iwl_trans_pcie_alloc()
3558 if (trans->trans_cfg->gen2) { in iwl_trans_pcie_alloc()
3559 trans_pcie->txqs.tfd.addr_size = 64; in iwl_trans_pcie_alloc()
3560 trans_pcie->txqs.tfd.max_tbs = IWL_TFH_NUM_TBS; in iwl_trans_pcie_alloc()
3561 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfh_tfd); in iwl_trans_pcie_alloc()
3563 trans_pcie->txqs.tfd.addr_size = 36; in iwl_trans_pcie_alloc()
3564 trans_pcie->txqs.tfd.max_tbs = IWL_NUM_OF_TBS; in iwl_trans_pcie_alloc()
3565 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfd); in iwl_trans_pcie_alloc()
3567 trans->max_skb_frags = IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie); in iwl_trans_pcie_alloc()
3570 trans_pcie->txqs.cmd.wdg_timeout = IWL_DEF_WD_TIMEOUT; in iwl_trans_pcie_alloc()
3572 trans_pcie->txqs.tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); in iwl_trans_pcie_alloc()
3573 if (!trans_pcie->txqs.tso_hdr_page) { in iwl_trans_pcie_alloc()
3574 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3578 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) in iwl_trans_pcie_alloc()
3579 trans_pcie->txqs.bc_tbl_size = in iwl_trans_pcie_alloc()
3581 else if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) in iwl_trans_pcie_alloc()
3582 trans_pcie->txqs.bc_tbl_size = in iwl_trans_pcie_alloc()
3585 trans_pcie->txqs.bc_tbl_size = sizeof(struct iwlagn_scd_bc_tbl); in iwl_trans_pcie_alloc()
3587 * For gen2 devices, we use a single allocation for each byte-count in iwl_trans_pcie_alloc()
3591 if (trans->trans_cfg->gen2) { in iwl_trans_pcie_alloc()
3592 trans_pcie->txqs.bc_pool = in iwl_trans_pcie_alloc()
3593 dmam_pool_create("iwlwifi:bc", trans->dev, in iwl_trans_pcie_alloc()
3594 trans_pcie->txqs.bc_tbl_size, in iwl_trans_pcie_alloc()
3596 if (!trans_pcie->txqs.bc_pool) { in iwl_trans_pcie_alloc()
3597 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3603 WARN_ON(trans_pcie->txqs.tfd.addr_size != in iwl_trans_pcie_alloc()
3604 (trans->trans_cfg->gen2 ? 64 : 36)); in iwl_trans_pcie_alloc()
3606 /* Initialize NAPI here - it should be before registering to mac80211 in iwl_trans_pcie_alloc()
3609 trans_pcie->napi_dev = alloc_netdev_dummy(sizeof(struct iwl_trans_pcie *)); in iwl_trans_pcie_alloc()
3610 if (!trans_pcie->napi_dev) { in iwl_trans_pcie_alloc()
3611 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3615 priv = netdev_priv(trans_pcie->napi_dev); in iwl_trans_pcie_alloc()
3618 trans_pcie->trans = trans; in iwl_trans_pcie_alloc()
3619 trans_pcie->opmode_down = true; in iwl_trans_pcie_alloc()
3620 spin_lock_init(&trans_pcie->irq_lock); in iwl_trans_pcie_alloc()
3621 spin_lock_init(&trans_pcie->reg_lock); in iwl_trans_pcie_alloc()
3622 spin_lock_init(&trans_pcie->alloc_page_lock); in iwl_trans_pcie_alloc()
3623 mutex_init(&trans_pcie->mutex); in iwl_trans_pcie_alloc()
3624 init_waitqueue_head(&trans_pcie->ucode_write_waitq); in iwl_trans_pcie_alloc()
3625 init_waitqueue_head(&trans_pcie->fw_reset_waitq); in iwl_trans_pcie_alloc()
3626 init_waitqueue_head(&trans_pcie->imr_waitq); in iwl_trans_pcie_alloc()
3628 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", in iwl_trans_pcie_alloc()
3630 if (!trans_pcie->rba.alloc_wq) { in iwl_trans_pcie_alloc()
3631 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3634 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); in iwl_trans_pcie_alloc()
3636 trans_pcie->debug_rfkill = -1; in iwl_trans_pcie_alloc()
3638 if (!cfg_trans->base_params->pcie_l1_allowed) { in iwl_trans_pcie_alloc()
3640 * W/A - seems to solve weird behavior. We need to remove this in iwl_trans_pcie_alloc()
3651 addr_size = trans_pcie->txqs.tfd.addr_size; in iwl_trans_pcie_alloc()
3652 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); in iwl_trans_pcie_alloc()
3654 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in iwl_trans_pcie_alloc()
3657 dev_err(&pdev->dev, "No suitable DMA available\n"); in iwl_trans_pcie_alloc()
3664 dev_err(&pdev->dev, "pcim_iomap_regions_request_all failed\n"); in iwl_trans_pcie_alloc()
3670 dev_err(&pdev->dev, "pcim_iomap_table failed\n"); in iwl_trans_pcie_alloc()
3671 ret = -ENOMEM; in iwl_trans_pcie_alloc()
3675 trans_pcie->hw_base = table[0]; in iwl_trans_pcie_alloc()
3676 if (!trans_pcie->hw_base) { in iwl_trans_pcie_alloc()
3677 dev_err(&pdev->dev, "couldn't find IO mem in first BAR\n"); in iwl_trans_pcie_alloc()
3678 ret = -ENODEV; in iwl_trans_pcie_alloc()
3686 trans_pcie->pci_dev = pdev; in iwl_trans_pcie_alloc()
3689 trans->hw_rev = iwl_read32(trans, CSR_HW_REV); in iwl_trans_pcie_alloc()
3690 if (trans->hw_rev == 0xffffffff) { in iwl_trans_pcie_alloc()
3691 dev_err(&pdev->dev, "HW_REV=0xFFFFFFFF, PCI issues?\n"); in iwl_trans_pcie_alloc()
3692 ret = -EIO; in iwl_trans_pcie_alloc()
3698 * changed, and now the revision step also includes bit 0-1 (no more in iwl_trans_pcie_alloc()
3699 * "dash" value). To keep hw_rev backwards compatible - we'll store it in iwl_trans_pcie_alloc()
3702 if (cfg_trans->device_family >= IWL_DEVICE_FAMILY_8000) in iwl_trans_pcie_alloc()
3703 trans->hw_rev_step = trans->hw_rev & 0xF; in iwl_trans_pcie_alloc()
3705 trans->hw_rev_step = (trans->hw_rev & 0xC) >> 2; in iwl_trans_pcie_alloc()
3707 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", trans->hw_rev); in iwl_trans_pcie_alloc()
3710 trans->hw_id = (pdev->device << 16) + pdev->subsystem_device; in iwl_trans_pcie_alloc()
3711 snprintf(trans->hw_id_str, sizeof(trans->hw_id_str), in iwl_trans_pcie_alloc()
3712 "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device); in iwl_trans_pcie_alloc()
3714 init_waitqueue_head(&trans_pcie->sx_waitq); in iwl_trans_pcie_alloc()
3720 if (trans_pcie->msix_enabled) { in iwl_trans_pcie_alloc()
3729 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, in iwl_trans_pcie_alloc()
3734 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); in iwl_trans_pcie_alloc()
3740 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; in iwl_trans_pcie_alloc()
3741 mutex_init(&trans_pcie->fw_mon_data.mutex); in iwl_trans_pcie_alloc()
3751 destroy_workqueue(trans_pcie->rba.alloc_wq); in iwl_trans_pcie_alloc()
3753 free_netdev(trans_pcie->napi_dev); in iwl_trans_pcie_alloc()
3755 free_percpu(trans_pcie->txqs.tso_hdr_page); in iwl_trans_pcie_alloc()
3783 int ret = -1; in iwl_trans_pcie_copy_imr()
3785 trans_pcie->imr_status = IMR_D2S_REQUESTED; in iwl_trans_pcie_copy_imr()
3787 ret = wait_event_timeout(trans_pcie->imr_waitq, in iwl_trans_pcie_copy_imr()
3788 trans_pcie->imr_status != in iwl_trans_pcie_copy_imr()
3790 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { in iwl_trans_pcie_copy_imr()
3793 return -ETIMEDOUT; in iwl_trans_pcie_copy_imr()
3795 trans_pcie->imr_status = IMR_D2S_IDLE; in iwl_trans_pcie_copy_imr()