Lines Matching +full:0 +full:x1ff00000
14 #define IWL_RX_INFO_ENERGY_ANT_A_MSK 0x000000ff
15 #define IWL_RX_INFO_ENERGY_ANT_B_MSK 0x0000ff00
16 #define IWL_RX_INFO_ENERGY_ANT_A_POS 0
27 * (REPLY_RX_PHY_CMD = 0xc0)
70 * bits 0:3 - reserved
78 CSUM_RXA_RESERVED_MASK = 0x000f,
79 CSUM_RXA_MICSIZE_MASK = 0x00f0,
80 CSUM_RXA_HEADERLEN_MASK = 0x1f00,
110 RX_RES_PHY_FLAGS_BAND_24 = BIT(0),
114 RX_RES_PHY_FLAGS_ANTENNA = (0x7 << 4),
151 RX_MPDU_RES_STATUS_CRC_OK = BIT(0),
159 RX_MPDU_RES_STATUS_SEC_NO_ENC = (0 << 8),
171 RX_MPDU_RES_STATUS_STA_ID_MSK = 0x1f << RX_MDPU_RES_STATUS_STA_ID_SHIFT,
176 IWL_RX_MDPU_MFLG1_ADDRTYPE_MASK = 0x03,
177 IWL_RX_MPDU_MFLG1_MIC_CRC_LEN_MASK = 0xf0,
186 IWL_RX_MPDU_MFLG2_HDR_LEN_MASK = 0x1f,
187 IWL_RX_MPDU_MFLG2_PAD = 0x20,
188 IWL_RX_MPDU_MFLG2_AMSDU = 0x40,
192 IWL_RX_MPDU_AMSDU_SUBFRAME_IDX_MASK = 0x7f,
193 IWL_RX_MPDU_AMSDU_LAST_SUBFRAME = 0x80,
197 #define RX_MPDU_BAND_MASK 0xC0
215 IWL_RX_L3L4_IP_HDR_CSUM_OK = BIT(0),
219 IWL_RX_L3L4_L3_PROTO_MASK = 0xf << IWL_RX_L3_PROTO_POS,
220 IWL_RX_L3L4_L4_PROTO_MASK = 0xf << 8,
221 IWL_RX_L3L4_RSS_HASH_MASK = 0xf << 12,
225 IWL_RX_MPDU_STATUS_CRC_OK = BIT(0),
234 IWL_RX_MPDU_STATUS_SEC_MASK = 0x7 << 8,
236 IWL_RX_MPDU_STATUS_SEC_NONE = 0x0 << 8,
237 IWL_RX_MPDU_STATUS_SEC_WEP = 0x1 << 8,
238 IWL_RX_MPDU_STATUS_SEC_CCM = 0x2 << 8,
239 IWL_RX_MPDU_STATUS_SEC_TKIP = 0x3 << 8,
240 IWL_RX_MPDU_STATUS_SEC_EXT_ENC = 0x4 << 8,
241 IWL_RX_MPDU_STATUS_SEC_GCM = 0x5 << 8,
247 IWL_RX_MPDU_STATUS_STA_ID = 0x1f000000,
250 #define IWL_RX_REORDER_DATA_INVALID_BAID 0x7f
253 IWL_RX_MPDU_REORDER_NSSN_MASK = 0x00000fff,
254 IWL_RX_MPDU_REORDER_SN_MASK = 0x00fff000,
256 IWL_RX_MPDU_REORDER_BAID_MASK = 0x7f000000,
258 IWL_RX_MPDU_REORDER_BA_OLD_SN = 0x80000000,
271 IWL_RX_MPDU_PHY_MAC_INDEX_MASK = 0x0f,
272 IWL_RX_MPDU_PHY_PHY_INDEX_MASK = 0xf0,
278 IWL_RX_PHY_DATA0_HE_BEAM_CHNG = 0x00000001,
279 IWL_RX_PHY_DATA0_HE_UPLINK = 0x00000002,
280 IWL_RX_PHY_DATA0_HE_BSS_COLOR_MASK = 0x000000fc,
281 IWL_RX_PHY_DATA0_HE_SPATIAL_REUSE_MASK = 0x00000f00,
283 IWL_RX_PHY_DATA0_HE_TXOP_DUR_MASK = 0x000fe000,
284 IWL_RX_PHY_DATA0_HE_LDPC_EXT_SYM = 0x00100000,
285 IWL_RX_PHY_DATA0_HE_PRE_FEC_PAD_MASK = 0x00600000,
286 IWL_RX_PHY_DATA0_HE_PE_DISAMBIG = 0x00800000,
287 IWL_RX_PHY_DATA0_HE_DOPPLER = 0x01000000,
289 IWL_RX_PHY_DATA0_HE_DELIM_EOF = 0x80000000,
295 IWL_RX_PHY_DATA0_EHT_VALIDATE = BIT(0),
297 IWL_RX_PHY_DATA0_EHT_BSS_COLOR_MASK = 0x000000fc,
298 IWL_RX_PHY_DATA0_ETH_SPATIAL_REUSE_MASK = 0x00000f00,
300 IWL_RX_PHY_DATA0_EHT_TXOP_DUR_MASK = 0x000fe000,
302 IWL_RX_PHY_DATA0_EHT_PRE_FEC_PAD_MASK = 0x00600000,
306 IWL_RX_PHY_DATA0_EHT_PHY_VER = 0x1c000000,
312 IWL_RX_PHY_INFO_TYPE_NONE = 0,
335 IWL_RX_PHY_DATA1_INFO_TYPE_MASK = 0xf0000000,
338 IWL_RX_PHY_DATA1_LSIG_LEN_MASK = 0x0fff0000,
344 IWL_RX_PHY_DATA1_HE_MU_SIGB_COMPRESSION = 0x00000001,
345 IWL_RX_PHY_DATA1_HE_MU_SIBG_SYM_OR_USER_NUM_MASK = 0x0000001e,
348 IWL_RX_PHY_DATA1_HE_LTF_NUM_MASK = 0x000000e0,
349 IWL_RX_PHY_DATA1_HE_RU_ALLOC_SEC80 = 0x00000100,
351 IWL_RX_PHY_DATA1_HE_RU_ALLOC_MASK = 0x0000fe00,
354 IWL_RX_PHY_DATA1_HE_TB_PILOT_TYPE = 0x00000001,
355 IWL_RX_PHY_DATA1_HE_TB_LOW_SS_MASK = 0x0000000e,
361 IWL_RX_PHY_DATA1_EHT_MU_NUM_SIG_SYM_USIGA2 = 0x0000001f,
363 IWL_RX_PHY_DATA1_EHT_TB_PILOT_TYPE = BIT(0),
364 IWL_RX_PHY_DATA1_EHT_TB_LOW_SS = 0x0000001e,
367 /* number of EHT-LTF symbols 0 - 1 EHT-LTF, 1 - 2 EHT-LTFs, 2 - 4 EHT-LTFs,
369 IWL_RX_PHY_DATA1_EHT_SIG_LTF_NUM = 0x000000e0,
370 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B0 = 0x00000100,
371 IWL_RX_PHY_DATA1_EHT_RU_ALLOC_B1_B7 = 0x0000fe00,
378 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU0 = 0x000000ff, /* a1 */
379 IWL_RX_PHY_DATA2_HE_MU_EXT_CH1_RU2 = 0x0000ff00, /* a2 */
380 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU0 = 0x00ff0000, /* b1 */
381 IWL_RX_PHY_DATA2_HE_MU_EXT_CH2_RU2 = 0xff000000, /* b2 */
384 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE1 = 0x0000000f,
385 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE2 = 0x000000f0,
386 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE3 = 0x00000f00,
387 IWL_RX_PHY_DATA2_HE_TB_EXT_SPTL_REUSE4 = 0x0000f000,
393 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU1 = 0x000000ff, /* c1 */
394 IWL_RX_PHY_DATA3_HE_MU_EXT_CH1_RU3 = 0x0000ff00, /* c2 */
395 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU1 = 0x00ff0000, /* d1 */
396 IWL_RX_PHY_DATA3_HE_MU_EXT_CH2_RU3 = 0xff000000, /* d2 */
402 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CTR_RU = 0x0001,
403 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CTR_RU = 0x0002,
404 IWL_RX_PHY_DATA4_HE_MU_EXT_CH1_CRC_OK = 0x0004,
405 IWL_RX_PHY_DATA4_HE_MU_EXT_CH2_CRC_OK = 0x0008,
406 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_MCS_MASK = 0x00f0,
407 IWL_RX_PHY_DATA4_HE_MU_EXT_SIGB_DCM = 0x0100,
408 IWL_RX_PHY_DATA4_HE_MU_EXT_PREAMBLE_PUNC_TYPE_MASK = 0x0600,
414 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A1 = 0x000001ff,
415 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_A2 = 0x0003fe00,
416 IWL_RX_PHY_DATA2_EHT_MU_EXT_RU_ALLOC_B1 = 0x07fc0000,
419 IWL_RX_PHY_DATA2_EHT_TB_EXT_TRIG_SIGA1 = 0xffffffff,
426 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C1 = 0x0003fe00,
427 IWL_RX_PHY_DATA3_EHT_MU_EXT_RU_ALLOC_C2 = 0x07fc0000,
433 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D1 = 0x000001ff,
434 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_D2 = 0x0003fe00,
435 IWL_RX_PHY_DATA4_EHT_MU_EXT_SIGB_MCS = 0x000c0000,
436 IWL_RX_PHY_DATA4_EHT_MU_EXT_RU_ALLOC_B2 = 0x1ff00000,
442 IWL_RX_PHY_DATA5_EHT_TYPE_AND_COMP = 0x00000003,
444 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE1 = 0x0000003c,
445 IWL_RX_PHY_DATA5_EHT_TB_SPATIAL_REUSE2 = 0x000003c0,
447 IWL_RX_PHY_DATA5_EHT_MU_PUNC_CH_CODE = 0x0000007c,
448 IWL_RX_PHY_DATA5_EHT_MU_STA_ID_USR = 0x0003ff80,
449 IWL_RX_PHY_DATA5_EHT_MU_NUM_USR_NON_OFDMA = 0x001c0000,
450 IWL_RX_PHY_DATA5_EHT_MU_SPATIAL_CONF_USR_FIELD = 0x0fe00000,
567 * @partial_hash: 31:0 ip/tcp header hash
730 #define RX_NO_DATA_CHAIN_A_POS 0
731 #define RX_NO_DATA_CHAIN_A_MSK (0xff << RX_NO_DATA_CHAIN_A_POS)
733 #define RX_NO_DATA_CHAIN_B_MSK (0xff << RX_NO_DATA_CHAIN_B_POS)
735 #define RX_NO_DATA_CHANNEL_MSK (0xff << RX_NO_DATA_CHANNEL_POS)
737 #define RX_NO_DATA_INFO_TYPE_POS 0
738 #define RX_NO_DATA_INFO_TYPE_MSK (0xff << RX_NO_DATA_INFO_TYPE_POS)
739 #define RX_NO_DATA_INFO_TYPE_NONE 0
746 #define RX_NO_DATA_INFO_ERR_MSK (0xff << RX_NO_DATA_INFO_ERR_POS)
747 #define RX_NO_DATA_INFO_ERR_NONE 0
754 #define RX_NO_DATA_FRAME_TIME_POS 0
755 #define RX_NO_DATA_FRAME_TIME_MSK (0xfffff << RX_NO_DATA_FRAME_TIME_POS)
757 #define RX_NO_DATA_RX_VEC0_HE_NSTS_MSK 0x03800000
758 #define RX_NO_DATA_RX_VEC0_VHT_NSTS_MSK 0x38000000
759 #define RX_NO_DATA_RX_VEC2_EHT_NSTS_MSK 0x00f00000
763 IWL_RX_USIG_A1_ENHANCED_WIFI_VER_ID = 0x00000007,
764 IWL_RX_USIG_A1_BANDWIDTH = 0x00000038,
765 IWL_RX_USIG_A1_UL_FLAG = 0x00000040,
766 IWL_RX_USIG_A1_BSS_COLOR = 0x00001f80,
767 IWL_RX_USIG_A1_TXOP_DURATION = 0x000fe000,
768 IWL_RX_USIG_A1_DISREGARD = 0x01f00000,
769 IWL_RX_USIG_A1_VALIDATE = 0x02000000,
770 IWL_RX_USIG_A1_EHT_BW320_SLOT = 0x04000000,
771 IWL_RX_USIG_A1_EHT_TYPE = 0x18000000,
772 IWL_RX_USIG_A1_RDY = 0x80000000,
777 IWL_RX_USIG_A2_EHT_PPDU_TYPE = 0x00000003,
778 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B2 = 0x00000004,
779 IWL_RX_USIG_A2_EHT_PUNC_CHANNEL = 0x000000f8,
780 IWL_RX_USIG_A2_EHT_USIG2_VALIDATE_B8 = 0x00000100,
781 IWL_RX_USIG_A2_EHT_SIG_MCS = 0x00000600,
782 IWL_RX_USIG_A2_EHT_SIG_SYM_NUM = 0x0000f800,
783 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_1 = 0x000f0000,
784 IWL_RX_USIG_A2_EHT_TRIG_SPATIAL_REUSE_2 = 0x00f00000,
785 IWL_RX_USIG_A2_EHT_TRIG_USIG2_DISREGARD = 0x1f000000,
786 IWL_RX_USIG_A2_EHT_CRC_OK = 0x40000000,
787 IWL_RX_USIG_A2_EHT_RDY = 0x80000000,
792 * @info: 7:0 frame type, 15:8 RX error type
793 * @rssi: 7:0 energy chain-A,
817 * @info: 7:0 frame type, 15:8 RX error type
818 * @rssi: 7:0 energy chain-A,
854 IWL_BAR_FRAME_RELEASE_TID_MASK = 0x0000000f,
855 IWL_BAR_FRAME_RELEASE_STA_MASK = 0x000001f0,
865 IWL_BAR_FRAME_RELEASE_NSSN_MASK = 0x00000fff,
866 IWL_BAR_FRAME_RELEASE_SN_MASK = 0x00fff000,
867 IWL_BAR_FRAME_RELEASE_BAID_MASK = 0x3f000000,
896 * @flags: 1 - enable, 0 - disable
910 #define IWL_MULTI_QUEUE_SYNC_SENDER_POS 0
911 #define IWL_MULTI_QUEUE_SYNC_SENDER_MSK 0xf
916 * @flags: flags of the notification. bit 0:3 are the sender queue
967 #define BA_WINDOW_STATUS_TID_MSK 0x000F
969 #define BA_WINDOW_STATUS_STA_ID_MSK 0x01F0
974 * @bitmap: bitmap of received frames [start_seq_num + 0]..[start_seq_num + 63]
975 * @ra_tid: bit 3:0 - TID, bit 8:4 - STA_ID, bit 9 - valid