131 	il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0);  in il4965_rx_init()
134 	il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);  in il4965_rx_init()
137 	il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8));  in il4965_rx_init()
140 	il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4);  in il4965_rx_init()
148 	il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG,  in il4965_rx_init()
1999 	il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);  in il4965_txq_ctx_alloc()
2034 	il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4);  in il4965_txq_ctx_reset()
3999 	il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8);  in il4965_hw_tx_queue_init()
4123 		il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);  in il4965_hdl_card_state()
4128 			il_wr(il, HBUS_TARG_MBX_C,  in il4965_hdl_card_state()
5179 		il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan),  in il4965_alive_notify()
5185 	il_wr(il, FH49_TX_CHICKEN_BITS_REG,  in il4965_alive_notify()
5196 		il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8));  in il4965_alive_notify()
6276 	il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8));  in il4965_set_wr_ptrs()