Lines Matching +full:0 +full:x18002000
21 #define SOCI_SB 0
25 #define DMP_DESC_TYPE_MSK 0x0000000F
26 #define DMP_DESC_EMPTY 0x00000000
27 #define DMP_DESC_VALID 0x00000001
28 #define DMP_DESC_COMPONENT 0x00000001
29 #define DMP_DESC_MASTER_PORT 0x00000003
30 #define DMP_DESC_ADDRESS 0x00000005
31 #define DMP_DESC_ADDRSIZE_GT32 0x00000008
32 #define DMP_DESC_EOT 0x0000000F
34 #define DMP_COMP_DESIGNER 0xFFF00000
36 #define DMP_COMP_PARTNUM 0x000FFF00
38 #define DMP_COMP_CLASS 0x000000F0
40 #define DMP_COMP_REVISION 0xFF000000
42 #define DMP_COMP_NUM_SWRAP 0x00F80000
44 #define DMP_COMP_NUM_MWRAP 0x0007C000
46 #define DMP_COMP_NUM_SPORT 0x00003E00
48 #define DMP_COMP_NUM_MPORT 0x000001F0
51 #define DMP_MASTER_PORT_UID 0x0000FF00
53 #define DMP_MASTER_PORT_NUM 0x000000F0
56 #define DMP_SLAVE_ADDR_BASE 0xFFFFF000
58 #define DMP_SLAVE_PORT_NUM 0x00000F00
60 #define DMP_SLAVE_TYPE 0x000000C0
62 #define DMP_SLAVE_TYPE_SLAVE 0
66 #define DMP_SLAVE_SIZE_TYPE 0x00000030
68 #define DMP_SLAVE_SIZE_4K 0
74 #define CIB_REV_MASK 0xff000000
78 #define ARMCR4_BCMA_IOCTL_CPUHALT 0x0020
81 #define D11_BCMA_IOCTL_PHYCLOCKEN 0x0004
82 #define D11_BCMA_IOCTL_PHYRESET 0x0008
86 /* SDIO device core, ID 0x829 */
87 #define BCM4329_CORE_BUS_BASE 0x18011000
88 /* internal memory core, ID 0x80e */
89 #define BCM4329_CORE_SOCRAM_BASE 0x18003000
90 /* ARM Cortex M3 core, ID 0x82a */
91 #define BCM4329_CORE_ARM_BASE 0x18002000
142 #define INVALID_RAMBASE ((u32)(~0))
145 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
146 #define SOCRAM_BANKINFO_SZMASK 0x0000007f
147 #define SOCRAM_BANKIDX_ROM_MASK 0x00000100
151 #define SOCRAM_MEMTYPE_RAM 0
156 #define SRCI_LSS_MASK 0x00f00000
158 #define SRCI_SRNB_MASK 0xf0
159 #define SRCI_SRNB_MASK_EXT 0x100
161 #define SRCI_SRBSZ_MASK 0xf
162 #define SRCI_SRBSZ_SHIFT 0
205 #define ARMCR4_CAP (0x04)
206 #define ARMCR4_BANKIDX (0x40)
207 #define ARMCR4_BANKINFO (0x44)
208 #define ARMCR4_BANKPDA (0x4C)
210 #define ARMCR4_TCBBNB_MASK 0xf0
212 #define ARMCR4_TCBANB_MASK 0xf
213 #define ARMCR4_TCBANB_SHIFT 0
215 #define ARMCR4_BSZ_MASK 0x7f
217 #define ARMCR4_BLK_1K_MASK 0x200
275 ret = ret && ((regdata & BCMA_RESET_CTL_RESET) == 0); in brcmf_chip_ai_iscoreup()
293 if ((val & SSB_TMSLOW_CLOCK) != 0) { in brcmf_chip_sb_coredisable()
360 if ((regdata & BCMA_RESET_CTL_RESET) != 0) in brcmf_chip_ai_coredisable()
397 brcmf_chip_sb_coredisable(core, 0, 0); in brcmf_chip_sb_resetcore()
413 ci->ops->write32(ci->ctx, CORE_SB(base, sbtmstatehigh), 0); in brcmf_chip_sb_resetcore()
459 count = 0; in brcmf_chip_ai_resetcore()
462 ci->ops->write32(ci->ctx, core->wrapbase + BCMA_RESET_CTL, 0); in brcmf_chip_ai_resetcore()
470 count = 0; in brcmf_chip_ai_resetcore()
476 0); in brcmf_chip_ai_resetcore()
499 fmt = ((id > 0xa000) || (id < 0x4000)) ? "BCM%d/%u" : "BCM%x/%u"; in brcmf_chip_name()
533 brcmf_dbg(INFO, " [%-2d] core 0x%x:%-3d base 0x%08x wrap 0x%08x\n", in brcmf_chip_cores_check()
565 return 0; in brcmf_chip_cores_check()
601 *ramsize = 0; in brcmf_chip_socram_ramsize()
602 *srsize = 0; in brcmf_chip_socram_ramsize()
608 brcmf_chip_resetcore(&sr->pub, 0, 0, 0); in brcmf_chip_socram_ramsize()
617 if (lss != 0) in brcmf_chip_socram_ramsize()
620 if (lss != 0) in brcmf_chip_socram_ramsize()
630 for (i = 0; i < nb; i++) { in brcmf_chip_socram_ramsize()
659 u32 memsize = 0; in brcmf_chip_sysmem_ramsize()
666 brcmf_chip_resetcore(&sysmem->pub, 0, 0, 0); in brcmf_chip_sysmem_ramsize()
671 for (idx = 0; idx < nb; idx++) { in brcmf_chip_sysmem_ramsize()
683 u32 memsize = 0; in brcmf_chip_tcm_ramsize()
697 for (idx = 0; idx < totb; idx++) { in brcmf_chip_tcm_ramsize()
715 return 0x198000; in brcmf_chip_tcm_rambase()
727 return 0x180000; in brcmf_chip_tcm_rambase()
734 return 0x200000; in brcmf_chip_tcm_rambase()
737 return (ci->pub.chiprev < 9) ? 0x180000 : 0x160000; in brcmf_chip_tcm_rambase()
740 return 0x160000; in brcmf_chip_tcm_rambase()
743 return 0x170000; in brcmf_chip_tcm_rambase()
745 return 0x352000; in brcmf_chip_tcm_rambase()
747 return 0x740000; in brcmf_chip_tcm_rambase()
795 brcmf_dbg(INFO, "RAM: base=0x%x size=%d (0x%x) sr=%d (0x%x)\n", in brcmf_chip_get_raminfo()
809 return 0; in brcmf_chip_get_raminfo()
839 *regbase = 0; in brcmf_chip_dmp_get_regaddr()
840 *wrapbase = 0; in brcmf_chip_dmp_get_regaddr()
869 return 0; in brcmf_chip_dmp_get_regaddr()
894 if (*regbase == 0 && stype == DMP_SLAVE_TYPE_SLAVE) in brcmf_chip_dmp_get_regaddr()
896 if (*wrapbase == 0 && stype == wraptype) in brcmf_chip_dmp_get_regaddr()
898 } while (*regbase == 0 || *wrapbase == 0); in brcmf_chip_dmp_get_regaddr()
900 return 0; in brcmf_chip_dmp_get_regaddr()
908 u8 desc_type = 0; in brcmf_chip_dmp_erom_scan()
943 if (nmw + nsw == 0 && in brcmf_chip_dmp_erom_scan()
961 return 0; in brcmf_chip_dmp_erom_scan()
975 const u32 READ_FAILED = 0xFFFFFFFF; in brcmf_chip_recognition()
978 * Chipid is assume to be at offset 0 from SI_ENUM_BASE in brcmf_chip_recognition()
985 brcmf_err("MMIO read failed: 0x%08x\n", regdata); in brcmf_chip_recognition()
1008 SI_ENUM_BASE_DEFAULT, 0); in brcmf_chip_recognition()
1011 BCM4329_CORE_BUS_BASE, 0); in brcmf_chip_recognition()
1014 BCM4329_CORE_SOCRAM_BASE, 0); in brcmf_chip_recognition()
1017 BCM4329_CORE_ARM_BASE, 0); in brcmf_chip_recognition()
1020 core = brcmf_chip_add_core(ci, BCMA_CORE_80211, 0x18001000, 0); in brcmf_chip_recognition()
1065 brcmf_chip_coredisable(core, 0, 0); in brcmf_chip_disable_arm()
1090 int ret = 0; in brcmf_chip_setup()
1112 brcmf_dbg(INFO, "ccrev=%d, pmurev=%d, pmucaps=0x%x\n", in brcmf_chip_setup()
1126 int err = 0; in brcmf_chip_attach()
1136 if (err < 0) in brcmf_chip_attach()
1144 chip->num_cores = 0; in brcmf_chip_attach()
1150 if (err < 0) in brcmf_chip_attach()
1154 if (err < 0) in brcmf_chip_attach()
1158 if (err < 0) in brcmf_chip_attach()
1190 if (unit-- == 0) in brcmf_chip_get_d11core()
1277 brcmf_chip_resetcore(core, 0, 0, 0); in brcmf_chip_cm3_set_passive()
1284 brcmf_chip_core_write32(sr, SOCRAMREGOFFS(bankpda), 0); in brcmf_chip_cm3_set_passive()
1298 chip->ops->activate(chip->ctx, &chip->pub, 0); in brcmf_chip_cm3_set_active()
1301 brcmf_chip_resetcore(core, 0, 0, 0); in brcmf_chip_cm3_set_active()
1317 for (i = 0; (core = brcmf_chip_get_d11core(&chip->pub, i)); i++) in brcmf_chip_cr4_set_passive()
1331 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0); in brcmf_chip_cr4_set_active()
1358 brcmf_chip_resetcore(core, ARMCR4_BCMA_IOCTL_CPUHALT, 0, 0); in brcmf_chip_ca7_set_active()
1411 u32 base, addr, reg, pmu_cc3_mask = ~0; in brcmf_chip_sr_capable()
1440 return (reg & pmu_cc3_mask) != 0; in brcmf_chip_sr_capable()
1445 return reg != 0; in brcmf_chip_sr_capable()
1451 return (reg & CC_SR_CTL0_ENABLE_MASK) != 0; in brcmf_chip_sr_capable()
1458 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0; in brcmf_chip_sr_capable()
1462 if ((reg & PCAPEXT_SR_SUPPORTED_MASK) == 0) in brcmf_chip_sr_capable()
1468 PMU_RCTL_LOGIC_DISABLE_MASK)) == 0; in brcmf_chip_sr_capable()