broadcom/b43legacy/dma.h

1 /* SPDX-License-Identifier: GPL-2.0 */
14 /* DMA-Interrupt reasons. */
21 /*** 32-bit DMA Engine. ***/
23 /* 32-bit DMA controller registers. */
72 /* 32-bit DMA descriptor. */
109 	/* The kernel DMA-able buffer. */
111 	/* DMA base bus-address of the descriptor buffer. */
113 	/* ieee80211 TX status. Only used once per 802.11 frag. */
127 	/* Cache of TX headers for each slot.
128 	 * This is to avoid an allocation on each TX.
132 	/* (Unadjusted) DMA base bus-address of the ring memory. */
134 	/* Number of descriptor slots in the ring. */
136 	/* Number of used descriptor slots. */
146 	/* DMA controller index number (0-5). */
148 	/* Boolean. Is this a TX ring? */
149 	bool tx;  member
154 	/* The QOS priority assigned to this ring. Only used for TX rings.
159 	/* Maximum number of used slots. */
171 	return b43legacy_read32(ring->dev, ring->mmio_base + offset);  in b43legacy_dma_read()
178 	b43legacy_write32(ring->dev, ring->mmio_base + offset, value);  in b43legacy_dma_write()