Lines Matching +full:idle +full:- +full:wait +full:- +full:delay
1 /* SPDX-License-Identifier: GPL-2.0 */
9 /* N-PHY registers. */
18 #define B43_NPHY_4WI_ADDR B43_PHY_N(0x00B) /* Four-wire bus address */
19 #define B43_NPHY_4WI_DATAHI B43_PHY_N(0x00C) /* Four-wire bus data high */
20 #define B43_NPHY_4WI_DATALO B43_PHY_N(0x00D) /* Four-wire bus data low */
21 #define B43_NPHY_BIST_STAT0 B43_PHY_N(0x00E) /* Built-in self test status 0 */
22 #define B43_NPHY_BIST_STAT1 B43_PHY_N(0x00F) /* Built-in self test status 1 */
310 #define B43_NPHY_TXMACDELAY B43_PHY_N(0x0B4) /* TX MAC delay */
311 #define B43_NPHY_TXFRAMEDELAY B43_PHY_N(0x0B5) /* TX frame delay */
324 #define B43_NPHY_BPHY_CTL2_MACDEL 0x7FE0 /* MAC delay */
333 #define B43_NPHY_SAMP_WAITCNT B43_PHY_N(0x0C5) /* Sample wait count */
351 #define B43_NPHY_AFESEQ_RX2TX_PUD B43_PHY_N(0x0D7) /* AFE seq RX2TX power up/down delay */
352 #define B43_NPHY_AFESEQ_TX2RX_PUD B43_PHY_N(0x0D8) /* AFE seq TX2RX power up/down delay */
428 #define B43_NPHY_TSSI_MAXTXFDT B43_PHY_N(0x11C) /* TSSI max TX frame delay time */
429 #define B43_NPHY_TSSI_MAXTXFDT_VAL 0x00FF /* max TX frame delay time */
431 #define B43_NPHY_TSSI_MAXTDT B43_PHY_N(0x11D) /* TSSI max TSSI delay time */
432 #define B43_NPHY_TSSI_MAXTDT_VAL 0x00FF /* max TSSI delay time */
434 #define B43_NPHY_ITSSI1 B43_PHY_N(0x11E) /* TSSI idle 1 */
435 #define B43_NPHY_ITSSI2 B43_PHY_N(0x11F) /* TSSI idle 2 */
436 #define B43_NPHY_ITSSI_VAL 0x00FF /* Idle TSSI */
442 #define B43_NPHY_CRSIT_COCNT_LO B43_PHY_N(0x124) /* CRS idle time CRS-on count (low) */
443 #define B43_NPHY_CRSIT_COCNT_HI B43_PHY_N(0x125) /* CRS idle time CRS-on count (high) */
444 #define B43_NPHY_CRSIT_MTCNT_LO B43_PHY_N(0x126) /* CRS idle time measure time count (low) */
445 #define B43_NPHY_CRSIT_MTCNT_HI B43_PHY_N(0x127) /* CRS idle time measure time count (high) */
446 #define B43_NPHY_SAMTWC B43_PHY_N(0x128) /* Sample tail wait count */
450 #define B43_NPHY_IQEST_WT B43_PHY_N(0x12A) /* I/Q estimate wait time */
451 #define B43_NPHY_IQEST_WT_VAL 0x00FF /* Wait time */
469 #define B43_NPHY_MAXRSSI_DTIME B43_PHY_N(0x13F) /* RSSI max RSSI delay time */
477 #define B43_NPHY_PIL_DW_16QAM 0x0F00 /* 16-QAM */
479 #define B43_NPHY_PIL_DW_64QAM 0xF000 /* 64-QAM */
533 #define B43_NPHY_HTAGC_WCNT B43_PHY_N(0x17B) /* HT ADC wait counters */
598 #define B43_NPHY_SAMC_WCNT B43_PHY_N(0x1BC) /* Sample collect wait counter */
599 #define B43_NPHY_PTHROUGH_CNT B43_PHY_N(0x1BD) /* Pass-through counter */
642 #define B43_NPHY_TXPCTL_N_TSSID 0x00FF /* N TSSI delay */
646 #define B43_NPHY_TXPCTL_ITSSI B43_PHY_N(0x1E9) /* TX power control idle TSSI */
647 #define B43_NPHY_TXPCTL_ITSSI_0 0x003F /* Idle TSSI 0 */
649 #define B43_NPHY_TXPCTL_ITSSI_1 0x3F00 /* Idle TSSI 1 */
691 #define B43_NPHY_TXRIFS_FRDEL B43_PHY_N(0x1FF) /* TX RIFS frame delay */
692 #define B43_NPHY_AFESEQ_RX2TX_PUD_40M B43_PHY_N(0x200) /* AFE seq rx2tx power up/down delay 40M */
693 #define B43_NPHY_AFESEQ_TX2RX_PUD_40M B43_PHY_N(0x201) /* AFE seq tx2rx power up/down delay 40M */
694 #define B43_NPHY_AFESEQ_RX2TX_PUD_20M B43_PHY_N(0x202) /* AFE seq rx2tx power up/down delay 20M */
695 #define B43_NPHY_AFESEQ_TX2RX_PUD_20M B43_PHY_N(0x203) /* AFE seq tx2rx power up/down delay 20M */
700 #define B43_NPHY_AFESEQ_RX2TX_PUD_10M B43_PHY_N(0x208) /* AFE seq rx2tx power up/down delay 10M */
701 #define B43_NPHY_AFESEQ_TX2RX_PUD_10M B43_PHY_N(0x209) /* AFE seq tx2rx power up/down delay 10M */
705 #define B43_NPHY_TXREALFD B43_PHY_N(0x20D) /* TX real frame delay */
711 #define B43_NPHY_STR_WTIME20U B43_PHY_N(0x214) /* STR wait time 20U */
712 #define B43_NPHY_STR_WTIME20L B43_PHY_N(0x215) /* STR wait time 20L */