Lines Matching refs:B43_PHY_OFDM
9 #define B43_PHY_VERSION_OFDM B43_PHY_OFDM(0x00) /* Versioning register for A-PHY */
10 #define B43_PHY_BBANDCFG B43_PHY_OFDM(0x01) /* Baseband config */
13 #define B43_PHY_PWRDOWN B43_PHY_OFDM(0x03) /* Powerdown */
14 #define B43_PHY_CRSTHRES1_R1 B43_PHY_OFDM(0x06) /* CRS Threshold 1 (phy.rev 1 only) */
15 #define B43_PHY_LNAHPFCTL B43_PHY_OFDM(0x1C) /* LNA/HPF control */
16 #define B43_PHY_LPFGAINCTL B43_PHY_OFDM(0x20) /* LPF Gain control */
17 #define B43_PHY_ADIVRELATED B43_PHY_OFDM(0x27) /* FIXME rename */
18 #define B43_PHY_CRS0 B43_PHY_OFDM(0x29)
20 #define B43_PHY_PEAK_COUNT B43_PHY_OFDM(0x30)
21 #define B43_PHY_ANTDWELL B43_PHY_OFDM(0x2B) /* Antenna dwell */
23 #define B43_PHY_ENCORE B43_PHY_OFDM(0x49) /* "Encore" (RangeMax / BroadRange) */
25 #define B43_PHY_LMS B43_PHY_OFDM(0x55)
26 #define B43_PHY_OFDM61 B43_PHY_OFDM(0x61) /* FIXME rename */
28 #define B43_PHY_IQBAL B43_PHY_OFDM(0x69) /* I/Q balance */
29 #define B43_PHY_BBTXDC_BIAS B43_PHY_OFDM(0x6B) /* Baseband TX DC bias */
30 #define B43_PHY_OTABLECTL B43_PHY_OFDM(0x72) /* OFDM table control (see below) */
34 #define B43_PHY_OTABLEI B43_PHY_OFDM(0x73) /* OFDM table data I */
35 #define B43_PHY_OTABLEQ B43_PHY_OFDM(0x74) /* OFDM table data Q */
36 #define B43_PHY_HPWR_TSSICTL B43_PHY_OFDM(0x78) /* Hardware power TSSI control */
37 #define B43_PHY_ADCCTL B43_PHY_OFDM(0x7A) /* ADC control */
38 #define B43_PHY_IDLE_TSSI B43_PHY_OFDM(0x7B)
39 #define B43_PHY_A_TEMP_SENSE B43_PHY_OFDM(0x7C) /* A PHY temperature sense */
40 #define B43_PHY_NRSSITHRES B43_PHY_OFDM(0x8A) /* NRSSI threshold */
41 #define B43_PHY_ANTWRSETT B43_PHY_OFDM(0x8C) /* Antenna WR settle */
43 #define B43_PHY_CLIPPWRDOWNT B43_PHY_OFDM(0x93) /* Clip powerdown threshold */
44 #define B43_PHY_OFDM9B B43_PHY_OFDM(0x9B) /* FIXME rename */
45 #define B43_PHY_N1P1GAIN B43_PHY_OFDM(0xA0)
46 #define B43_PHY_P1P2GAIN B43_PHY_OFDM(0xA1)
47 #define B43_PHY_N1N2GAIN B43_PHY_OFDM(0xA2)
48 #define B43_PHY_CLIPTHRES B43_PHY_OFDM(0xA3)
49 #define B43_PHY_CLIPN1P2THRES B43_PHY_OFDM(0xA4)
50 #define B43_PHY_CCKSHIFTBITS_WA B43_PHY_OFDM(0xA5) /* CCK shiftbits workaround, FIXME rename */
51 #define B43_PHY_CCKSHIFTBITS B43_PHY_OFDM(0xA7) /* FIXME rename */
52 #define B43_PHY_DIVSRCHIDX B43_PHY_OFDM(0xA8) /* Divider search gain/index */
53 #define B43_PHY_CLIPP2THRES B43_PHY_OFDM(0xA9)
54 #define B43_PHY_CLIPP3THRES B43_PHY_OFDM(0xAA)
55 #define B43_PHY_DIVP1P2GAIN B43_PHY_OFDM(0xAB)
56 #define B43_PHY_DIVSRCHGAINBACK B43_PHY_OFDM(0xAD) /* Divider search gain back */
57 #define B43_PHY_DIVSRCHGAINCHNG B43_PHY_OFDM(0xAE) /* Divider search gain change */
58 #define B43_PHY_CRSTHRES1 B43_PHY_OFDM(0xC0) /* CRS Threshold 1 (phy.rev >= 2 only) */
59 #define B43_PHY_CRSTHRES2 B43_PHY_OFDM(0xC1) /* CRS Threshold 2 (phy.rev >= 2 only) */
60 #define B43_PHY_TSSIP_LTBASE B43_PHY_OFDM(0x380) /* TSSI power lookup table base */
61 #define B43_PHY_DC_LTBASE B43_PHY_OFDM(0x3A0) /* DC lookup table base */
62 #define B43_PHY_GAIN_LTBASE B43_PHY_OFDM(0x3C0) /* Gain lookup table base */