broadcom/b43/dma.h

1 /* SPDX-License-Identifier: GPL-2.0 */
10 /* DMA-Interrupt reasons. */
16 /*** 32-bit DMA Engine. ***/
18 /* 32-bit DMA controller registers. */
69 /* 32-bit DMA descriptor. */
82 /*** 64-bit DMA Engine. ***/
84 /* 64-bit DMA controller registers. */
142 /* 64-bit DMA descriptor. */
178 #define B43_DMA_PTR_POISON		((void *)ERR_PTR(-ENOMEM))
187 	/* The kernel DMA-able buffer. */
189 	/* DMA base bus-address of the descriptor buffer. */
191 	/* ieee80211 TX status. Only used once per 802.11 frag. */
233 	/* Cache of TX headers for each TX frame.
234 	 * This is to avoid an allocation on each TX.
238 	/* (Unadjusted) DMA base bus-address of the ring memory. */
240 	/* Number of descriptor slots in the ring. */
242 	/* Number of used descriptor slots. */
252 	/* DMA controller index number (0-5). */
254 	/* Boolean. Is this a TX ring? */
255 	bool tx;  member
260 	/* The QOS priority assigned to this ring. Only used for TX rings.
265 	/* Maximum number of used slots. */
271 	/* Statistics: Number of failed TX packets */
273 	/* Statistics: Total number of TX plus all retries. */
280 	return b43_read32(ring->dev, ring->mmio_base + offset);  in b43_dma_read()
285 	b43_write32(ring->dev, ring->mmio_base + offset, value);  in b43_dma_write()