Lines Matching +full:1 +full:- +full:bit

1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2012-2016 Qualcomm Atheros, Inc.
4 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
13 #define BUF_SW_OWNED (1)
26 return le32_to_cpu(addr->addr_low) | in wil_desc_addr()
27 ((u64)le16_to_cpu(addr->addr_high) << 32); in wil_desc_addr()
33 addr->addr_low = cpu_to_le32(lower_32_bits(pa)); in wil_desc_addr_set()
34 addr->addr_high = cpu_to_le16((u16)upper_32_bits(pa)); in wil_desc_addr_set()
37 /* Tx descriptor - MAC part
39 * bit 0.. 9 : lifetime_expiry_value:10
40 * bit 10 : interrupt_en:1
41 * bit 11 : status_en:1
42 * bit 12..13 : txss_override:2
43 * bit 14 : timestamp_insertion:1
44 * bit 15 : duration_preserve:1
45 * bit 16..21 : reserved0:6
46 * bit 22..26 : mcs_index:5
47 * bit 27 : mcs_en:1
48 * bit 28..30 : reserved1:3
49 * bit 31 : sn_preserved:1
50 * [dword 1]
51 * bit 0.. 3 : pkt_mode:4
52 * bit 4 : pkt_mode_en:1
53 * bit 5 : mac_id_en:1
54 * bit 6..7 : mac_id:2
55 * bit 8..14 : reserved0:7
56 * bit 15 : ack_policy_en:1
57 * bit 16..19 : dst_index:4
58 * bit 20 : dst_index_en:1
59 * bit 21..22 : ack_policy:2
60 * bit 23 : lifetime_en:1
61 * bit 24..30 : max_retry:7
62 * bit 31 : max_retry_en:1
64 * bit 0.. 7 : num_of_descriptors:8
65 * bit 8..17 : reserved:10
66 * bit 18..19 : l2_translation_type:2 00 - bypass, 01 - 802.3, 10 - 802.11
67 * bit 20 : snap_hdr_insertion_en:1
68 * bit 21 : vlan_removal_en:1
69 * bit 22..31 : reserved0:10
71 * bit 0.. 31: ucode_cmd:32
84 #define MAC_CFG_DESC_TX_0_INTERRUP_EN_LEN 1
88 #define MAC_CFG_DESC_TX_0_STATUS_EN_LEN 1
96 #define MAC_CFG_DESC_TX_0_TIMESTAMP_INSERTION_LEN 1
100 #define MAC_CFG_DESC_TX_0_DURATION_PRESERVE_LEN 1
108 #define MAC_CFG_DESC_TX_0_MCS_EN_LEN 1
112 #define MAC_CFG_DESC_TX_0_SN_PRESERVED_LEN 1
115 /* TX MAC Dword 1 */
121 #define MAC_CFG_DESC_TX_1_PKT_MODE_EN_LEN 1
125 #define MAC_CFG_DESC_TX_1_MAC_ID_EN_LEN 1
133 #define MAC_CFG_DESC_TX_1_ACK_POLICY_EN_LEN 1
141 #define MAC_CFG_DESC_TX_1_DST_INDEX_EN_LEN 1
149 #define MAC_CFG_DESC_TX_1_LIFETIME_EN_LEN 1
157 #define MAC_CFG_DESC_TX_1_MAX_RETRY_EN_LEN 1
174 #define MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_LEN 1
178 #define MAC_CFG_DESC_TX_2_VLAN_REMOVAL_EN_LEN 1
192 #define DMA_CFG_DESC_TX_0_CMD_EOP_LEN 1
196 #define DMA_CFG_DESC_TX_0_CMD_MARK_WB_LEN 1
200 #define DMA_CFG_DESC_TX_0_CMD_DMA_IT_LEN 1
208 #define DMA_CFG_DESC_TX_0_TCP_SEG_EN_LEN 1
212 #define DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_LEN 1
216 #define DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_LEN 1
224 #define DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_LEN 1
229 #define DMA_CFG_DESC_TX_0_L4_TYPE_MSK 0xC0000000 /* L4 type: 0-UDP, 2-TCP */
236 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_LEN 1
237 #define DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_MSK 0x80 /* 1-IPv4, 0-IPv6 */
239 #define TX_DMA_STATUS_DU BIT(0)
241 /* Tx descriptor - DMA part
243 * bit 0.. 7 : l4_length:8 layer 4 length
244 * bit 8 : cmd_eop:1 This descriptor is the last one in the packet
245 * bit 9 : reserved
246 * bit 10 : cmd_dma_it:1 immediate interrupt
247 * bit 11..12 : SBD - Segment Buffer Details
248 * 00 - Header Segment
249 * 01 - First Data Segment
250 * 10 - Medium Data Segment
251 * 11 - Last Data Segment
252 * bit 13 : TSE - TCP Segmentation Enable
253 * bit 14 : IIC - Directs the HW to Insert IPv4 Checksum
254 * bit 15 : ITC - Directs the HW to Insert TCP/UDP Checksum
255 * bit 16..20 : QID - The target QID that the packet should be stored
257 * bit 21 : PO - Pseudo header Offload:
258 * 0 - Use the pseudo header value from the TCP checksum field
259 * 1- Calculate Pseudo header Checksum
260 * bit 22 : NC - No UDP Checksum
261 * bit 23..29 : reserved
262 * bit 30..31 : L4T - Layer 4 Type: 00 - UDP , 10 - TCP , 10, 11 - Reserved
264 * [dword 1]
265 * bit 0..31 : addr_low:32 The payload buffer low address
267 * bit 0..15 : addr_high:16 The payload buffer high address
268 * bit 16..23 : ip_length:8 The IP header length for the TX IP checksum
270 * bit 24..30 : mac_length:7
271 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6
274 * bit 0 2 : mac_status:3
275 * bit 3 7 : reserved:5
277 * bit 0 : DU:1 Descriptor Used
278 * bit 1 7 : reserved:7
287 u8 status; /* 0: used; 1..7; reserved */
291 /* TSO type used in dma descriptor d0 bits 11-12 */
294 wil_tso_type_first = 1,
299 /* Rx descriptor - MAC part
301 * bit 0.. 3 : tid:4 The QoS (b3-0) TID Field
302 * bit 4.. 6 : cid:3 The Source index that was found during parsing the TA.
304 * bit 7 : MAC_id_valid:1, 1 if MAC virtual number is valid.
305 * bit 8.. 9 : mid:2 The MAC virtual number
306 * bit 10..11 : frame_type:2 : The FC (b3-2) - MPDU Type
308 * bit 12..15 : frame_subtype:4 : The FC (b7-4) - Frame Subtype
309 * bit 16..27 : seq_number:12 The received Sequence number field
310 * bit 28..31 : extended:4 extended subtype
311 * [dword 1]
312 * bit 0.. 3 : reserved
313 * bit 4.. 5 : key_id:2
314 * bit 6 : decrypt_bypass:1
315 * bit 7 : security:1 FC (b14)
316 * bit 8.. 9 : ds_bits:2 FC (b9-8)
317 * bit 10 : a_msdu_present:1 QoS (b7)
318 * bit 11 : a_msdu_type:1 QoS (b8)
319 * bit 12 : a_mpdu:1 part of AMPDU aggregation
320 * bit 13 : broadcast:1
321 * bit 14 : mutlicast:1
322 * bit 15 : reserved:1
323 * bit 16..20 : rx_mac_qid:5 The Queue Identifier that the packet
325 * bit 21..24 : mcs:4
326 * bit 25..28 : mic_icr:4 this signal tells the DMA to assert an interrupt
328 * bit 29..31 : reserved:3
330 * bit 0.. 2 : time_slot:3 The timeslot that the MPDU is received
331 * bit 3.. 4 : fc_protocol_ver:1 The FC (b1-0) - Protocol Version
332 * bit 5 : fc_order:1 The FC Control (b15) -Order
333 * bit 6.. 7 : qos_ack_policy:2 The QoS (b6-5) ack policy Field
334 * bit 8 : esop:1 The QoS (b4) ESOP field
335 * bit 9 : qos_rdg_more_ppdu:1 The QoS (b9) RDG field
336 * bit 10..14 : qos_reserved:5 The QoS (b14-10) Reserved field
337 * bit 15 : qos_ac_constraint:1 QoS (b15)
338 * bit 16..31 : pn_15_0:16 low 2 bytes of PN
340 * bit 0..31 : pn_47_16:32 high 4 bytes of PN
352 /* Rx descriptor - DMA part
354 * bit 0.. 7 : l4_length:8 layer 4 length. The field is only valid if
355 * L4I bit is set
356 * bit 8 : cmd_eop:1 set to 1
357 * bit 9 : cmd_rt:1 set to 1
358 * bit 10 : cmd_dma_it:1 immediate interrupt
359 * bit 11..15 : reserved:5
360 * bit 16..29 : phy_info_length:14 It is valid when the PII is set.
361 * When the FFM bit is set bits 29-27 are used for
364 * bit 30..31 : l4_type:2 valid if the L4I bit is set in the status field
365 * 00 - UDP, 01 - TCP, 10, 11 - reserved
366 * [dword 1]
367 * bit 0..31 : addr_low:32 The payload buffer low address
369 * bit 0..15 : addr_high:16 The payload buffer high address
370 * bit 16..23 : ip_length:8 The filed is valid only if the L3I bit is set
371 * bit 24..30 : mac_length:7
372 * bit 31 : ip_version:1 1 - IPv4, 0 - IPv6
375 * bit 0 : FCS:1
376 * bit 1 : MIC:1
377 * bit 2 : Key miss:1
378 * bit 3 : Replay:1
379 * bit 4 : L3:1 IPv4 checksum
380 * bit 5 : L4:1 TCP/UDP checksum
381 * bit 6 7 : reserved:2
383 * bit 0 : DU:1 Descriptor Used
384 * bit 1 : EOP:1 The descriptor indicates the End of Packet
385 * bit 2 : error:1
386 * bit 3 : MI:1 MAC Interrupt is asserted (according to parser decision)
387 * bit 4 : L3I:1 L3 identified and checksum calculated
388 * bit 5 : L4I:1 L4 identified and checksum calculated
389 * bit 6 : PII:1 PHY Info Included in the packet
390 * bit 7 : FFM:1 EtherType Flex Filter Match
394 #define RX_DMA_D0_CMD_DMA_EOP BIT(8)
395 #define RX_DMA_D0_CMD_DMA_RT BIT(9) /* always 1 */
396 #define RX_DMA_D0_CMD_DMA_IT BIT(10) /* interrupt */
397 #define RX_MAC_D0_MAC_ID_VALID BIT(7)
400 #define RX_DMA_ERROR_FCS BIT(0)
401 #define RX_DMA_ERROR_MIC BIT(1)
402 #define RX_DMA_ERROR_KEY BIT(2) /* Key missing */
403 #define RX_DMA_ERROR_REPLAY BIT(3)
404 #define RX_DMA_ERROR_L3_ERR BIT(4)
405 #define RX_DMA_ERROR_L4_ERR BIT(5)
408 #define RX_DMA_STATUS_DU BIT(0)
409 #define RX_DMA_STATUS_EOP BIT(1)
410 #define RX_DMA_STATUS_ERROR BIT(2)
411 #define RX_DMA_STATUS_MI BIT(3) /* MAC Interrupt is asserted */
412 #define RX_DMA_STATUS_L3I BIT(4)
413 #define RX_DMA_STATUS_L4I BIT(5)
414 #define RX_DMA_STATUS_PHY_INFO BIT(6)
415 #define RX_DMA_STATUS_FFM BIT(7) /* EtherType Flex Filter Match */
417 /* IEEE 802.11, 8.5.2 EAPOL-Key frames */
418 #define WIL_KEY_INFO_KEY_TYPE BIT(3) /* val of 1 = Pairwise, 0 = Group key */
420 #define WIL_KEY_INFO_MIC BIT(8)
421 #define WIL_KEY_INFO_ENCR_KEY_DATA BIT(12) /* for rsn only */
431 WIL_1X_TYPE_EAPOL_START = 1,
506 return WIL_GET_BITS(d->mac.d0, 0, 3); in wil_rxdesc_tid()
511 return WIL_GET_BITS(d->mac.d0, 4, 6); in wil_rxdesc_cid()
516 return (d->mac.d0 & RX_MAC_D0_MAC_ID_VALID) ? in wil_rxdesc_mid()
517 WIL_GET_BITS(d->mac.d0, 8, 9) : 0; in wil_rxdesc_mid()
522 return WIL_GET_BITS(d->mac.d0, 10, 11); in wil_rxdesc_ftype()
527 return WIL_GET_BITS(d->mac.d0, 12, 15); in wil_rxdesc_subtype()
530 /* 1-st byte (with frame type/subtype) of FC field */
533 return (u8)(WIL_GET_BITS(d->mac.d0, 10, 15) << 2); in wil_rxdesc_fc1()
538 return WIL_GET_BITS(d->mac.d0, 16, 27); in wil_rxdesc_seq()
543 return WIL_GET_BITS(d->mac.d0, 28, 31); in wil_rxdesc_ext_subtype()
548 return WIL_GET_BITS(d->mac.d0, 31, 31); in wil_rxdesc_retry()
553 return WIL_GET_BITS(d->mac.d1, 4, 5); in wil_rxdesc_key_id()
558 return WIL_GET_BITS(d->mac.d1, 7, 7); in wil_rxdesc_security()
563 return WIL_GET_BITS(d->mac.d1, 8, 9); in wil_rxdesc_ds_bits()
568 return WIL_GET_BITS(d->mac.d1, 21, 24); in wil_rxdesc_mcs()
573 return WIL_GET_BITS(d->mac.d1, 13, 14); in wil_rxdesc_mcast()
578 return (void *)skb->cb; in wil_skb_rxdesc()
583 return ring->swhead == ring->swtail; in wil_ring_is_empty()
588 return (ring->swtail + 1) % ring->size; in wil_ring_next_tail()
593 ring->swhead = (ring->swhead + n) % ring->size; in wil_ring_advance_head()
598 return wil_ring_next_tail(ring) == ring->swhead; in wil_ring_is_full()
603 struct ethhdr *eth = (void *)skb->data; in wil_skb_get_da()
605 return eth->h_dest; in wil_skb_get_da()
610 struct ethhdr *eth = (void *)skb->data; in wil_skb_get_sa()
612 return eth->h_source; in wil_skb_get_sa()
619 return is_unicast_ether_addr(da) && skb->sk && in wil_need_txstat()
620 (skb_shinfo(skb)->tx_flags & SKBTX_WIFI_STATUS); in wil_need_txstat()
634 u32 swhead = ring->swhead; in wil_ring_used_tx()
635 u32 swtail = ring->swtail; in wil_ring_used_tx()
637 return (ring->size + swhead - swtail) % ring->size; in wil_ring_used_tx()
643 return ring->size - wil_ring_used_tx(ring) - 1; in wil_ring_avail_tx()
649 return wil->use_enhanced_dma_hw ? 1 : 0; in wil_get_min_tx_ring_id()
652 /* similar to ieee80211_ version, but FC contain only 1-st byte */
659 /* wil_val_in_range - check if value in [min,max) */
667 struct skb_rx_info *skb_rx_info = (void *)skb->cb; in wil_skb_get_cid()
669 return skb_rx_info->rx_info.cid; in wil_skb_get_cid()
674 struct skb_rx_info *skb_rx_info = (void *)skb->cb; in wil_skb_set_cid()
676 skb_rx_info->rx_info.cid = cid; in wil_skb_set_cid()