Lines Matching full:u8
109 #define FREQ2FBIN(x, y) (u8)((y) ? ((x) - 2300) : (((x) - 4800) / 5))
287 u8 opCapFlags;
288 u8 eepMisc;
290 u8 macAddr[6];
291 u8 rxMask;
292 u8 txMask;
297 u8 deviceType;
298 u8 pwdclkind;
299 u8 fastClk5g;
300 u8 divChain;
301 u8 rxGainType;
302 u8 dacHiPwrMode_5G;
303 u8 openLoopPwrCntl;
304 u8 dacLpMode;
305 u8 txGainType;
306 u8 rcChainMask;
307 u8 desiredScaleCCK;
308 u8 pwr_table_offset;
309 u8 frac_n_5g;
310 u8 futureBase_3[21];
317 u8 opCapFlags;
318 u8 eepMisc;
320 u8 macAddr[6];
321 u8 rxMask;
322 u8 txMask;
327 u8 deviceType;
328 u8 txGainType;
334 u8 spurRangeLow;
335 u8 spurRangeHigh;
341 u8 antennaGainCh[AR5416_MAX_CHAINS];
342 u8 switchSettling;
343 u8 txRxAttenCh[AR5416_MAX_CHAINS];
344 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
345 u8 adcDesiredSize;
346 u8 pgaDesiredSize;
347 u8 xlnaGainCh[AR5416_MAX_CHAINS];
348 u8 txEndToXpaOff;
349 u8 txEndToRxOn;
350 u8 txFrameToXpaOn;
351 u8 thresh62;
352 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
353 u8 xpdGain;
354 u8 xpd;
355 u8 iqCalICh[AR5416_MAX_CHAINS];
356 u8 iqCalQCh[AR5416_MAX_CHAINS];
357 u8 pdGainOverlap;
358 u8 ob;
359 u8 db;
360 u8 xpaBiasLvl;
361 u8 pwrDecreaseFor2Chain;
362 u8 pwrDecreaseFor3Chain;
363 u8 txFrameToDataStart;
364 u8 txFrameToPaOn;
365 u8 ht40PowerIncForPdadc;
366 u8 bswAtten[AR5416_MAX_CHAINS];
367 u8 bswMargin[AR5416_MAX_CHAINS];
368 u8 swSettleHt40;
369 u8 xatten2Db[AR5416_MAX_CHAINS];
370 u8 xatten2Margin[AR5416_MAX_CHAINS];
371 u8 ob_ch1;
372 u8 db_ch1;
373 u8 lna_ctl;
374 u8 miscBits;
376 u8 futureModal[6];
382 u8 pwrPdg[2][5];
383 u8 vpdPdg[2][5];
384 u8 pcdac[2][5];
385 u8 empty[2][5];
391 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
392 u8 switchSettling;
393 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
394 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
395 u8 adcDesiredSize;
396 u8 pgaDesiredSize;
397 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
398 u8 txEndToXpaOff;
399 u8 txEndToRxOn;
400 u8 txFrameToXpaOn;
401 u8 thresh62;
402 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
403 u8 xpdGain;
404 u8 xpd;
405 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
406 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
407 u8 pdGainOverlap;
409 u8 ob_1:4, ob_0:4;
410 u8 db1_1:4, db1_0:4;
412 u8 ob_0:4, ob_1:4;
413 u8 db1_0:4, db1_1:4;
415 u8 xpaBiasLvl;
416 u8 txFrameToDataStart;
417 u8 txFrameToPaOn;
418 u8 ht40PowerIncForPdadc;
419 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
420 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
421 u8 swSettleHt40;
422 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
423 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
425 u8 db2_1:4, db2_0:4;
427 u8 db2_0:4, db2_1:4;
429 u8 version;
431 u8 ob_3:4, ob_2:4;
432 u8 antdiv_ctl1:4, ob_4:4;
433 u8 db1_3:4, db1_2:4;
434 u8 antdiv_ctl2:4, db1_4:4;
435 u8 db2_2:4, db2_3:4;
436 u8 reserved:4, db2_4:4;
438 u8 ob_2:4, ob_3:4;
439 u8 ob_4:4, antdiv_ctl1:4;
440 u8 db1_2:4, db1_3:4;
441 u8 db1_4:4, antdiv_ctl2:4;
442 u8 db2_2:4, db2_3:4;
443 u8 db2_4:4, reserved:4;
445 u8 tx_diversity;
446 u8 flc_pwr_thresh;
447 u8 bb_scale_smrt_antenna;
449 u8 futureModal[1];
457 u8 opCapFlags;
458 u8 eepMisc;
460 u8 macAddr[6];
461 u8 rxMask;
462 u8 txMask;
467 u8 deviceType;
468 u8 openLoopPwrCntl;
472 u8 futureBase[29];
479 u8 switchSettling;
480 u8 txRxAttenCh[AR9287_MAX_CHAINS];
481 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
483 u8 txEndToXpaOff;
484 u8 txEndToRxOn;
485 u8 txFrameToXpaOn;
486 u8 thresh62;
488 u8 xpdGain;
489 u8 xpd;
492 u8 pdGainOverlap;
493 u8 xpaBiasLvl;
494 u8 txFrameToDataStart;
495 u8 txFrameToPaOn;
496 u8 ht40PowerIncForPdadc;
497 u8 bswAtten[AR9287_MAX_CHAINS];
498 u8 bswMargin[AR9287_MAX_CHAINS];
499 u8 swSettleHt40;
500 u8 version;
501 u8 db1;
502 u8 db2;
503 u8 ob_cck;
504 u8 ob_psk;
505 u8 ob_qam;
506 u8 ob_pal_off;
507 u8 futureModal[30];
512 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
513 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
517 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
518 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
522 u8 bChannel;
523 u8 tPow2x[4];
527 u8 bChannel;
528 u8 tPow2x[8];
532 u8 bChannel;
533 u8 ctl;
537 u8 pwrPdg[2][5];
538 u8 vpdPdg[2][5];
539 u8 pcdac[2][5];
540 u8 empty[2][5];
544 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
545 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
570 u8 custData[64];
572 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
573 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
592 u8 ctlIndex[AR5416_NUM_CTLS];
594 u8 padding;
599 u8 custData[20];
601 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
612 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
614 u8 padding;
619 u8 custData[AR9287_DATA_SZ];
621 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
632 u8 ctlIndex[AR9287_NUM_CTLS];
634 u8 padding;
650 u8 isMultidomain;
651 u8 iso[3];
658 u32 (*dump_eeprom)(struct ath_hw *hw, bool dump_base_hdr, u8 *buf,
665 u16 cfgCtl, u8 twiceAntennaReduction,
666 u8 powerLimit, bool test);
668 u8 (*get_eepmisc)(struct ath_hw *ah);
677 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
685 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
686 u8 *pVpdList, u16 numIntercepts,
687 u8 *pRetVpdList);
703 u8 antenna_reduction);
710 u8 *bChans, u16 availPiers,
712 u16 *pPdGainBoundaries, u8 *pPDADCValues,
715 static inline u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz) in ath9k_hw_fbin2freq()