Lines Matching +full:0 +full:x0ffe0000
23 #define AR_CHAN_BASE 0x9800
25 #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0)
26 #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4)
27 #define AR_PHY_TIMING3 (AR_CHAN_BASE + 0x8)
28 #define AR_PHY_TIMING4 (AR_CHAN_BASE + 0xc)
29 #define AR_PHY_TIMING5 (AR_CHAN_BASE + 0x10)
30 #define AR_PHY_TIMING6 (AR_CHAN_BASE + 0x14)
31 #define AR_PHY_TIMING11 (AR_CHAN_BASE + 0x18)
32 #define AR_PHY_SPUR_REG (AR_CHAN_BASE + 0x1c)
33 #define AR_PHY_RX_IQCAL_CORR_B0 (AR_CHAN_BASE + 0xdc)
34 #define AR_PHY_TX_IQCAL_CONTROL_3 (AR_CHAN_BASE + 0xb0)
37 #define AR_PHY_TIMING11_SPUR_FREQ_SD 0x3FF00000
40 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE 0x000FFFFF
41 #define AR_PHY_TIMING11_SPUR_DELTA_PHASE_S 0
43 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC 0x40000000
46 #define AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR 0x80000000
49 #define AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT 0x4000000
52 #define AR_PHY_SPUR_REG_ENABLE_MASK_PPM 0x20000 /* bins move with freq …
54 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH 0x000000FF
55 #define AR_PHY_SPUR_REG_SPUR_RSSI_THRESH_S 0
56 #define AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI 0x00000100
58 #define AR_PHY_SPUR_REG_MASK_RATE_CNTL 0x03FC0000
61 #define AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN 0x20000000
64 #define AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN 0x80000000
67 #define AR_PHY_FIND_SIG_LOW (AR_CHAN_BASE + 0x20)
69 #define AR_PHY_SFCORR (AR_CHAN_BASE + 0x24)
70 #define AR_PHY_SFCORR_LOW (AR_CHAN_BASE + 0x28)
71 #define AR_PHY_SFCORR_EXT (AR_CHAN_BASE + 0x2c)
73 #define AR_PHY_EXT_CCA (AR_CHAN_BASE + 0x30)
74 #define AR_PHY_RADAR_0 (AR_CHAN_BASE + 0x34)
75 #define AR_PHY_RADAR_1 (AR_CHAN_BASE + 0x38)
76 #define AR_PHY_RADAR_EXT (AR_CHAN_BASE + 0x3c)
77 #define AR_PHY_MULTICHAIN_CTRL (AR_CHAN_BASE + 0x80)
78 #define AR_PHY_PERCHAIN_CSD (AR_CHAN_BASE + 0x84)
80 #define AR_PHY_TX_PHASE_RAMP_0 (AR_CHAN_BASE + 0xd0)
81 #define AR_PHY_ADC_GAIN_DC_CORR_0 (AR_CHAN_BASE + 0xd4)
82 #define AR_PHY_IQ_ADC_MEAS_0_B0 (AR_CHAN_BASE + 0xc0)
83 #define AR_PHY_IQ_ADC_MEAS_1_B0 (AR_CHAN_BASE + 0xc4)
84 #define AR_PHY_IQ_ADC_MEAS_2_B0 (AR_CHAN_BASE + 0xc8)
85 #define AR_PHY_IQ_ADC_MEAS_3_B0 (AR_CHAN_BASE + 0xcc)
88 #define AR_PHY_TX_PHASE_RAMP_0_9300_10 (AR_CHAN_BASE + 0xd0 - 0x10)
89 #define AR_PHY_ADC_GAIN_DC_CORR_0_9300_10 (AR_CHAN_BASE + 0xd4 - 0x10)
90 #define AR_PHY_IQ_ADC_MEAS_0_B0_9300_10 (AR_CHAN_BASE + 0xc0 + 0x8)
91 #define AR_PHY_IQ_ADC_MEAS_1_B0_9300_10 (AR_CHAN_BASE + 0xc4 + 0x8)
92 #define AR_PHY_IQ_ADC_MEAS_2_B0_9300_10 (AR_CHAN_BASE + 0xc8 + 0x8)
93 #define AR_PHY_IQ_ADC_MEAS_3_B0_9300_10 (AR_CHAN_BASE + 0xcc + 0x8)
95 #define AR_PHY_TX_CRC (AR_CHAN_BASE + 0xa0)
96 #define AR_PHY_TST_DAC_CONST (AR_CHAN_BASE + 0xa4)
97 #define AR_PHY_SPUR_REPORT_0 (AR_CHAN_BASE + 0xa8)
98 #define AR_PHY_CHAN_INFO_TAB_0 (AR_CHAN_BASE + 0x300)
103 #define AR_PHY_TIMING2_USE_FORCE_PPM 0x00001000
104 #define AR_PHY_TIMING2_FORCE_PPM_VAL 0x00000fff
105 #define AR_PHY_TIMING3_DSC_MAN 0xFFFE0000
107 #define AR_PHY_TIMING3_DSC_EXP 0x0001E000
109 #define AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX 0xF000
111 #define AR_PHY_TIMING4_DO_CAL 0x10000
113 #define AR_PHY_TIMING4_ENABLE_PILOT_MASK 0x10000000
115 #define AR_PHY_TIMING4_ENABLE_CHAN_MASK 0x20000000
118 #define AR_PHY_TIMING4_ENABLE_SPUR_FILTER 0x40000000
120 #define AR_PHY_TIMING4_ENABLE_SPUR_RSSI 0x80000000
123 #define AR_PHY_NEW_ADC_GAIN_CORR_ENABLE 0x40000000
124 #define AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE 0x80000000
125 #define AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW 0x00000001
126 #define AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW 0x00003F00
128 #define AR_PHY_SFCORR_LOW_M1_THRESH_LOW 0x001FC000
130 #define AR_PHY_SFCORR_LOW_M2_THRESH_LOW 0x0FE00000
132 #define AR_PHY_SFCORR_M2COUNT_THR 0x0000001F
133 #define AR_PHY_SFCORR_M2COUNT_THR_S 0
134 #define AR_PHY_SFCORR_M1_THRESH 0x00FE0000
136 #define AR_PHY_SFCORR_M2_THRESH 0x7F000000
138 #define AR_PHY_SFCORR_EXT_M1_THRESH 0x0000007F
139 #define AR_PHY_SFCORR_EXT_M1_THRESH_S 0
140 #define AR_PHY_SFCORR_EXT_M2_THRESH 0x00003F80
142 #define AR_PHY_SFCORR_EXT_M1_THRESH_LOW 0x001FC000
144 #define AR_PHY_SFCORR_EXT_M2_THRESH_LOW 0x0FE00000
146 #define AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD 0x10000000
149 #define AR_PHY_EXT_CCA_THRESH62 0x007F0000
151 #define AR_PHY_EXTCHN_PWRTHR1_ANT_DIV_ALT_ANT_MINGAINIDX 0x0000FF00
153 #define AR_PHY_EXT_MINCCA_PWR 0x01FF0000
155 #define AR_PHY_EXT_CYCPWR_THR1 0x0000FE00L
157 #define AR_PHY_TIMING5_CYCPWR_THR1 0x000000FE
159 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE 0x00000001
160 #define AR_PHY_TIMING5_CYCPWR_THR1_ENABLE_S 0
161 #define AR_PHY_TIMING5_CYCPWR_THR1A 0x007F0000
163 #define AR_PHY_TIMING5_RSSI_THR1A (0x7F << 16)
165 #define AR_PHY_TIMING5_RSSI_THR1A_ENA (0x1 << 15)
166 #define AR_PHY_RADAR_0_ENA 0x00000001
167 #define AR_PHY_RADAR_0_FFT_ENA 0x80000000
168 #define AR_PHY_RADAR_0_INBAND 0x0000003e
170 #define AR_PHY_RADAR_0_PRSSI 0x00000FC0
172 #define AR_PHY_RADAR_0_HEIGHT 0x0003F000
174 #define AR_PHY_RADAR_0_RRSSI 0x00FC0000
176 #define AR_PHY_RADAR_0_FIRPWR 0x7F000000
178 #define AR_PHY_RADAR_1_RELPWR_ENA 0x00800000
179 #define AR_PHY_RADAR_1_USE_FIR128 0x00400000
180 #define AR_PHY_RADAR_1_RELPWR_THRESH 0x003F0000
182 #define AR_PHY_RADAR_1_BLOCK_CHECK 0x00008000
183 #define AR_PHY_RADAR_1_MAX_RRSSI 0x00004000
184 #define AR_PHY_RADAR_1_RELSTEP_CHECK 0x00002000
185 #define AR_PHY_RADAR_1_RELSTEP_THRESH 0x00001F00
187 #define AR_PHY_RADAR_1_MAXLEN 0x000000FF
188 #define AR_PHY_RADAR_1_MAXLEN_S 0
189 #define AR_PHY_RADAR_EXT_ENA 0x00004000
190 #define AR_PHY_RADAR_DC_PWR_THRESH 0x007f8000
192 #define AR_PHY_RADAR_LB_DC_CAP 0x7f800000
194 #define AR_PHY_FIND_SIG_LOW_FIRSTEP_LOW (0x3f << 6)
196 #define AR_PHY_FIND_SIG_LOW_FIRPWR (0x7f << 12)
199 #define AR_PHY_FIND_SIG_LOW_RELSTEP 0x1f
200 #define AR_PHY_FIND_SIG_LOW_RELSTEP_S 0
202 #define AR_PHY_CHAN_INFO_TAB_S2_READ 0x00000008
204 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF 0x0000007F
205 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF_S 0
206 #define AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF 0x00003F80
208 #define AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE 0x00004000
209 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF 0x003f8000
211 #define AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF 0x1fc00000
217 #define AR_MRC_BASE 0x9c00
219 #define AR_PHY_TIMING_3A (AR_MRC_BASE + 0x0)
220 #define AR_PHY_LDPC_CNTL1 (AR_MRC_BASE + 0x4)
221 #define AR_PHY_LDPC_CNTL2 (AR_MRC_BASE + 0x8)
222 #define AR_PHY_PILOT_SPUR_MASK (AR_MRC_BASE + 0xc)
223 #define AR_PHY_CHAN_SPUR_MASK (AR_MRC_BASE + 0x10)
224 #define AR_PHY_SGI_DELTA (AR_MRC_BASE + 0x14)
225 #define AR_PHY_ML_CNTL_1 (AR_MRC_BASE + 0x18)
226 #define AR_PHY_ML_CNTL_2 (AR_MRC_BASE + 0x1c)
227 #define AR_PHY_TST_ADC (AR_MRC_BASE + 0x20)
229 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A 0x00000FE0
231 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A 0x1F
232 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A_S 0
233 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B 0x00FE0000
235 #define AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B 0x0001F000
238 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A 0x00000FE0
240 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A 0x1F
241 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A_S 0
242 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B 0x00FE0000
244 #define AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B 0x0001F000
251 #define AR_PHY_SGI_DSC_MAN 0x0007FFF0
253 #define AR_PHY_SGI_DSC_EXP 0x0000000F
254 #define AR_PHY_SGI_DSC_EXP_S 0
258 #define AR_BBB_BASE 0x9d00
263 #define AR_AGC_BASE 0x9e00
265 #define AR_PHY_SETTLING (AR_AGC_BASE + 0x0)
266 #define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4)
267 #define AR_PHY_GAINS_MINOFF0 (AR_AGC_BASE + 0x8)
268 #define AR_PHY_DESIRED_SZ (AR_AGC_BASE + 0xc)
269 #define AR_PHY_FIND_SIG (AR_AGC_BASE + 0x10)
270 #define AR_PHY_AGC (AR_AGC_BASE + 0x14)
271 #define AR_PHY_EXT_ATTEN_CTL_0 (AR_AGC_BASE + 0x18)
272 #define AR_PHY_CCA_0 (AR_AGC_BASE + 0x1c)
273 #define AR_PHY_CCA_CTRL_0 (AR_AGC_BASE + 0x20)
274 #define AR_PHY_RESTART (AR_AGC_BASE + 0x24)
279 #define AR_PHY_MC_GAIN_CTRL (AR_AGC_BASE + 0x28)
280 #define AR_ANT_DIV_CTRL_ALL 0x7e000000
282 #define AR_ANT_DIV_ENABLE 0x1000000
286 #define AR_PHY_ANT_FAST_DIV_BIAS 0x00007e00
288 #define AR_PHY_ANT_SW_RX_PROT 0x00800000
290 #define AR_PHY_ANT_DIV_LNADIV 0x01000000
292 #define AR_PHY_ANT_DIV_ALT_LNACONF 0x06000000
294 #define AR_PHY_ANT_DIV_MAIN_LNACONF 0x18000000
296 #define AR_PHY_ANT_DIV_ALT_GAINTB 0x20000000
298 #define AR_PHY_ANT_DIV_MAIN_GAINTB 0x40000000
301 #define AR_PHY_EXTCHN_PWRTHR1 (AR_AGC_BASE + 0x2c)
302 #define AR_PHY_EXT_CHN_WIN (AR_AGC_BASE + 0x30)
303 #define AR_PHY_20_40_DET_THR (AR_AGC_BASE + 0x34)
304 #define AR_PHY_RIFS_SRCH (AR_AGC_BASE + 0x38)
305 #define AR_PHY_PEAK_DET_CTRL_1 (AR_AGC_BASE + 0x3c)
306 #define AR_PHY_PEAK_DET_CTRL_2 (AR_AGC_BASE + 0x40)
307 #define AR_PHY_RX_GAIN_BOUNDS_1 (AR_AGC_BASE + 0x44)
308 #define AR_PHY_RX_GAIN_BOUNDS_2 (AR_AGC_BASE + 0x48)
309 #define AR_PHY_RSSI_0 (AR_AGC_BASE + 0x180)
310 #define AR_PHY_SPUR_CCK_REP0 (AR_AGC_BASE + 0x184)
312 #define AR_PHY_CCK_DETECT (AR_AGC_BASE + 0x1c0)
313 #define AR_FAST_DIV_ENABLE 0x2000
316 #define AR_PHY_DAG_CTRLCCK (AR_AGC_BASE + 0x1c4)
317 #define AR_PHY_IQCORR_CTRL_CCK (AR_AGC_BASE + 0x1c8)
319 #define AR_PHY_CCK_SPUR_MIT (AR_AGC_BASE + 0x1cc)
320 #define AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR 0x000001fe
322 #define AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE 0x60000000
324 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT 0x00000001
325 #define AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_S 0
326 #define AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ 0x1ffffe00
329 #define AR_PHY_MRC_CCK_CTRL (AR_AGC_BASE + 0x1d0)
330 #define AR_PHY_MRC_CCK_ENABLE 0x00000001
331 #define AR_PHY_MRC_CCK_ENABLE_S 0
332 #define AR_PHY_MRC_CCK_MUX_REG 0x00000002
335 #define AR_PHY_RX_OCGAIN (AR_AGC_BASE + 0x200)
360 #define AR_PHY_EXT_ATTEN_CTL_RXTX_MARGIN 0x00FC0000
362 #define AR_PHY_EXT_ATTEN_CTL_BSW_MARGIN 0x00003C00
364 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN 0x0000001F
365 #define AR_PHY_EXT_ATTEN_CTL_BSW_ATTEN_S 0
366 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_MARGIN 0x003E0000
368 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN 0x0001F000
370 #define AR_PHY_EXT_ATTEN_CTL_XATTEN2_DB 0x00000FC0
372 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB 0x0000003F
373 #define AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB_S 0
374 #define AR_PHY_RXGAIN_TXRX_ATTEN 0x0003F000
376 #define AR_PHY_RXGAIN_TXRX_RF_MAX 0x007C0000
378 #define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80
380 #define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000
382 #define AR_PHY_SETTLING_SWITCH 0x00003F80
384 #define AR_PHY_DESIRED_SZ_ADC 0x000000FF
385 #define AR_PHY_DESIRED_SZ_ADC_S 0
386 #define AR_PHY_DESIRED_SZ_PGA 0x0000FF00
388 #define AR_PHY_DESIRED_SZ_TOT_DES 0x0FF00000
390 #define AR_PHY_MINCCA_PWR 0x1FF00000
392 #define AR_PHY_CCA_THRESH62 0x0007F000
394 #define AR9280_PHY_MINCCA_PWR 0x1FF00000
396 #define AR9280_PHY_CCA_THRESH62 0x000FF000
398 #define AR_PHY_EXT_CCA0_THRESH62 0x000000FF
399 #define AR_PHY_EXT_CCA0_THRESH62_S 0
400 #define AR_PHY_EXT_CCA0_THRESH62_1 0x000001FF
401 #define AR_PHY_EXT_CCA0_THRESH62_1_S 0
402 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK 0x0000003F
403 #define AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S 0
404 #define AR_PHY_CCK_DETECT_ANT_SWITCH_TIME 0x00001FC0
406 #define AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV 0x2000
408 #define AR_PHY_DAG_CTRLCCK_EN_RSSI_THR 0x00000200
410 #define AR_PHY_DAG_CTRLCCK_RSSI_THR 0x0001FC00
413 #define AR_PHY_RIFS_INIT_DELAY 0x3ff0000
414 #define AR_PHY_AGC_QUICK_DROP 0x03c00000
416 #define AR_PHY_AGC_COARSE_LOW 0x00007F80
418 #define AR_PHY_AGC_COARSE_HIGH 0x003F8000
420 #define AR_PHY_AGC_COARSE_PWR_CONST 0x0000007F
421 #define AR_PHY_AGC_COARSE_PWR_CONST_S 0
422 #define AR_PHY_FIND_SIG_FIRSTEP 0x0003F000
424 #define AR_PHY_FIND_SIG_FIRPWR 0x03FC0000
427 #define AR_PHY_FIND_SIG_RELPWR (0x1f << 6)
430 #define AR_PHY_FIND_SIG_RELSTEP 0x1f
431 #define AR_PHY_FIND_SIG_RELSTEP_S 0
433 #define AR_PHY_RESTART_ENABLE_DIV_M2FLAG 0x00200000
435 #define AR_PHY_RESTART_DIV_GC 0x001C0000
437 #define AR_PHY_RESTART_ENA 0x01
438 #define AR_PHY_DC_RESTART_DIS 0x40000000
440 #define AR_PHY_TPC_OLPC_GAIN_DELTA_PAL_ON 0xFF000000
442 #define AR_PHY_TPC_OLPC_GAIN_DELTA 0x00FF0000
445 #define AR_PHY_TPC_6_ERROR_EST_MODE 0x03000000
451 #define AR_SM_BASE 0xa200
453 #define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0)
454 #define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4)
455 #define AR_PHY_MODE (AR_SM_BASE + 0x8)
456 #define AR_PHY_ACTIVE (AR_SM_BASE + 0xc)
457 #define AR_PHY_SPUR_MASK_A(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x18 : 0x20))
458 #define AR_PHY_SPUR_MASK_B(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x1c : 0x24))
459 #define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28)
460 #define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c)
461 #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30)
462 #define AR_PHY_MAX_RX_LEN (AR_SM_BASE + 0x34)
463 #define AR_PHY_FRAME_CTL (AR_SM_BASE + 0x38)
464 #define AR_PHY_RFBUS_REQ (AR_SM_BASE + 0x3c)
465 #define AR_PHY_RFBUS_GRANT (AR_SM_BASE + 0x40)
466 #define AR_PHY_RIFS (AR_SM_BASE + 0x44)
467 #define AR_PHY_RX_CLR_DELAY (AR_SM_BASE + 0x50)
468 #define AR_PHY_RX_DELAY (AR_SM_BASE + 0x54)
470 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
471 #define AR_PHY_MISC_PA_CTL (AR_SM_BASE + 0x80)
472 #define AR_PHY_SWITCH_CHAIN_0 (AR_SM_BASE + 0x84)
473 #define AR_PHY_SWITCH_COM (AR_SM_BASE + 0x88)
474 #define AR_PHY_SWITCH_COM_2 (AR_SM_BASE + 0x8c)
475 #define AR_PHY_RX_CHAINMASK (AR_SM_BASE + 0xa0)
476 #define AR_PHY_CAL_CHAINMASK (AR_SM_BASE + 0xc0)
477 #define AR_PHY_CALMODE (AR_SM_BASE + 0xc8)
478 #define AR_PHY_FCAL_1 (AR_SM_BASE + 0xcc)
479 #define AR_PHY_FCAL_2_0 (AR_SM_BASE + 0xd0)
480 #define AR_PHY_DFT_TONE_CTL_0 (AR_SM_BASE + 0xd4)
481 #define AR_PHY_CL_CAL_CTL (AR_SM_BASE + 0xd8)
482 #define AR_PHY_CL_TAB_0 (AR_SM_BASE + 0x100)
483 #define AR_PHY_SYNTH_CONTROL (AR_SM_BASE + 0x140)
484 #define AR_PHY_ADDAC_CLK_SEL (AR_SM_BASE + 0x144)
485 #define AR_PHY_PLL_CTL (AR_SM_BASE + 0x148)
486 #define AR_PHY_ANALOG_SWAP (AR_SM_BASE + 0x14c)
487 #define AR_PHY_ADDAC_PARA_CTL (AR_SM_BASE + 0x150)
488 #define AR_PHY_XPA_CFG (AR_SM_BASE + 0x158)
491 #define AR_PHY_FLC_PWR_THRESH_S 0
494 #define AR_PHY_FRAME_CTL_CF_OVERLAP_WINDOW_S 0
496 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A 0x0001FC00
498 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF
499 #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0
501 #define AR_PHY_TEST(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x15c : 0x160))
503 #define AR_PHY_TEST_BBB_OBS_SEL 0x780000
509 #define AR_PHY_TEST_CHAIN_SEL 0xC0000000
512 #define AR_PHY_TEST_CTL_STATUS(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x160 : 0x164))
513 #define AR_PHY_TEST_CTL_TSTDAC_EN 0x1
514 #define AR_PHY_TEST_CTL_TSTDAC_EN_S 0
515 #define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C
517 #define AR_PHY_TEST_CTL_TX_OBS_MUX_SEL 0x60
519 #define AR_PHY_TEST_CTL_TSTADC_EN 0x100
521 #define AR_PHY_TEST_CTL_RX_OBS_SEL 0x3C00
523 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL 0xe0000000
527 #define AR_PHY_TSTDAC(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x164 : 0x168))
529 #define AR_PHY_CHAN_STATUS(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x168 : 0x16c))
531 #define AR_PHY_CHAN_INFO_MEMORY(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x16c : 0x170))
532 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 0x00000008
535 #define AR_PHY_CHNINFO_NOISEPWR(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x170 : 0x174))
536 #define AR_PHY_CHNINFO_GAINDIFF(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x174 : 0x178))
537 #define AR_PHY_CHNINFO_FINETIM(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x178 : 0x17c))
538 #define AR_PHY_CHAN_INFO_GAIN_0(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x17c : 0x180))
539 #define AR_PHY_SCRAMBLER_SEED(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x184 : 0x190))
540 #define AR_PHY_CCK_TX_CTRL(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x188 : 0x194))
542 #define AR_PHY_HEAVYCLIP_CTL(_ah) (AR_SM_BASE + (AR_SREV_9561(_ah) ? 0x198 : 0x1a4))
543 #define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8)
544 #define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac)
545 #define AR_PHY_HEAVYCLIP_1 (AR_SM_BASE + 0x19c)
546 #define AR_PHY_HEAVYCLIP_2 (AR_SM_BASE + 0x1a0)
547 #define AR_PHY_HEAVYCLIP_3 (AR_SM_BASE + 0x1a4)
548 #define AR_PHY_HEAVYCLIP_4 (AR_SM_BASE + 0x1a8)
549 #define AR_PHY_HEAVYCLIP_5 (AR_SM_BASE + 0x1ac)
550 #define AR_PHY_ILLEGAL_TXRATE (AR_SM_BASE + 0x1b0)
552 #define AR_PHY_POWER_TX_RATE(_d) (AR_SM_BASE + 0x1c0 + ((_d) << 2))
554 #define AR_PHY_PWRTX_MAX (AR_SM_BASE + 0x1f0)
555 #define AR_PHY_POWER_TX_SUB (AR_SM_BASE + 0x1f4)
557 #define AR_PHY_TPC_1 (AR_SM_BASE + 0x1f8)
558 #define AR_PHY_TPC_1_FORCED_DAC_GAIN 0x0000003e
560 #define AR_PHY_TPC_1_FORCE_DAC_GAIN 0x00000001
561 #define AR_PHY_TPC_1_FORCE_DAC_GAIN_S 0
563 #define AR_PHY_TPC_4_B0 (AR_SM_BASE + 0x204)
564 #define AR_PHY_TPC_5_B0 (AR_SM_BASE + 0x208)
565 #define AR_PHY_TPC_6_B0 (AR_SM_BASE + 0x20c)
567 #define AR_PHY_TPC_11_B0 (AR_SM_BASE + 0x220)
568 #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
569 #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
570 #define AR_PHY_TPC_11_OLPC_GAIN_DELTA 0x00ff0000
573 #define AR_PHY_TPC_12 (AR_SM_BASE + 0x224)
574 #define AR_PHY_TPC_12_DESIRED_SCALE_HT40_5 0x3e000000
577 #define AR_PHY_TPC_18 (AR_SM_BASE + 0x23c)
578 #define AR_PHY_TPC_18_THERM_CAL_VALUE 0x000000ff
579 #define AR_PHY_TPC_18_THERM_CAL_VALUE_S 0
580 #define AR_PHY_TPC_18_VOLT_CAL_VALUE 0x0000ff00
583 #define AR_PHY_TPC_19 (AR_SM_BASE + 0x240)
584 #define AR_PHY_TPC_19_ALPHA_VOLT 0x001f0000
586 #define AR_PHY_TPC_19_ALPHA_THERM 0xff
587 #define AR_PHY_TPC_19_ALPHA_THERM_S 0
589 #define AR_PHY_TX_FORCED_GAIN (AR_SM_BASE + 0x258)
590 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN 0x00000001
591 #define AR_PHY_TX_FORCED_GAIN_FORCE_TX_GAIN_S 0
592 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN 0x0000000e
594 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN 0x00000030
596 #define AR_PHY_TX_FORCED_GAIN_FORCED_TXMXRGAIN 0x000003c0
598 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNA 0x00003c00
600 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNB 0x0003c000
602 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGNC 0x003c0000
604 #define AR_PHY_TX_FORCED_GAIN_FORCED_PADRVGND 0x00c00000
606 #define AR_PHY_TX_FORCED_GAIN_FORCED_ENABLE_PAL 0x01000000
610 #define AR_PHY_PDADC_TAB_0 (AR_SM_BASE + 0x280)
612 #define AR_PHY_TXGAIN_TABLE (AR_SM_BASE + 0x300)
615 0x3c4 : 0x444))
617 0x3c8 : 0x448))
619 0x3c4 : 0x440))
621 0x3f0 : 0x48c))
624 0x3d0 : 0x450) + ((_i) << 2))
625 #define AR_PHY_RTT_CTRL (AR_SM_BASE + 0x380)
627 #define AR_PHY_WATCHDOG_STATUS (AR_SM_BASE + 0x5c0)
628 #define AR_PHY_WATCHDOG_CTL_1 (AR_SM_BASE + 0x5c4)
629 #define AR_PHY_WATCHDOG_CTL_2 (AR_SM_BASE + 0x5c8)
630 #define AR_PHY_WATCHDOG_CTL (AR_SM_BASE + 0x5cc)
631 #define AR_PHY_ONLY_WARMRESET (AR_SM_BASE + 0x5d0)
632 #define AR_PHY_ONLY_CTL (AR_SM_BASE + 0x5d4)
633 #define AR_PHY_ECO_CTRL (AR_SM_BASE + 0x5dc)
635 #define AR_PHY_BB_THERM_ADC_1 (AR_SM_BASE + 0x248)
636 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM 0x000000ff
637 #define AR_PHY_BB_THERM_ADC_1_INIT_THERM_S 0
639 #define AR_PHY_BB_THERM_ADC_3 (AR_SM_BASE + 0x250)
640 #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_SCALE_GAIN 0x0001ff00
642 #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET 0x000000ff
643 #define AR_PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_S 0
645 #define AR_PHY_BB_THERM_ADC_4 (AR_SM_BASE + 0x254)
646 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE 0x000000ff
647 #define AR_PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_S 0
648 #define AR_PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE 0x0000ff00
651 #define AR_PHY_65NM_CH0_TXRF3 0x16048
652 #define AR_PHY_65NM_CH0_TXRF3_CAPDIV2G 0x0000001e
655 #define AR_PHY_65NM_CH0_SYNTH4 0x1608c
656 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x00000001 : 0x…
657 #define AR_PHY_SYNTH4_LONG_SHIFT_SELECT_S ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0 : 1)
658 #define AR_PHY_65NM_CH0_SYNTH7 0x16098
659 #define AR_PHY_65NM_CH0_SYNTH12 0x160ac
660 #define AR_PHY_65NM_CH0_BIAS1 0x160c0
661 #define AR_PHY_65NM_CH0_BIAS2 0x160c4
662 #define AR_PHY_65NM_CH0_BIAS4 0x160cc
663 #define AR_PHY_65NM_CH0_RXTX2 0x16104
664 #define AR_PHY_65NM_CH1_RXTX2 0x16504
665 #define AR_PHY_65NM_CH2_RXTX2 0x16904
666 #define AR_PHY_65NM_CH0_RXTX4 0x1610c
667 #define AR_PHY_65NM_CH1_RXTX4 0x1650c
668 #define AR_PHY_65NM_CH2_RXTX4 0x1690c
670 #define AR_PHY_65NM_CH0_BB1 0x16140
671 #define AR_PHY_65NM_CH0_BB2 0x16144
672 #define AR_PHY_65NM_CH0_BB3 0x16148
673 #define AR_PHY_65NM_CH1_BB1 0x16540
674 #define AR_PHY_65NM_CH1_BB2 0x16544
675 #define AR_PHY_65NM_CH1_BB3 0x16548
676 #define AR_PHY_65NM_CH2_BB1 0x16940
677 #define AR_PHY_65NM_CH2_BB2 0x16944
678 #define AR_PHY_65NM_CH2_BB3 0x16948
680 #define AR_PHY_65NM_CH0_SYNTH12_VREFMUL3 0x00780000
682 #define AR_PHY_65NM_CH0_RXTX2_SYNTHON_MASK 0x00000004
684 #define AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK 0x00000008
687 #define AR_CH0_TOP(_ah) (AR_SREV_9300(_ah) ? 0x16288 : \
688 (((AR_SREV_9462(_ah) || AR_SREV_9565(_ah)) ? 0x1628c : 0x16280)))
689 #define AR_CH0_TOP_XPABIASLVL (AR_SREV_9550(ah) ? 0x3c0 : 0x300)
692 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
693 #define AR_SWITCH_TABLE_COM_ALL_S (0)
694 #define AR_SWITCH_TABLE_COM_AR9462_ALL (0xffffff)
695 #define AR_SWITCH_TABLE_COM_AR9462_ALL_S (0)
696 #define AR_SWITCH_TABLE_COM_AR9550_ALL (0xffffff)
697 #define AR_SWITCH_TABLE_COM_AR9550_ALL_S (0)
698 #define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
699 #define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)
702 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
703 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
705 #define AR_SWITCH_TABLE_ALL (0xfff)
706 #define AR_SWITCH_TABLE_ALL_S (0)
708 #define AR_CH0_THERM(_ah) (AR_SREV_9300(_ah) ? 0x16290 :\
709 ((AR_SREV_9462(_ah) || AR_SREV_9565(_ah)) ? 0x16294 : 0x1628c))
710 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
711 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
712 #define AR_CH0_THERM_XPASHORT2GND 0x4
715 #define AR_CH0_THERM_LOCAL 0x80000000
716 #define AR_CH0_THERM_START 0x20000000
717 #define AR_CH0_THERM_SAR_ADC_OUT 0x0000ff00
720 #define AR_CH0_TOP2(_ah) (AR_SREV_9300(_ah) ? 0x1628c : \
721 (AR_SREV_9462(_ah) ? 0x16290 : 0x16284))
722 #define AR_CH0_TOP2_XPABIASLVL (AR_SREV_9561(ah) ? 0x1e00 : 0xf000)
725 #define AR_CH0_XTAL(_ah) (AR_SREV_9300(_ah) ? 0x16294 : \
726 ((AR_SREV_9462(_ah) || AR_SREV_9565(_ah)) ? 0x16298 : \
727 (AR_SREV_9561(_ah) ? 0x162c0 : 0x16290)))
728 #define AR_CH0_XTAL_CAPINDAC 0x7f000000
730 #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000
733 #define AR_PHY_PMU1(_ah) ((AR_SREV_9462(_ah) || AR_SREV_9565(_ah)) ? 0x16340 : \
734 (AR_SREV_9561(_ah) ? 0x16cc0 : 0x16c40))
735 #define AR_PHY_PMU1_PWD 0x1
736 #define AR_PHY_PMU1_PWD_S 0
738 #define AR_PHY_PMU2(_ah) ((AR_SREV_9462(_ah) || AR_SREV_9565(_ah)) ? 0x16344 : \
739 (AR_SREV_9561(_ah) ? 0x16cc4 : 0x16c44))
740 #define AR_PHY_PMU2_PGM 0x00200000
743 #define AR_PHY_RX1DB_BIQUAD_LONG_SHIFT 0x00380000
745 #define AR_PHY_RX6DB_BIQUAD_LONG_SHIFT 0x00c00000
747 #define AR_PHY_LNAGAIN_LONG_SHIFT 0xe0000000
749 #define AR_PHY_MXRGAIN_LONG_SHIFT 0x03000000
751 #define AR_PHY_VGAGAIN_LONG_SHIFT 0x1c000000
753 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT 0x00000001
754 #define AR_PHY_SCFIR_GAIN_LONG_SHIFT_S 0
755 #define AR_PHY_MANRXGAIN_LONG_SHIFT 0x00000002
761 #define AR_PHY_CL_CAL_ENABLE 0x00000002
762 #define AR_PHY_PARALLEL_CAL_ENABLE 0x00000001
763 #define AR_PHY_TPCRG1_PD_CAL_ENABLE 0x00400000
766 #define AR_PHY_ADDAC_PARACTL_OFF_PWDADC 0x00008000
768 #define AR_PHY_FCAL20_CAP_STATUS_0 0x01f00000
771 #define AR_PHY_RFBUS_REQ_EN 0x00000001 /* request for RF bus */
772 #define AR_PHY_RFBUS_GRANT_EN 0x00000001 /* RF bus granted */
773 #define AR_PHY_GC_TURBO_MODE 0x00000001 /* set turbo mode bits */
774 #define AR_PHY_GC_TURBO_SHORT 0x00000002 /* set short symbols to turbo mode setting */
775 #define AR_PHY_GC_DYN2040_EN 0x00000004 /* enable dyn 20/40 mode */
776 #define AR_PHY_GC_DYN2040_PRI_ONLY 0x00000008 /* dyn 20/40 - primary only */
777 #define AR_PHY_GC_DYN2040_PRI_CH 0x00000010 /* dyn 20/40 - primary ch offset (0=+10MHz, 1=-10MHz…
779 #define AR_PHY_GC_DYN2040_EXT_CH 0x00000020 /* dyn 20/40 - ext ch spacing (0=20MHz/ 1=25MHz) */
780 #define AR_PHY_GC_HT_EN 0x00000040 /* ht enable */
781 #define AR_PHY_GC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */
782 #define AR_PHY_GC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX…
783 #define AR_PHY_GC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */
784 #define AR_PHY_GC_GF_DETECT_EN 0x00000400 /* enable Green Field detection. Only affects rx, no…
785 #define AR_PHY_GC_ENABLE_DAC_FIFO 0x00000800 /* fifo between bb and dac */
786 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF /* delay from wakeup to rx ena */
788 #define AR_PHY_CALMODE_IQ 0x00000000
789 #define AR_PHY_CALMODE_ADC_GAIN 0x00000001
790 #define AR_PHY_CALMODE_ADC_DC_PER 0x00000002
791 #define AR_PHY_CALMODE_ADC_DC_INIT 0x00000003
792 #define AR_PHY_SWAP_ALT_CHAIN 0x00000040
793 #define AR_PHY_MODE_OFDM 0x00000000
794 #define AR_PHY_MODE_CCK 0x00000001
795 #define AR_PHY_MODE_DYNAMIC 0x00000004
797 #define AR_PHY_MODE_HALF 0x00000020
798 #define AR_PHY_MODE_QUARTER 0x00000040
799 #define AR_PHY_MAC_CLK_MODE 0x00000080
800 #define AR_PHY_MODE_DYN_CCK_DISABLE 0x00000100
801 #define AR_PHY_MODE_SVD_HALF 0x00000200
802 #define AR_PHY_ACTIVE_EN 0x00000001
803 #define AR_PHY_ACTIVE_DIS 0x00000000
804 #define AR_PHY_FORCE_XPA_CFG 0x000000001
805 #define AR_PHY_FORCE_XPA_CFG_S 0
806 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF 0xFF000000
808 #define AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF 0x00FF0000
810 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON 0x0000FF00
812 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON 0x000000FF
813 #define AR_PHY_XPA_TIMING_CTL_FRAME_XPAA_ON_S 0
814 #define AR_PHY_TX_END_TO_A2_RX_ON 0x00FF0000
816 #define AR_PHY_TX_END_DATA_START 0x000000FF
817 #define AR_PHY_TX_END_DATA_START_S 0
818 #define AR_PHY_TX_END_PA_ON 0x0000FF00
820 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP 0x0000000F
821 #define AR_PHY_TPCRG5_PD_GAIN_OVERLAP_S 0
822 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1 0x000003F0
824 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2 0x0000FC00
826 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3 0x003F0000
828 #define AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4 0x0FC00000
830 #define AR_PHY_TPCRG1_NUM_PD_GAIN 0x0000c000
832 #define AR_PHY_TPCRG1_PD_GAIN_1 0x00030000
834 #define AR_PHY_TPCRG1_PD_GAIN_2 0x000C0000
836 #define AR_PHY_TPCRG1_PD_GAIN_3 0x00300000
838 #define AR_PHY_TPCGR1_FORCED_DAC_GAIN 0x0000003e
840 #define AR_PHY_TPCGR1_FORCE_DAC_GAIN 0x00000001
841 #define AR_PHY_TXGAIN_FORCE 0x00000001
842 #define AR_PHY_TXGAIN_FORCE_S 0
843 #define AR_PHY_TXGAIN_FORCED_PADVGNRA 0x00003c00
845 #define AR_PHY_TXGAIN_FORCED_PADVGNRB 0x0003c000
847 #define AR_PHY_TXGAIN_FORCED_PADVGNRD 0x00c00000
849 #define AR_PHY_TXGAIN_FORCED_TXMXRGAIN 0x000003c0
851 #define AR_PHY_TXGAIN_FORCED_TXBB1DBGAIN 0x0000000e
854 #define AR_PHY_POWER_TX_RATE_MAX 0x993c
855 #define AR_PHY_POWER_TX_RATE_MAX_TPC_ENABLE 0x00000040
856 #define PHY_AGC_CLR 0x10000000
857 #define RFSILENT_BB 0x00002000
858 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_MASK 0xFFF
859 #define AR_PHY_CHAN_INFO_GAIN_DIFF_PPM_SIGNED_BIT 0x800
861 #define AR_PHY_CHAN_INFO_MEMORY_CAPTURE_MASK 0x0001
862 #define AR_PHY_RX_DELAY_DELAY 0x00003FFF
863 #define AR_PHY_CCK_TX_CTRL_JAPAN 0x00000010
865 #define AR_PHY_SPECTRAL_SCAN_ENABLE 0x00000001
866 #define AR_PHY_SPECTRAL_SCAN_ENABLE_S 0
867 #define AR_PHY_SPECTRAL_SCAN_ACTIVE 0x00000002
869 #define AR_PHY_SPECTRAL_SCAN_FFT_PERIOD 0x000000F0
871 #define AR_PHY_SPECTRAL_SCAN_PERIOD 0x0000FF00
873 #define AR_PHY_SPECTRAL_SCAN_COUNT 0x0FFF0000
875 #define AR_PHY_SPECTRAL_SCAN_SHORT_REPEAT 0x10000000
877 #define AR_PHY_SPECTRAL_SCAN_PRIORITY 0x20000000
879 #define AR_PHY_SPECTRAL_SCAN_USE_ERR5 0x40000000
881 #define AR_PHY_SPECTRAL_SCAN_COMPRESSED_RPT 0x80000000
884 #define AR_PHY_CHANNEL_STATUS_RX_CLEAR 0x00000004
885 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION 0x00000001
886 #define AR_PHY_RTT_CTRL_ENA_RADIO_RETENTION_S 0
887 #define AR_PHY_RTT_CTRL_RESTORE_MASK 0x0000007E
889 #define AR_PHY_RTT_CTRL_FORCE_RADIO_RESTORE 0x00000080
891 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS 0x00000001
892 #define AR_PHY_RTT_SW_RTT_TABLE_ACCESS_S 0
893 #define AR_PHY_RTT_SW_RTT_TABLE_WRITE 0x00000002
895 #define AR_PHY_RTT_SW_RTT_TABLE_ADDR 0x0000001C
897 #define AR_PHY_RTT_SW_RTT_TABLE_DATA 0xFFFFFFF0
899 #define AR_PHY_TX_IQCAL_CONTROL_0_ENABLE_TXIQ_CAL 0x80000000
901 #define AR_PHY_TX_IQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT 0x01fc0000
903 #define AR_PHY_TX_IQCAL_START_DO_CAL 0x00000001
904 #define AR_PHY_TX_IQCAL_START_DO_CAL_S 0
906 #define AR_PHY_TX_IQCAL_STATUS_FAILED 0x00000001
907 #define AR_PHY_CALIBRATED_GAINS_0 0x3e
910 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE 0x00003fff
911 #define AR_PHY_TX_IQCAL_CORR_COEFF_00_COEFF_TABLE_S 0
912 #define AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE 0x0fffc000
915 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON 0x10000000
917 #define AR_PHY_65NM_CH0_RXTX4_THERM_ON_OVR 0x20000000
920 #define AR_PHY_65NM_RXTX4_XLNA_BIAS 0xC0000000
926 #define AR_CHAN1_BASE 0xa800
928 #define AR_PHY_EXT_CCA_1 (AR_CHAN1_BASE + 0x30)
929 #define AR_PHY_TX_PHASE_RAMP_1 (AR_CHAN1_BASE + 0xd0)
930 #define AR_PHY_ADC_GAIN_DC_CORR_1 (AR_CHAN1_BASE + 0xd4)
932 #define AR_PHY_SPUR_REPORT_1 (AR_CHAN1_BASE + 0xa8)
933 #define AR_PHY_CHAN_INFO_TAB_1 (AR_CHAN1_BASE + 0x300)
934 #define AR_PHY_RX_IQCAL_CORR_B1 (AR_CHAN1_BASE + 0xdc)
939 #define AR_PHY_CH1_EXT_MINCCA_PWR 0x01FF0000
945 #define AR_AGC1_BASE 0xae00
947 #define AR_PHY_FORCEMAX_GAINS_1 (AR_AGC1_BASE + 0x4)
948 #define AR_PHY_EXT_ATTEN_CTL_1 (AR_AGC1_BASE + 0x18)
949 #define AR_PHY_CCA_1 (AR_AGC1_BASE + 0x1c)
950 #define AR_PHY_CCA_CTRL_1 (AR_AGC1_BASE + 0x20)
951 #define AR_PHY_RSSI_1 (AR_AGC1_BASE + 0x180)
952 #define AR_PHY_SPUR_CCK_REP_1 (AR_AGC1_BASE + 0x184)
953 #define AR_PHY_RX_OCGAIN_2 (AR_AGC1_BASE + 0x200)
958 #define AR_PHY_CH1_MINCCA_PWR 0x1FF00000
964 #define AR_SM1_BASE 0xb200
966 #define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84)
967 #define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0)
968 #define AR_PHY_DFT_TONE_CTL_1 (AR_SM1_BASE + 0xd4)
969 #define AR_PHY_CL_TAB_1 (AR_SM1_BASE + 0x100)
970 #define AR_PHY_CHAN_INFO_GAIN_1 (AR_SM1_BASE + 0x180)
971 #define AR_PHY_TPC_4_B1 (AR_SM1_BASE + 0x204)
972 #define AR_PHY_TPC_5_B1 (AR_SM1_BASE + 0x208)
973 #define AR_PHY_TPC_6_B1 (AR_SM1_BASE + 0x20c)
974 #define AR_PHY_TPC_11_B1 (AR_SM1_BASE + 0x220)
976 0x280 : 0x240))
977 #define AR_PHY_TPC_19_B1 (AR_SM1_BASE + 0x240)
978 #define AR_PHY_TPC_19_B1_ALPHA_THERM 0xff
979 #define AR_PHY_TPC_19_B1_ALPHA_THERM_S 0
980 #define AR_PHY_TX_IQCAL_STATUS_B1 (AR_SM1_BASE + 0x48c)
981 #define AR_PHY_TX_IQCAL_CORR_COEFF_B1(_i) (AR_SM1_BASE + 0x450 + ((_i) << 2))
983 #define AR_PHY_RTT_TABLE_SW_INTF_B(i) (0x384 + ((i) ? \
985 #define AR_PHY_RTT_TABLE_SW_INTF_1_B(i) (0x388 + ((i) ? \
990 #define AR_CHAN2_BASE 0xb800
992 #define AR_PHY_EXT_CCA_2 (AR_CHAN2_BASE + 0x30)
993 #define AR_PHY_TX_PHASE_RAMP_2 (AR_CHAN2_BASE + 0xd0)
994 #define AR_PHY_ADC_GAIN_DC_CORR_2 (AR_CHAN2_BASE + 0xd4)
996 #define AR_PHY_SPUR_REPORT_2 (AR_CHAN2_BASE + 0xa8)
997 #define AR_PHY_CHAN_INFO_TAB_2 (AR_CHAN2_BASE + 0x300)
998 #define AR_PHY_RX_IQCAL_CORR_B2 (AR_CHAN2_BASE + 0xdc)
1003 #define AR_PHY_CH2_EXT_MINCCA_PWR 0x01FF0000
1008 #define AR_AGC2_BASE 0xbe00
1010 #define AR_PHY_FORCEMAX_GAINS_2 (AR_AGC2_BASE + 0x4)
1011 #define AR_PHY_EXT_ATTEN_CTL_2 (AR_AGC2_BASE + 0x18)
1012 #define AR_PHY_CCA_2 (AR_AGC2_BASE + 0x1c)
1013 #define AR_PHY_CCA_CTRL_2 (AR_AGC2_BASE + 0x20)
1014 #define AR_PHY_RSSI_2 (AR_AGC2_BASE + 0x180)
1019 #define AR_PHY_CH2_MINCCA_PWR 0x1FF00000
1025 #define AR_SM2_BASE 0xc200
1027 #define AR_PHY_SWITCH_CHAIN_2 (AR_SM2_BASE + 0x84)
1028 #define AR_PHY_FCAL_2_2 (AR_SM2_BASE + 0xd0)
1029 #define AR_PHY_DFT_TONE_CTL_2 (AR_SM2_BASE + 0xd4)
1030 #define AR_PHY_CL_TAB_2 (AR_SM2_BASE + 0x100)
1031 #define AR_PHY_CHAN_INFO_GAIN_2 (AR_SM2_BASE + 0x180)
1032 #define AR_PHY_TPC_4_B2 (AR_SM2_BASE + 0x204)
1033 #define AR_PHY_TPC_5_B2 (AR_SM2_BASE + 0x208)
1034 #define AR_PHY_TPC_6_B2 (AR_SM2_BASE + 0x20c)
1035 #define AR_PHY_TPC_11_B2 (AR_SM2_BASE + 0x220)
1036 #define AR_PHY_TPC_19_B2 (AR_SM2_BASE + 0x240)
1037 #define AR_PHY_TX_IQCAL_STATUS_B2 (AR_SM2_BASE + 0x48c)
1038 #define AR_PHY_TX_IQCAL_CORR_COEFF_B2(_i) (AR_SM2_BASE + 0x450 + ((_i) << 2))
1040 #define AR_PHY_TX_IQCAL_STATUS_B2_FAILED 0x00000001
1043 #define AR_GLB_BASE 0x20000
1045 #define AR_PHY_GLB_CONTROL (AR_GLB_BASE + 0x44)
1047 (AR_SREV_9462_20_OR_LATER(_ah) ? 0x4c : 0x50))
1048 #define AR_GLB_STATUS (AR_GLB_BASE + 0x48)
1073 #define AR_PHY_WATCHDOG_NON_IDLE_ENABLE 0x00000001
1074 #define AR_PHY_WATCHDOG_IDLE_ENABLE 0x00000002
1075 #define AR_PHY_WATCHDOG_IDLE_MASK 0xFFFF0000
1076 #define AR_PHY_WATCHDOG_NON_IDLE_MASK 0x0000FFFC
1078 #define AR_PHY_WATCHDOG_RST_ENABLE 0x00000002
1079 #define AR_PHY_WATCHDOG_IRQ_ENABLE 0x00000004
1080 #define AR_PHY_WATCHDOG_CNTL2_MASK 0xFFFFFFF9
1082 #define AR_PHY_WATCHDOG_INFO 0x00000007
1083 #define AR_PHY_WATCHDOG_INFO_S 0
1084 #define AR_PHY_WATCHDOG_DET_HANG 0x00000008
1086 #define AR_PHY_WATCHDOG_RADAR_SM 0x000000F0
1088 #define AR_PHY_WATCHDOG_RX_OFDM_SM 0x00000F00
1090 #define AR_PHY_WATCHDOG_RX_CCK_SM 0x0000F000
1092 #define AR_PHY_WATCHDOG_TX_OFDM_SM 0x000F0000
1094 #define AR_PHY_WATCHDOG_TX_CCK_SM 0x00F00000
1096 #define AR_PHY_WATCHDOG_AGC_SM 0x0F000000
1098 #define AR_PHY_WATCHDOG_SRCH_SM 0xF0000000
1101 #define AR_PHY_WATCHDOG_STATUS_CLR 0x00000008
1106 #define AR_PHY_XPA_TIMING_CTL (AR_SM_BASE + 0x64)
1108 #define AR_PHY_PAPRD_AM2AM (AR_CHAN_BASE + 0xe4)
1109 #define AR_PHY_PAPRD_AM2AM_MASK 0x01ffffff
1110 #define AR_PHY_PAPRD_AM2AM_MASK_S 0
1112 #define AR_PHY_PAPRD_AM2PM (AR_CHAN_BASE + 0xe8)
1113 #define AR_PHY_PAPRD_AM2PM_MASK 0x01ffffff
1114 #define AR_PHY_PAPRD_AM2PM_MASK_S 0
1116 #define AR_PHY_PAPRD_HT40 (AR_CHAN_BASE + 0xec)
1117 #define AR_PHY_PAPRD_HT40_MASK 0x01ffffff
1118 #define AR_PHY_PAPRD_HT40_MASK_S 0
1120 #define AR_PHY_PAPRD_CTRL0_B0 (AR_CHAN_BASE + 0xf0)
1121 #define AR_PHY_PAPRD_CTRL0_B1 (AR_CHAN1_BASE + 0xf0)
1122 #define AR_PHY_PAPRD_CTRL0_B2 (AR_CHAN2_BASE + 0xf0)
1123 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE 0x00000001
1124 #define AR_PHY_PAPRD_CTRL0_PAPRD_ENABLE_S 0
1125 #define AR_PHY_PAPRD_CTRL0_USE_SINGLE_TABLE_MASK 0x00000002
1127 #define AR_PHY_PAPRD_CTRL0_PAPRD_MAG_THRSH 0xf8000000
1130 #define AR_PHY_PAPRD_CTRL1_B0 (AR_CHAN_BASE + 0xf4)
1131 #define AR_PHY_PAPRD_CTRL1_B1 (AR_CHAN1_BASE + 0xf4)
1132 #define AR_PHY_PAPRD_CTRL1_B2 (AR_CHAN2_BASE + 0xf4)
1133 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA 0x00000001
1134 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_SCALING_ENA_S 0
1135 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2AM_ENABLE 0x00000002
1137 #define AR_PHY_PAPRD_CTRL1_ADAPTIVE_AM2PM_ENABLE 0x00000004
1139 #define AR_PHY_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL 0x000001f8
1141 #define AR_PHY_PAPRD_CTRL1_PA_GAIN_SCALE_FACT_MASK 0x0001fe00
1143 #define AR_PHY_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACT 0x0ffe0000
1146 #define AR_PHY_PAPRD_TRAINER_CNTL1(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x580 : 0x490))
1148 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE 0x00000001
1149 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_CF_PAPRD_TRAIN_ENABLE_S 0
1150 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING 0x0000007e
1152 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE 0x00000100
1154 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE 0x00000200
1156 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE 0x00000400
1158 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE 0x00000800
1160 #define AR_PHY_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP 0x0003f000
1163 #define AR_PHY_PAPRD_TRAINER_CNTL2(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x584 : 0x494))
1165 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN 0xFFFFFFFF
1166 #define AR_PHY_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_S 0
1168 #define AR_PHY_PAPRD_TRAINER_CNTL3(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x588 : 0x498))
1170 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE 0x0000003f
1171 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_S 0
1172 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP 0x00000fc0
1174 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL 0x0001f000
1176 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES 0x000e0000
1178 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN 0x00f00000
1180 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN 0x0f000000
1182 #define AR_PHY_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE 0x20000000
1185 #define AR_PHY_PAPRD_TRAINER_CNTL4(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x58c : 0x49c))
1187 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES 0x03ff0000
1189 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA 0x0000f000
1191 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR 0x00000fff
1192 #define AR_PHY_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_S 0
1194 #define AR_PHY_PAPRD_PRE_POST_SCALE_0_B0 (AR_CHAN_BASE + 0x100)
1195 #define AR_PHY_PAPRD_PRE_POST_SCALE_1_B0 (AR_CHAN_BASE + 0x104)
1196 #define AR_PHY_PAPRD_PRE_POST_SCALE_2_B0 (AR_CHAN_BASE + 0x108)
1197 #define AR_PHY_PAPRD_PRE_POST_SCALE_3_B0 (AR_CHAN_BASE + 0x10c)
1198 #define AR_PHY_PAPRD_PRE_POST_SCALE_4_B0 (AR_CHAN_BASE + 0x110)
1199 #define AR_PHY_PAPRD_PRE_POST_SCALE_5_B0 (AR_CHAN_BASE + 0x114)
1200 #define AR_PHY_PAPRD_PRE_POST_SCALE_6_B0 (AR_CHAN_BASE + 0x118)
1201 #define AR_PHY_PAPRD_PRE_POST_SCALE_7_B0 (AR_CHAN_BASE + 0x11c)
1202 #define AR_PHY_PAPRD_PRE_POST_SCALING 0x3FFFF
1203 #define AR_PHY_PAPRD_PRE_POST_SCALING_S 0
1205 #define AR_PHY_PAPRD_TRAINER_STAT1(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x590 : 0x4a0))
1207 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE 0x00000001
1208 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_S 0
1209 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE 0x00000002
1211 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR 0x00000004
1213 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE 0x00000008
1215 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX 0x000001f0
1217 #define AR_PHY_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR 0x0001fe00
1220 #define AR_PHY_PAPRD_TRAINER_STAT2(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x594 : 0x4a4))
1222 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL 0x0000ffff
1223 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_S 0
1224 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX 0x001f0000
1226 #define AR_PHY_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX 0x00600000
1229 #define AR_PHY_PAPRD_TRAINER_STAT3(_ah) (AR_SM_BASE + (AR_SREV_9485(_ah) ? 0x598 : 0x4a8))
1231 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT 0x000fffff
1232 #define AR_PHY_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_S 0
1234 #define AR_PHY_PAPRD_MEM_TAB_B0 (AR_CHAN_BASE + 0x120)
1235 #define AR_PHY_PAPRD_MEM_TAB_B1 (AR_CHAN1_BASE + 0x120)
1236 #define AR_PHY_PAPRD_MEM_TAB_B2 (AR_CHAN2_BASE + 0x120)
1238 #define AR_PHY_PA_GAIN123_B0 (AR_CHAN_BASE + 0xf8)
1239 #define AR_PHY_PA_GAIN123_B1 (AR_CHAN1_BASE + 0xf8)
1240 #define AR_PHY_PA_GAIN123_B2 (AR_CHAN2_BASE + 0xf8)
1241 #define AR_PHY_PA_GAIN123_PA_GAIN1 0x3FF
1242 #define AR_PHY_PA_GAIN123_PA_GAIN1_S 0
1244 #define AR_PHY_POWERTX_RATE5 (AR_SM_BASE + 0x1d0)
1245 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0 0x3F
1246 #define AR_PHY_POWERTX_RATE5_POWERTXHT20_0_S 0
1248 #define AR_PHY_POWERTX_RATE6 (AR_SM_BASE + 0x1d4)
1249 #define AR_PHY_POWERTX_RATE6_POWERTXHT20_5 0x3F00
1252 #define AR_PHY_POWERTX_RATE8 (AR_SM_BASE + 0x1dc)
1253 #define AR_PHY_POWERTX_RATE8_POWERTXHT40_5 0x3F00
1256 #define AR_PHY_CL_TAB_CL_GAIN_MOD 0x1f
1257 #define AR_PHY_CL_TAB_CL_GAIN_MOD_S 0
1259 #define AR_BTCOEX_WL_LNADIV 0x1a64
1260 #define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD 0x00003FFF
1261 #define AR_BTCOEX_WL_LNADIV_PREDICTED_PERIOD_S 0
1262 #define AR_BTCOEX_WL_LNADIV_DPDT_IGNORE_PRIORITY 0x00004000
1264 #define AR_BTCOEX_WL_LNADIV_FORCE_ON 0x00008000
1266 #define AR_BTCOEX_WL_LNADIV_MODE_OPTION 0x00030000
1268 #define AR_BTCOEX_WL_LNADIV_MODE 0x007c0000
1270 #define AR_BTCOEX_WL_LNADIV_ALLOWED_TX_ANTDIV_WL_TX_REQ 0x00800000
1272 #define AR_BTCOEX_WL_LNADIV_DISABLE_TX_ANTDIV_ENABLE 0x01000000
1274 #define AR_BTCOEX_WL_LNADIV_CONTINUOUS_BT_ACTIVE_PROTECT 0x02000000
1276 #define AR_BTCOEX_WL_LNADIV_BT_INACTIVE_THRESHOLD 0xFC000000
1280 #define AR_PHY_65NM_BASE 0x16000
1282 (i * 0x400) + 0x8)
1283 #define AR_PHY_65NM_RXRF_GAINSTAGES_RX_OVERRIDE 0x80000000
1285 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNAON_CALDC 0x00000002
1287 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA2G_GAIN_OVR 0x70000000
1289 #define AR_PHY_65NM_RXRF_GAINSTAGES_LNA5G_GAIN_OVR 0x03800000
1293 (i * 0x400) + 0x104)
1294 #define AR_PHY_65NM_RXTX2_RXON_OVR 0x00001000
1296 #define AR_PHY_65NM_RXTX2_RXON 0x00000800
1300 (i * 0x400) + 0xc)
1301 #define AR_PHY_65NM_RXRF_AGC_AGC_OVERRIDE 0x80000000
1303 #define AR_PHY_65NM_RXRF_AGC_AGC_ON_OVR 0x40000000
1305 #define AR_PHY_65NM_RXRF_AGC_AGC_CAL_OVR 0x20000000
1307 #define AR_PHY_65NM_RXRF_AGC_AGC2G_DBDAC_OVR 0x1E000000
1309 #define AR_PHY_65NM_RXRF_AGC_AGC5G_DBDAC_OVR 0x00078000
1311 #define AR_PHY_65NM_RXRF_AGC_AGC2G_CALDAC_OVR 0x01F80000
1313 #define AR_PHY_65NM_RXRF_AGC_AGC5G_CALDAC_OVR 0x00007e00
1315 #define AR_PHY_65NM_RXRF_AGC_AGC_OUT 0x00000004