Lines Matching +full:common +full:- +full:mode +full:- +full:channel
2 * Copyright (c) 2010-2011 Atheros Communications Inc.
39 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
43 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
125 * ar9003_hw_set_channel - set channel on single-chip device
129 * This is the function to change channel on single-chip devices, that is
132 * This function takes the channel value in MHz and sets
133 * hardware channel value. Assumes writes have been enabled to analog bus.
137 * For 2GHz channel,
138 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
141 * For 5GHz channel,
142 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
146 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
159 if (freq < 4800) { /* 2 GHz, fractional mode */ in ar9003_hw_set_channel()
163 if (ah->is_clk_25mhz) in ar9003_hw_set_channel()
172 if (ah->is_clk_25mhz) { in ar9003_hw_set_channel()
182 /* Set to 2G mode */ in ar9003_hw_set_channel()
187 ah->is_clk_25mhz) { in ar9003_hw_set_channel()
196 /* Set to 5G mode */ in ar9003_hw_set_channel()
200 /* Enable fractional mode for all channels */ in ar9003_hw_set_channel()
217 /* Toggle Load Synth channel bit */ in ar9003_hw_set_channel()
223 ah->curchan = chan; in ar9003_hw_set_channel()
229 * ar9003_hw_spur_mitigate_mrc_cck - convert baseband spur frequency
233 * For single-chip solutions. Converts to baseband spur frequency given the
234 * input channel frequency and compute register settings below.
248 * Need to verify range +/- 10 MHz in control channel, otherwise spur in ar9003_hw_spur_mitigate_mrc_cck()
249 * is out-of-band and can be ignored. in ar9003_hw_spur_mitigate_mrc_cck()
261 synth_freq = chan->channel + 10; in ar9003_hw_spur_mitigate_mrc_cck()
263 synth_freq = chan->channel - 10; in ar9003_hw_spur_mitigate_mrc_cck()
266 synth_freq = chan->channel; in ar9003_hw_spur_mitigate_mrc_cck()
271 synth_freq = chan->channel; in ar9003_hw_spur_mitigate_mrc_cck()
286 cur_bb_spur -= synth_freq; in ar9003_hw_spur_mitigate_mrc_cck()
289 cur_bb_spur = -cur_bb_spur; in ar9003_hw_spur_mitigate_mrc_cck()
295 cck_spur_freq = -cck_spur_freq; in ar9003_hw_spur_mitigate_mrc_cck()
410 mask_index = mask_index - 1; in ar9003_hw_spur_ofdm()
443 mask_index = mask_index - 1; in ar9003_hw_spur_ofdm_9565()
496 spur_freq_sd = ((freq_offset - 10) << 9) / 11; in ar9003_hw_spur_ofdm_work()
530 return; /* No spur in the mode */ in ar9003_hw_spur_mitigate_ofdm()
536 synth_freq = chan->channel - 10; in ar9003_hw_spur_mitigate_ofdm()
538 synth_freq = chan->channel + 10; in ar9003_hw_spur_mitigate_ofdm()
541 synth_freq = chan->channel; in ar9003_hw_spur_mitigate_ofdm()
549 freq_offset -= synth_freq; in ar9003_hw_spur_mitigate_ofdm()
558 freq_offset -= synth_freq; in ar9003_hw_spur_mitigate_ofdm()
628 /* Configure control (primary) channel at +-10MHz */ in ar9003_hw_set_channel_regs()
669 if (ah->caps.tx_chainmask == 5 || ah->caps.rx_chainmask == 5) in ar9003_hw_set_chain_masks()
676 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) in ar9003_hw_set_chain_masks()
715 ah->enabled_cals |= TX_IQ_CAL; in ar9003_hw_override_ini()
717 ah->enabled_cals &= ~TX_IQ_CAL; in ar9003_hw_override_ini()
722 ah->enabled_cals |= TX_CL_CAL; in ar9003_hw_override_ini()
724 ah->enabled_cals &= ~TX_CL_CAL; in ar9003_hw_override_ini()
728 if (ah->is_clk_25mhz) { in ar9003_hw_override_ini()
748 if (!iniArr->ia_array) in ar9003_hw_prog_ini()
753 * may be modal (> 2 columns) or non-modal (2 columns). Determine if in ar9003_hw_prog_ini()
754 * the array is non-modal and force the column to 1. in ar9003_hw_prog_ini()
756 if (column >= iniArr->ia_columns) in ar9003_hw_prog_ini()
759 for (i = 0; i < iniArr->ia_rows; i++) { in ar9003_hw_prog_ini()
781 if (chan->channel <= 5350) in ar9550_hw_get_modes_txgain_index()
783 else if ((chan->channel > 5350) && (chan->channel <= 5600)) in ar9550_hw_get_modes_txgain_index()
870 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex); in ar9003_hw_process_ini()
871 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex); in ar9003_hw_process_ini()
872 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex); in ar9003_hw_process_ini()
873 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex); in ar9003_hw_process_ini()
876 &ah->ini_radio_post_sys2ant, in ar9003_hw_process_ini()
885 REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites); in ar9003_hw_process_ini()
889 * CUS217 mix LNA mode. in ar9003_hw_process_ini()
892 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_process_ini()
894 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_process_ini()
899 * 5G-XLNA in ar9003_hw_process_ini()
903 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, in ar9003_hw_process_ini()
909 REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, in ar9003_hw_process_ini()
913 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, in ar9003_hw_process_ini()
928 REG_WRITE_ARRAY(&ah->iniModesTxGain, modes_txgain_index, in ar9003_hw_process_ini()
931 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites); in ar9003_hw_process_ini()
939 REG_WRITE_ARRAY(&ah->iniModesFastClock, in ar9003_hw_process_ini()
945 REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites); in ar9003_hw_process_ini()
950 if (chan->channel == 2484) { in ar9003_hw_process_ini()
951 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_process_ini()
958 ah->modes_index = modesIndex; in ar9003_hw_process_ini()
961 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); in ar9003_hw_process_ini()
1004 * scale for selected channel bandwidth in ar9003_hw_set_delta_slope()
1012 * ALGO -> coef = 1e8/fcarrier*fclock/40; in ar9003_hw_set_delta_slope()
1057 ath9k_hw_synth_delay(ah, ah->curchan, synthDelay); in ar9003_hw_rfbus_done()
1065 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_control() local
1066 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_control()
1067 struct ar5416AniState *aniState = &ah->ani; in ar9003_hw_ani_control()
1075 switch (cmd & ah->ani_function) { in ar9003_hw_ani_control()
1090 aniState->iniDef.m1ThreshLow : m1ThreshLow_off; in ar9003_hw_ani_control()
1092 aniState->iniDef.m2ThreshLow : m2ThreshLow_off; in ar9003_hw_ani_control()
1094 aniState->iniDef.m1Thresh : m1Thresh_off; in ar9003_hw_ani_control()
1096 aniState->iniDef.m2Thresh : m2Thresh_off; in ar9003_hw_ani_control()
1098 aniState->iniDef.m2CountThr : m2CountThr_off; in ar9003_hw_ani_control()
1100 aniState->iniDef.m2CountThrLow : m2CountThrLow_off; in ar9003_hw_ani_control()
1102 aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off; in ar9003_hw_ani_control()
1104 aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off; in ar9003_hw_ani_control()
1106 aniState->iniDef.m1ThreshExt : m1ThreshExt_off; in ar9003_hw_ani_control()
1108 aniState->iniDef.m2ThreshExt : m2ThreshExt_off; in ar9003_hw_ani_control()
1148 if (on != aniState->ofdmWeakSigDetect) { in ar9003_hw_ani_control()
1149 ath_dbg(common, ANI, in ar9003_hw_ani_control()
1151 chan->channel, in ar9003_hw_ani_control()
1152 aniState->ofdmWeakSigDetect ? in ar9003_hw_ani_control()
1156 ah->stats.ast_ani_ofdmon++; in ar9003_hw_ani_control()
1158 ah->stats.ast_ani_ofdmoff++; in ar9003_hw_ani_control()
1159 aniState->ofdmWeakSigDetect = on; in ar9003_hw_ani_control()
1167 ath_dbg(common, ANI, in ar9003_hw_ani_control()
1177 value = firstep_table[level] - in ar9003_hw_ani_control()
1179 aniState->iniDef.firstep; in ar9003_hw_ani_control()
1192 value2 = firstep_table[level] - in ar9003_hw_ani_control()
1194 aniState->iniDef.firstepLow; in ar9003_hw_ani_control()
1203 if (level != aniState->firstepLevel) { in ar9003_hw_ani_control()
1204 ath_dbg(common, ANI, in ar9003_hw_ani_control()
1206 chan->channel, in ar9003_hw_ani_control()
1207 aniState->firstepLevel, in ar9003_hw_ani_control()
1211 aniState->iniDef.firstep); in ar9003_hw_ani_control()
1212 ath_dbg(common, ANI, in ar9003_hw_ani_control()
1214 chan->channel, in ar9003_hw_ani_control()
1215 aniState->firstepLevel, in ar9003_hw_ani_control()
1219 aniState->iniDef.firstepLow); in ar9003_hw_ani_control()
1220 if (level > aniState->firstepLevel) in ar9003_hw_ani_control()
1221 ah->stats.ast_ani_stepup++; in ar9003_hw_ani_control()
1222 else if (level < aniState->firstepLevel) in ar9003_hw_ani_control()
1223 ah->stats.ast_ani_stepdown++; in ar9003_hw_ani_control()
1224 aniState->firstepLevel = level; in ar9003_hw_ani_control()
1232 ath_dbg(common, ANI, in ar9003_hw_ani_control()
1241 value = cycpwrThr1_table[level] - in ar9003_hw_ani_control()
1243 aniState->iniDef.cycpwrThr1; in ar9003_hw_ani_control()
1253 * set AR_PHY_EXT_CCA for extension channel in ar9003_hw_ani_control()
1257 value2 = cycpwrThr1_table[level] - in ar9003_hw_ani_control()
1259 aniState->iniDef.cycpwrThr1Ext; in ar9003_hw_ani_control()
1267 if (level != aniState->spurImmunityLevel) { in ar9003_hw_ani_control()
1268 ath_dbg(common, ANI, in ar9003_hw_ani_control()
1270 chan->channel, in ar9003_hw_ani_control()
1271 aniState->spurImmunityLevel, in ar9003_hw_ani_control()
1275 aniState->iniDef.cycpwrThr1); in ar9003_hw_ani_control()
1276 ath_dbg(common, ANI, in ar9003_hw_ani_control()
1278 chan->channel, in ar9003_hw_ani_control()
1279 aniState->spurImmunityLevel, in ar9003_hw_ani_control()
1283 aniState->iniDef.cycpwrThr1Ext); in ar9003_hw_ani_control()
1284 if (level > aniState->spurImmunityLevel) in ar9003_hw_ani_control()
1285 ah->stats.ast_ani_spurup++; in ar9003_hw_ani_control()
1286 else if (level < aniState->spurImmunityLevel) in ar9003_hw_ani_control()
1287 ah->stats.ast_ani_spurdown++; in ar9003_hw_ani_control()
1288 aniState->spurImmunityLevel = level; in ar9003_hw_ani_control()
1299 if (ah->caps.rx_chainmask == 1) in ar9003_hw_ani_control()
1306 if (is_on != aniState->mrcCCK) { in ar9003_hw_ani_control()
1307 ath_dbg(common, ANI, "** ch %d: MRC CCK: %s=>%s\n", in ar9003_hw_ani_control()
1308 chan->channel, in ar9003_hw_ani_control()
1309 aniState->mrcCCK ? "on" : "off", in ar9003_hw_ani_control()
1312 ah->stats.ast_ani_ccklow++; in ar9003_hw_ani_control()
1314 ah->stats.ast_ani_cckhigh++; in ar9003_hw_ani_control()
1315 aniState->mrcCCK = is_on; in ar9003_hw_ani_control()
1320 ath_dbg(common, ANI, "invalid cmd %u\n", cmd); in ar9003_hw_ani_control()
1324 ath_dbg(common, ANI, in ar9003_hw_ani_control()
1326 aniState->spurImmunityLevel, in ar9003_hw_ani_control()
1327 aniState->ofdmWeakSigDetect ? "on" : "off", in ar9003_hw_ani_control()
1328 aniState->firstepLevel, in ar9003_hw_ani_control()
1329 aniState->mrcCCK ? "on" : "off", in ar9003_hw_ani_control()
1330 aniState->listenTime, in ar9003_hw_ani_control()
1331 aniState->ofdmPhyErrCount, in ar9003_hw_ani_control()
1332 aniState->cckPhyErrCount); in ar9003_hw_ani_control()
1348 if (ah->rxchainmask & BIT(i)) { in ar9003_hw_do_getnf()
1349 nf = MS(REG_READ(ah, ah->nf_regs[i]), in ar9003_hw_do_getnf()
1353 if (IS_CHAN_HT40(ah->curchan)) { in ar9003_hw_do_getnf()
1356 nf = MS(REG_READ(ah, ah->nf_regs[ext_idx]), in ar9003_hw_do_getnf()
1366 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1367 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1368 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9300_2GHZ; in ar9003_hw_set_nf_limits()
1369 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1370 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1371 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9300_5GHZ; in ar9003_hw_set_nf_limits()
1374 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9330_2GHZ; in ar9003_hw_set_nf_limits()
1377 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1378 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9462_2GHZ; in ar9003_hw_set_nf_limits()
1379 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1380 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9462_5GHZ; in ar9003_hw_set_nf_limits()
1392 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_ani_cache_ini_regs() local
1393 struct ath9k_channel *chan = ah->curchan; in ar9003_hw_ani_cache_ini_regs()
1397 aniState = &ah->ani; in ar9003_hw_ani_cache_ini_regs()
1398 iniDef = &aniState->iniDef; in ar9003_hw_ani_cache_ini_regs()
1400 ath_dbg(common, ANI, "ver %d.%d opmode %u chan %d Mhz\n", in ar9003_hw_ani_cache_ini_regs()
1401 ah->hw_version.macVersion, in ar9003_hw_ani_cache_ini_regs()
1402 ah->hw_version.macRev, in ar9003_hw_ani_cache_ini_regs()
1403 ah->opmode, in ar9003_hw_ani_cache_ini_regs()
1404 chan->channel); in ar9003_hw_ani_cache_ini_regs()
1407 iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH); in ar9003_hw_ani_cache_ini_regs()
1408 iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH); in ar9003_hw_ani_cache_ini_regs()
1409 iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR); in ar9003_hw_ani_cache_ini_regs()
1412 iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1413 iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1414 iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW); in ar9003_hw_ani_cache_ini_regs()
1417 iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH); in ar9003_hw_ani_cache_ini_regs()
1418 iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH); in ar9003_hw_ani_cache_ini_regs()
1419 iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1420 iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW); in ar9003_hw_ani_cache_ini_regs()
1421 iniDef->firstep = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1424 iniDef->firstepLow = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1427 iniDef->cycpwrThr1 = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1430 iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah, in ar9003_hw_ani_cache_ini_regs()
1435 aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL; in ar9003_hw_ani_cache_ini_regs()
1436 aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL; in ar9003_hw_ani_cache_ini_regs()
1437 aniState->ofdmWeakSigDetect = true; in ar9003_hw_ani_cache_ini_regs()
1438 aniState->mrcCCK = true; in ar9003_hw_ani_cache_ini_regs()
1453 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); in ar9003_hw_set_radar_params()
1454 radar_0 |= SM(conf->radar_rssi, AR_PHY_RADAR_0_RRSSI); in ar9003_hw_set_radar_params()
1455 radar_0 |= SM(conf->pulse_height, AR_PHY_RADAR_0_HEIGHT); in ar9003_hw_set_radar_params()
1456 radar_0 |= SM(conf->pulse_rssi, AR_PHY_RADAR_0_PRSSI); in ar9003_hw_set_radar_params()
1457 radar_0 |= SM(conf->pulse_inband, AR_PHY_RADAR_0_INBAND); in ar9003_hw_set_radar_params()
1464 radar_1 |= SM(conf->pulse_maxlen, AR_PHY_RADAR_1_MAXLEN); in ar9003_hw_set_radar_params()
1465 radar_1 |= SM(conf->pulse_inband_step, AR_PHY_RADAR_1_RELSTEP_THRESH); in ar9003_hw_set_radar_params()
1466 radar_1 |= SM(conf->radar_inband, AR_PHY_RADAR_1_RELPWR_THRESH); in ar9003_hw_set_radar_params()
1470 if (conf->ext_channel) in ar9003_hw_set_radar_params()
1476 REG_WRITE_ARRAY(&ah->ini_dfs, in ar9003_hw_set_radar_params()
1477 IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites); in ar9003_hw_set_radar_params()
1483 struct ath_hw_radar_conf *conf = &ah->radar_conf; in ar9003_hw_set_radar_conf()
1485 conf->fir_power = -28; in ar9003_hw_set_radar_conf()
1486 conf->radar_rssi = 0; in ar9003_hw_set_radar_conf()
1487 conf->pulse_height = 10; in ar9003_hw_set_radar_conf()
1488 conf->pulse_rssi = 15; in ar9003_hw_set_radar_conf()
1489 conf->pulse_inband = 8; in ar9003_hw_set_radar_conf()
1490 conf->pulse_maxlen = 255; in ar9003_hw_set_radar_conf()
1491 conf->pulse_inband_step = 12; in ar9003_hw_set_radar_conf()
1492 conf->radar_inband = 8; in ar9003_hw_set_radar_conf()
1501 antconf->main_lna_conf = (regval & AR_PHY_ANT_DIV_MAIN_LNACONF) >> in ar9003_hw_antdiv_comb_conf_get()
1503 antconf->alt_lna_conf = (regval & AR_PHY_ANT_DIV_ALT_LNACONF) >> in ar9003_hw_antdiv_comb_conf_get()
1505 antconf->fast_div_bias = (regval & AR_PHY_ANT_FAST_DIV_BIAS) >> in ar9003_hw_antdiv_comb_conf_get()
1509 antconf->lna1_lna2_switch_delta = -1; in ar9003_hw_antdiv_comb_conf_get()
1510 antconf->lna1_lna2_delta = -9; in ar9003_hw_antdiv_comb_conf_get()
1511 antconf->div_group = 1; in ar9003_hw_antdiv_comb_conf_get()
1513 antconf->lna1_lna2_switch_delta = -1; in ar9003_hw_antdiv_comb_conf_get()
1514 antconf->lna1_lna2_delta = -9; in ar9003_hw_antdiv_comb_conf_get()
1515 antconf->div_group = 2; in ar9003_hw_antdiv_comb_conf_get()
1517 antconf->lna1_lna2_switch_delta = 3; in ar9003_hw_antdiv_comb_conf_get()
1518 antconf->lna1_lna2_delta = -9; in ar9003_hw_antdiv_comb_conf_get()
1519 antconf->div_group = 3; in ar9003_hw_antdiv_comb_conf_get()
1521 antconf->lna1_lna2_switch_delta = -1; in ar9003_hw_antdiv_comb_conf_get()
1522 antconf->lna1_lna2_delta = -3; in ar9003_hw_antdiv_comb_conf_get()
1523 antconf->div_group = 0; in ar9003_hw_antdiv_comb_conf_get()
1538 regval |= ((antconf->main_lna_conf << AR_PHY_ANT_DIV_MAIN_LNACONF_S) in ar9003_hw_antdiv_comb_conf_set()
1540 regval |= ((antconf->alt_lna_conf << AR_PHY_ANT_DIV_ALT_LNACONF_S) in ar9003_hw_antdiv_comb_conf_set()
1542 regval |= ((antconf->fast_div_bias << AR_PHY_ANT_FAST_DIV_BIAS_S) in ar9003_hw_antdiv_comb_conf_set()
1544 regval |= ((antconf->main_gaintb << AR_PHY_ANT_DIV_MAIN_GAINTB_S) in ar9003_hw_antdiv_comb_conf_set()
1546 regval |= ((antconf->alt_gaintb << AR_PHY_ANT_DIV_ALT_GAINTB_S) in ar9003_hw_antdiv_comb_conf_set()
1556 struct ath9k_hw_capabilities *pCap = &ah->caps; in ar9003_hw_set_bt_ant_diversity()
1565 IS_CHAN_2GHZ(ah->curchan)); in ar9003_hw_set_bt_ant_diversity()
1568 regval |= ah->config.ant_ctrl_comm2g_switch_enable; in ar9003_hw_set_bt_ant_diversity()
1574 ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1); in ar9003_hw_set_bt_ant_diversity()
1608 if (pCap->hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB) { in ar9003_hw_set_bt_ant_diversity()
1678 if (modesIndex == ah->modes_index) { in ar9003_hw_fast_chan_change()
1683 ar9003_hw_prog_ini(ah, &ah->iniSOC[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1684 ar9003_hw_prog_ini(ah, &ah->iniMac[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1685 ar9003_hw_prog_ini(ah, &ah->iniBB[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1686 ar9003_hw_prog_ini(ah, &ah->iniRadio[ATH_INI_POST], modesIndex); in ar9003_hw_fast_chan_change()
1689 ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant, in ar9003_hw_fast_chan_change()
1692 REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites); in ar9003_hw_fast_chan_change()
1696 * CUS217 mix LNA mode. in ar9003_hw_fast_chan_change()
1699 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_core, in ar9003_hw_fast_chan_change()
1701 REG_WRITE_ARRAY(&ah->ini_modes_rxgain_bb_postamble, in ar9003_hw_fast_chan_change()
1711 REG_WRITE_ARRAY(&ah->iniModesFastClock, modesIndex, regWrites); in ar9003_hw_fast_chan_change()
1714 REG_WRITE_ARRAY(&ah->iniModesFastClock, 1, regWrites); in ar9003_hw_fast_chan_change()
1719 if (chan->channel == 2484) in ar9003_hw_fast_chan_change()
1720 ar9003_hw_prog_ini(ah, &ah->iniCckfirJapan2484, 1); in ar9003_hw_fast_chan_change()
1722 ah->modes_index = modesIndex; in ar9003_hw_fast_chan_change()
1735 if (!param->enabled) { in ar9003_hw_spectral_scan_config()
1748 count = param->count; in ar9003_hw_spectral_scan_config()
1749 if (param->endless) in ar9003_hw_spectral_scan_config()
1751 else if (param->count == 0) in ar9003_hw_spectral_scan_config()
1754 if (param->short_repeat) in ar9003_hw_spectral_scan_config()
1764 AR_PHY_SPECTRAL_SCAN_PERIOD, param->period); in ar9003_hw_spectral_scan_config()
1766 AR_PHY_SPECTRAL_SCAN_FFT_PERIOD, param->fft_period); in ar9003_hw_spectral_scan_config()
1782 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_spectral_scan_wait() local
1788 ath_err(common, "spectral scan wait failed\n"); in ar9003_hw_spectral_scan_wait()
1826 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1827 ah->tx_power[1] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1828 ah->tx_power[2] = min(rate_array[ALL_TARGET_LEGACY_1L_5L], in ar9003_hw_init_txpower_cck()
1830 ah->tx_power[3] = min(rate_array[ALL_TARGET_LEGACY_11L], in ar9003_hw_init_txpower_cck()
1841 j = ofdm2pwr[i - offset]; in ar9003_hw_init_txpower_ofdm()
1842 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ofdm()
1855 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1861 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1867 ah->tx_power[i] = rate_array[j]; in ar9003_hw_init_txpower_ht()
1875 memcpy(&ah->tx_power_stbc[ss_offset], &ah->tx_power[ss_offset], in ar9003_hw_init_txpower_stbc()
1877 memcpy(&ah->tx_power_stbc[ds_offset], &ah->tx_power[ds_offset], in ar9003_hw_init_txpower_stbc()
1879 memcpy(&ah->tx_power_stbc[ts_offset], &ah->tx_power[ts_offset], in ar9003_hw_init_txpower_stbc()
1931 priv_ops->rf_set_freq = ar9003_hw_set_channel; in ar9003_hw_attach_phy_ops()
1932 priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; in ar9003_hw_attach_phy_ops()
1936 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc; in ar9003_hw_attach_phy_ops()
1938 priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; in ar9003_hw_attach_phy_ops()
1940 priv_ops->set_channel_regs = ar9003_hw_set_channel_regs; in ar9003_hw_attach_phy_ops()
1941 priv_ops->init_bb = ar9003_hw_init_bb; in ar9003_hw_attach_phy_ops()
1942 priv_ops->process_ini = ar9003_hw_process_ini; in ar9003_hw_attach_phy_ops()
1943 priv_ops->set_rfmode = ar9003_hw_set_rfmode; in ar9003_hw_attach_phy_ops()
1944 priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive; in ar9003_hw_attach_phy_ops()
1945 priv_ops->set_delta_slope = ar9003_hw_set_delta_slope; in ar9003_hw_attach_phy_ops()
1946 priv_ops->rfbus_req = ar9003_hw_rfbus_req; in ar9003_hw_attach_phy_ops()
1947 priv_ops->rfbus_done = ar9003_hw_rfbus_done; in ar9003_hw_attach_phy_ops()
1948 priv_ops->ani_control = ar9003_hw_ani_control; in ar9003_hw_attach_phy_ops()
1949 priv_ops->do_getnf = ar9003_hw_do_getnf; in ar9003_hw_attach_phy_ops()
1950 priv_ops->ani_cache_ini_regs = ar9003_hw_ani_cache_ini_regs; in ar9003_hw_attach_phy_ops()
1951 priv_ops->set_radar_params = ar9003_hw_set_radar_params; in ar9003_hw_attach_phy_ops()
1952 priv_ops->fast_chan_change = ar9003_hw_fast_chan_change; in ar9003_hw_attach_phy_ops()
1954 ops->antdiv_comb_conf_get = ar9003_hw_antdiv_comb_conf_get; in ar9003_hw_attach_phy_ops()
1955 ops->antdiv_comb_conf_set = ar9003_hw_antdiv_comb_conf_set; in ar9003_hw_attach_phy_ops()
1956 ops->spectral_scan_config = ar9003_hw_spectral_scan_config; in ar9003_hw_attach_phy_ops()
1957 ops->spectral_scan_trigger = ar9003_hw_spectral_scan_trigger; in ar9003_hw_attach_phy_ops()
1958 ops->spectral_scan_wait = ar9003_hw_spectral_scan_wait; in ar9003_hw_attach_phy_ops()
1961 ops->set_bt_ant_diversity = ar9003_hw_set_bt_ant_diversity; in ar9003_hw_attach_phy_ops()
1963 ops->tx99_start = ar9003_hw_tx99_start; in ar9003_hw_attach_phy_ops()
1964 ops->tx99_stop = ar9003_hw_tx99_stop; in ar9003_hw_attach_phy_ops()
1965 ops->tx99_set_txpower = ar9003_hw_tx99_set_txpower; in ar9003_hw_attach_phy_ops()
1969 memcpy(ah->nf_regs, ar9300_cca_regs, sizeof(ah->nf_regs)); in ar9003_hw_attach_phy_ops()
1975 * 0x04000539: BB hang when operating in HT40 DFS Channel.
2002 switch(ah->bb_watchdog_last_status) { in ar9003_hw_bb_watchdog_check()
2037 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_config() local
2038 u32 idle_tmo_ms = ah->bb_watchdog_timeout_ms; in ar9003_hw_bb_watchdog_config()
2042 /* disable IRQ, disable chip-reset for BB panic */ in ar9003_hw_bb_watchdog_config()
2048 /* disable watchdog in non-IDLE mode, disable in IDLE mode */ in ar9003_hw_bb_watchdog_config()
2054 ath_dbg(common, RESET, "Disabled BB Watchdog\n"); in ar9003_hw_bb_watchdog_config()
2058 /* enable IRQ, disable chip-reset for BB watchdog */ in ar9003_hw_bb_watchdog_config()
2075 * be common for both 2 GHz and 5 GHz. in ar9003_hw_bb_watchdog_config()
2078 if (ah->curchan && IS_CHAN_HT40(ah->curchan)) in ar9003_hw_bb_watchdog_config()
2082 * enable watchdog in non-IDLE mode, disable in IDLE mode, in ar9003_hw_bb_watchdog_config()
2083 * set idle time-out. in ar9003_hw_bb_watchdog_config()
2090 ath_dbg(common, RESET, "Enabled BB Watchdog timeout (%u ms)\n", in ar9003_hw_bb_watchdog_config()
2100 ah->bb_watchdog_last_status = REG_READ(ah, AR_PHY_WATCHDOG_STATUS); in ar9003_hw_bb_watchdog_read()
2107 ah->bb_watchdog_last_status & ~AR_PHY_WATCHDOG_STATUS_CLR); in ar9003_hw_bb_watchdog_read()
2112 struct ath_common *common = ath9k_hw_common(ah); in ar9003_hw_bb_watchdog_dbg_info() local
2115 if (likely(!(common->debug_mask & ATH_DBG_RESET))) in ar9003_hw_bb_watchdog_dbg_info()
2118 status = ah->bb_watchdog_last_status; in ar9003_hw_bb_watchdog_dbg_info()
2119 ath_dbg(common, RESET, in ar9003_hw_bb_watchdog_dbg_info()
2121 ath_dbg(common, RESET, in ar9003_hw_bb_watchdog_dbg_info()
2133 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", in ar9003_hw_bb_watchdog_dbg_info()
2136 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n", in ar9003_hw_bb_watchdog_dbg_info()
2139 #define PCT(_field) (common->cc_survey._field * 100 / common->cc_survey.cycles) in ar9003_hw_bb_watchdog_dbg_info()
2140 if (common->cc_survey.cycles) in ar9003_hw_bb_watchdog_dbg_info()
2141 ath_dbg(common, RESET, in ar9003_hw_bb_watchdog_dbg_info()
2145 ath_dbg(common, RESET, "==== BB update: done ====\n\n"); in ar9003_hw_bb_watchdog_dbg_info()
2159 result = MS(ah->bb_watchdog_last_status, AR_PHY_WATCHDOG_RX_OFDM_SM); in ar9003_hw_disable_phy_restart()
2161 if ((result == 0xb) || ah->bb_hang_rx_ofdm) { in ar9003_hw_disable_phy_restart()
2162 ah->bb_hang_rx_ofdm = true; in ar9003_hw_disable_phy_restart()