Lines Matching +full:0 +full:x1ff00000
27 #define AR9300_11NA_OFDM_SHIFT 0
38 /* level: 0 1 2 3 4 5 6 7 8 */
39 { -4, -2, 0, 2, 4, 6, 8, 10, 12 }; /* lvl 0-8, default 2 */
42 /* level: 0 1 2 3 4 5 6 7 8 */
43 { -6, -4, -2, 0, 2, 4, 6, 8 }; /* lvl 0-7, default 3 */
138 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
142 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
146 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
151 u16 bMode, fracMode = 0, aModeRefSel = 0; in ar9003_hw_set_channel()
152 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; in ar9003_hw_set_channel()
169 chan_frac = (((freq * 4) % div) * 0x20000) / div; in ar9003_hw_set_channel()
174 chan_frac = (((freq * 2) % 75) * 0x20000) / 75; in ar9003_hw_set_channel()
189 chan_frac = ((freq % 75) * 0x20000) / 75; in ar9003_hw_set_channel()
197 bMode = 0; in ar9003_hw_set_channel()
202 aModeRefSel = 0; in ar9003_hw_set_channel()
203 loadSynthChannel = 0; in ar9003_hw_set_channel()
225 return 0; in ar9003_hw_set_channel()
242 int cur_bb_spur, negative = 0, cck_spur_freq; in ar9003_hw_spur_mitigate_mrc_cck()
254 if (spur_fbin_ptr[0] == 0) /* No spur */ in ar9003_hw_spur_mitigate_mrc_cck()
260 AR_PHY_GC_DYN2040_PRI_CH) == 0) in ar9003_hw_spur_mitigate_mrc_cck()
274 for (i = 0; i < max_spur_cnts; i++) { in ar9003_hw_spur_mitigate_mrc_cck()
275 if (AR_SREV_9462(ah) && (i == 0 || i == 3)) in ar9003_hw_spur_mitigate_mrc_cck()
278 negative = 0; in ar9003_hw_spur_mitigate_mrc_cck()
287 if (cur_bb_spur < 0) { in ar9003_hw_spur_mitigate_mrc_cck()
297 cck_spur_freq = cck_spur_freq & 0xfffff; in ar9003_hw_spur_mitigate_mrc_cck()
300 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7); in ar9003_hw_spur_mitigate_mrc_cck()
302 AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f); in ar9003_hw_spur_mitigate_mrc_cck()
305 0x2); in ar9003_hw_spur_mitigate_mrc_cck()
308 0x1); in ar9003_hw_spur_mitigate_mrc_cck()
318 AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5); in ar9003_hw_spur_mitigate_mrc_cck()
320 AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0); in ar9003_hw_spur_mitigate_mrc_cck()
322 AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0); in ar9003_hw_spur_mitigate_mrc_cck()
329 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0); in ar9003_hw_spur_ofdm_clear()
331 AR_PHY_TIMING11_SPUR_FREQ_SD, 0); in ar9003_hw_spur_ofdm_clear()
333 AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0); in ar9003_hw_spur_ofdm_clear()
335 AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0); in ar9003_hw_spur_ofdm_clear()
337 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0); in ar9003_hw_spur_ofdm_clear()
339 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0); in ar9003_hw_spur_ofdm_clear()
341 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0); in ar9003_hw_spur_ofdm_clear()
343 AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0); in ar9003_hw_spur_ofdm_clear()
345 AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0); in ar9003_hw_spur_ofdm_clear()
348 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0); in ar9003_hw_spur_ofdm_clear()
350 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0); in ar9003_hw_spur_ofdm_clear()
352 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0); in ar9003_hw_spur_ofdm_clear()
354 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0); in ar9003_hw_spur_ofdm_clear()
356 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0); in ar9003_hw_spur_ofdm_clear()
358 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0); in ar9003_hw_spur_ofdm_clear()
360 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0); in ar9003_hw_spur_ofdm_clear()
362 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0); in ar9003_hw_spur_ofdm_clear()
364 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0); in ar9003_hw_spur_ofdm_clear()
366 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0); in ar9003_hw_spur_ofdm_clear()
377 int mask_index = 0; in ar9003_hw_spur_ofdm()
381 AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1); in ar9003_hw_spur_ofdm()
389 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1); in ar9003_hw_spur_ofdm()
393 AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1); in ar9003_hw_spur_ofdm()
396 AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1); in ar9003_hw_spur_ofdm()
404 AR_PHY_MODE_DYNAMIC) == 0x1) in ar9003_hw_spur_ofdm()
409 if (mask_index < 0) in ar9003_hw_spur_ofdm()
412 mask_index = mask_index & 0x7f; in ar9003_hw_spur_ofdm()
415 AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1); in ar9003_hw_spur_ofdm()
417 AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1); in ar9003_hw_spur_ofdm()
419 AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1); in ar9003_hw_spur_ofdm()
427 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc); in ar9003_hw_spur_ofdm()
429 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc); in ar9003_hw_spur_ofdm()
431 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); in ar9003_hw_spur_ofdm()
433 AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff); in ar9003_hw_spur_ofdm()
439 int mask_index = 0; in ar9003_hw_spur_ofdm_9565()
442 if (mask_index < 0) in ar9003_hw_spur_ofdm_9565()
445 mask_index = mask_index & 0x7f; in ar9003_hw_spur_ofdm_9565()
460 AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_B, 0xe); in ar9003_hw_spur_ofdm_9565()
462 AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_B, 0xe); in ar9003_hw_spur_ofdm_9565()
466 AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0); in ar9003_hw_spur_ofdm_9565()
475 int spur_freq_sd = 0; in ar9003_hw_spur_ofdm_work()
476 int spur_subchannel_sd = 0; in ar9003_hw_spur_ofdm_work()
477 int spur_delta_phase = 0; in ar9003_hw_spur_ofdm_work()
480 if (freq_offset < 0) { in ar9003_hw_spur_ofdm_work()
482 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) in ar9003_hw_spur_ofdm_work()
485 spur_subchannel_sd = 0; in ar9003_hw_spur_ofdm_work()
491 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) in ar9003_hw_spur_ofdm_work()
492 spur_subchannel_sd = 0; in ar9003_hw_spur_ofdm_work()
503 spur_subchannel_sd = 0; in ar9003_hw_spur_ofdm_work()
508 spur_freq_sd = spur_freq_sd & 0x3ff; in ar9003_hw_spur_ofdm_work()
509 spur_delta_phase = spur_delta_phase & 0xfffff; in ar9003_hw_spur_ofdm_work()
525 int freq_offset = 0; in ar9003_hw_spur_mitigate_ofdm()
529 if (spur_fbin_ptr[0] == 0) in ar9003_hw_spur_mitigate_ofdm()
535 AR_PHY_GC_DYN2040_PRI_CH) == 0x0) in ar9003_hw_spur_mitigate_ofdm()
546 for (i = 0; i < AR_EEPROM_MODAL_SPURS && spur_fbin_ptr[i]; i++) { in ar9003_hw_spur_mitigate_ofdm()
581 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); in ar9003_hw_compute_pll_control_soc()
584 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
586 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
588 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); in ar9003_hw_compute_pll_control_soc()
598 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); in ar9003_hw_compute_pll_control()
601 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
603 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
605 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); in ar9003_hw_compute_pll_control()
614 u32 enableDacFifo = 0; in ar9003_hw_set_channel_regs()
647 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S); in ar9003_hw_set_channel_regs()
676 if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && (tx == 0x7)) in ar9003_hw_set_chain_masks()
729 REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x17c << 1); in ar9003_hw_override_ini()
730 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); in ar9003_hw_override_ini()
731 REG_WRITE(ah, AR_SLP32_INC, 0x0001e7ae); in ar9003_hw_override_ini()
733 REG_WRITE(ah, AR_RTC_DERIVED_CLK(ah), 0x261 << 1); in ar9003_hw_override_ini()
734 REG_WRITE(ah, AR_SLP32_MODE, 0x0010f400); in ar9003_hw_override_ini()
735 REG_WRITE(ah, AR_SLP32_INC, 0x0001e800); in ar9003_hw_override_ini()
745 unsigned int i, regWrites = 0; in ar9003_hw_prog_ini()
759 for (i = 0; i < iniArr->ia_rows; i++) { in ar9003_hw_prog_ini()
760 u32 reg = INI_RA(iniArr, i, 0); in ar9003_hw_prog_ini()
804 return 0; in ar9561_hw_get_modes_txgain_index()
812 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); in ar9003_doubler_fix()
815 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); in ar9003_doubler_fix()
818 1 << AR_PHY_65NM_CH0_RXTX2_SYNTHOVR_MASK_S, 0); in ar9003_doubler_fix()
841 AR_PHY_65NM_CH0_SYNTH12_VREFMUL3, 0xf); in ar9003_doubler_fix()
843 REG_RMW(ah, AR_PHY_65NM_CH0_RXTX2, 0, in ar9003_doubler_fix()
846 REG_RMW(ah, AR_PHY_65NM_CH1_RXTX2, 0, in ar9003_doubler_fix()
849 REG_RMW(ah, AR_PHY_65NM_CH2_RXTX2, 0, in ar9003_doubler_fix()
858 unsigned int regWrites = 0, i; in ar9003_hw_process_ini()
869 for (i = 0; i < ATH_INI_NUM_SPLIT; i++) { in ar9003_hw_process_ini()
912 if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) in ar9003_hw_process_ini()
955 AR_PHY_FLC_PWR_THRESH, 0); in ar9003_hw_process_ini()
964 return 0; in ar9003_hw_process_ini()
970 u32 rfMode = 0; in ar9003_hw_set_rfmode()
999 u32 clockMhzScaled = 0x64000000; in ar9003_hw_set_delta_slope()
1059 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0); in ar9003_hw_rfbus_done()
1081 * on == 0 means ofdm weak signal detection is OFF in ar9003_hw_ani_control()
1082 * on == 0 means more noise imm in ar9003_hw_ani_control()
1084 u32 on = param ? 1 : 0; in ar9003_hw_ani_control()
1295 * is_on == 0 means MRC CCK is OFF (more noise imm) in ar9003_hw_ani_control()
1297 bool is_on = param ? 1 : 0; in ar9003_hw_ani_control()
1339 #define AR_PHY_CH_MINCCA_PWR 0x1FF00000 in ar9003_hw_do_getnf()
1341 #define AR_PHY_CH_EXT_MINCCA_PWR 0x01FF0000 in ar9003_hw_do_getnf()
1347 for (i = 0; i < AR9300_MAX_CHAINS; i++) { in ar9003_hw_do_getnf()
1444 unsigned int regWrites = 0; in ar9003_hw_set_radar_params()
1445 u32 radar_0 = 0, radar_1; in ar9003_hw_set_radar_params()
1486 conf->radar_rssi = 0; in ar9003_hw_set_radar_conf()
1523 antconf->div_group = 0; in ar9003_hw_antdiv_comb_conf_get()
1582 regval |= (ant_div_ctl1 & 0x3f) << AR_ANT_DIV_CTRL_ALL_S; in ar9003_hw_set_bt_ant_diversity()
1591 regval |= ((ant_div_ctl1 >> 6) & 0x1) << AR_PHY_ANT_DIV_LNADIV_S; in ar9003_hw_set_bt_ant_diversity()
1602 regval |= ((ant_div_ctl1 >> 7) & 0x1) << AR_FAST_DIV_ENABLE_S; in ar9003_hw_set_bt_ant_diversity()
1668 unsigned int regWrites = 0; in ar9003_hw_fast_chan_change()
1727 return 0; in ar9003_hw_fast_chan_change()
1744 /* on AR93xx and newer, count = 0 will make the chip send in ar9003_hw_spectral_scan_config()
1750 count = 0; in ar9003_hw_spectral_scan_config()
1751 else if (param->count == 0) in ar9003_hw_spectral_scan_config()
1787 0, AH_WAIT_TIMEOUT)) { in ar9003_hw_spectral_scan_wait()
1798 REG_WRITE(ah, AR_DLCL_IFS(qnum), 0); in ar9003_hw_tx99_start()
1801 REG_WRITE(ah, AR_TIME_OUT, 0x00000400); in ar9003_hw_tx99_start()
1802 REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff); in ar9003_hw_tx99_start()
1814 static u8 p_pwr_array[ar9300RateSize] = { 0 }; in ar9003_hw_tx99_set_txpower()
1818 for (i = 0; i < ar9300RateSize; i++) in ar9003_hw_tx99_set_txpower()
1826 ah->tx_power[0] = rate_array[ALL_TARGET_LEGACY_1L_5L]; in ar9003_hw_init_txpower_cck()
1850 int i, j, mcs_idx = 0; in ar9003_hw_init_txpower_ht()
1975 * 0x04000539: BB hang when operating in HT40 DFS Channel.
1979 * 0x1300000a: Related to CAC deafness.
1982 * 0x0400000a: Related to CAC deafness.
1985 * 0x04000b09: RX state machine gets into an illegal state
1990 * 0x04000409: Packet stuck on receive.
2003 case 0x04000539: in ar9003_hw_bb_watchdog_check()
2006 val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR); in ar9003_hw_bb_watchdog_check()
2015 case 0x1300000a: in ar9003_hw_bb_watchdog_check()
2017 case 0x0400000a: in ar9003_hw_bb_watchdog_check()
2018 case 0x04000b09: in ar9003_hw_bb_watchdog_check()
2020 case 0x04000409: in ar9003_hw_bb_watchdog_check()
2104 * sure we write 0 to the watchdog status bit. in ar9003_hw_bb_watchdog_read()
2120 "\n==== BB update: BB status=0x%08x ====\n", status); in ar9003_hw_bb_watchdog_dbg_info()
2133 ath_dbg(common, RESET, "** BB WD cntl: cntl1=0x%08x cntl2=0x%08x **\n", in ar9003_hw_bb_watchdog_dbg_info()
2136 ath_dbg(common, RESET, "** BB mode: BB_gen_controls=0x%08x **\n", in ar9003_hw_bb_watchdog_dbg_info()
2155 * gets into a state 0xb and if phy_restart happens in that in ar9003_hw_disable_phy_restart()
2156 * state, BB would go hang. If RXSM is in 0xb state after in ar9003_hw_disable_phy_restart()
2161 if ((result == 0xb) || ah->bb_hang_rx_ofdm) { in ar9003_hw_disable_phy_restart()