59  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
63  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
68 	u16 bMode, fracMode, aModeRefSel = 0;  in ar9002_hw_set_channel()
69 	u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;  in ar9002_hw_set_channel()
77 	reg32 &= 0xc0000000;  in ar9002_hw_set_channel()
81 		int regWrites = 0;  in ar9002_hw_set_channel()
85 		aModeRefSel = 0;  in ar9002_hw_set_channel()
109 		bMode = 0;  in ar9002_hw_set_channel()
110 		fracMode = 0;  in ar9002_hw_set_channel()
113 		case 0:  in ar9002_hw_set_channel()
115 				aModeRefSel = 0;  in ar9002_hw_set_channel()
116 			else if ((freq % 20) == 0)  in ar9002_hw_set_channel()
118 			else if ((freq % 10) == 0)  in ar9002_hw_set_channel()
125 			aModeRefSel = 0;  in ar9002_hw_set_channel()
143 			channelSel = ndiv & 0x1ff;  in ar9002_hw_set_channel()
144 			channelFrac = (ndiv & 0xfffffe00) * 2;  in ar9002_hw_set_channel()
157 	return 0;  in ar9002_hw_set_channel()
188 	for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {  in ar9002_hw_spur_mitigate()
225 	tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));  in ar9002_hw_spur_mitigate()
233 	REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);  in ar9002_hw_spur_mitigate()
243 		if (bb_spur < 0) {  in ar9002_hw_spur_mitigate()
247 			spur_subchannel_sd = 0;  in ar9002_hw_spur_mitigate()
251 		spur_subchannel_sd = 0;  in ar9002_hw_spur_mitigate()
265 	spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;  in ar9002_hw_spur_mitigate()
296 		for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)  in ar9002_olc_init()
300 		ah->PDADCdelta = 0;  in ar9002_olc_init()
308 	int pll_div = 0x2c;  in ar9002_hw_compute_pll_control()
314 			pll_div = 0x50;  in ar9002_hw_compute_pll_control()
316 			pll_div = 0x28;  in ar9002_hw_compute_pll_control()
324 		pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);  in ar9002_hw_compute_pll_control()
326 		pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);  in ar9002_hw_compute_pll_control()
337 	nfarray[0] = sign_extend32(nf, 8);  in ar9002_hw_do_getnf()
392 	antconf->div_group = 0;  in ar9002_hw_antdiv_comb_conf_get()
433 		REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000);  in ar9002_hw_set_bt_ant_diversity()
451 		REG_WRITE(ah, AR_PHY_SWITCH_COM, 0);  in ar9002_hw_set_bt_ant_diversity()
452 		REG_RMW(ah, AR_PHY_SWITCH_CHAIN_0, 0, 0xf0000000);  in ar9002_hw_set_bt_ant_diversity()
508 			count = 0x80;  in ar9002_hw_spectral_scan_config()
510 			count = 0;  in ar9002_hw_spectral_scan_config()
511 	} else if (count & 0x80)  in ar9002_hw_spectral_scan_config()
512 		count = 0x7f;  in ar9002_hw_spectral_scan_config()
549 			   0, AH_WAIT_TIMEOUT)) {  in ar9002_hw_spectral_scan_wait()
557 	REG_SET_BIT(ah, 0x9864, 0x7f000);  in ar9002_hw_tx99_start()
558 	REG_SET_BIT(ah, 0x9924, 0x7f00fe);  in ar9002_hw_tx99_start()
561 	REG_WRITE(ah, AR_DLCL_IFS(qnum), 0);  in ar9002_hw_tx99_start()
564 	REG_WRITE(ah, AR_D_FPCTL, 0x10|qnum);  in ar9002_hw_tx99_start()
565 	REG_WRITE(ah, AR_TIME_OUT, 0x00000400);  in ar9002_hw_tx99_start()
566 	REG_WRITE(ah, AR_DRETRY_LIMIT(qnum), 0xffffffff);  in ar9002_hw_tx99_start()