Lines Matching +full:0 +full:x001fffff
26 #define AR6004_BOARD_EXT_DATA_SZ 0
28 #define RESET_CONTROL_ADDRESS 0x00004000
29 #define RESET_CONTROL_COLD_RST 0x00000100
30 #define RESET_CONTROL_MBOX_RST 0x00000004
32 #define CPU_CLOCK_STANDARD_S 0
33 #define CPU_CLOCK_STANDARD 0x00000003
34 #define CPU_CLOCK_ADDRESS 0x00000020
36 #define CLOCK_CONTROL_ADDRESS 0x00000028
38 #define CLOCK_CONTROL_LF_CLK32 0x00000004
40 #define SYSTEM_SLEEP_ADDRESS 0x000000c4
41 #define SYSTEM_SLEEP_DISABLE_S 0
42 #define SYSTEM_SLEEP_DISABLE 0x00000001
44 #define LPO_CAL_ADDRESS 0x000000e0
46 #define LPO_CAL_ENABLE 0x00100000
48 #define GPIO_PIN9_ADDRESS 0x0000004c
49 #define GPIO_PIN10_ADDRESS 0x00000050
50 #define GPIO_PIN11_ADDRESS 0x00000054
51 #define GPIO_PIN12_ADDRESS 0x00000058
52 #define GPIO_PIN13_ADDRESS 0x0000005c
54 #define HOST_INT_STATUS_ADDRESS 0x00000400
56 #define HOST_INT_STATUS_ERROR 0x00000080
59 #define HOST_INT_STATUS_CPU 0x00000040
62 #define HOST_INT_STATUS_COUNTER 0x00000010
64 #define CPU_INT_STATUS_ADDRESS 0x00000401
66 #define ERROR_INT_STATUS_ADDRESS 0x00000402
68 #define ERROR_INT_STATUS_WAKEUP 0x00000004
71 #define ERROR_INT_STATUS_RX_UNDERFLOW 0x00000002
73 #define ERROR_INT_STATUS_TX_OVERFLOW_S 0
74 #define ERROR_INT_STATUS_TX_OVERFLOW 0x00000001
76 #define COUNTER_INT_STATUS_ADDRESS 0x00000403
77 #define COUNTER_INT_STATUS_COUNTER_S 0
78 #define COUNTER_INT_STATUS_COUNTER 0x000000ff
80 #define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
82 #define INT_STATUS_ENABLE_ADDRESS 0x00000418
84 #define INT_STATUS_ENABLE_ERROR 0x00000080
87 #define INT_STATUS_ENABLE_CPU 0x00000040
90 #define INT_STATUS_ENABLE_INT 0x00000020
92 #define INT_STATUS_ENABLE_COUNTER 0x00000010
94 #define INT_STATUS_ENABLE_MBOX_DATA_S 0
95 #define INT_STATUS_ENABLE_MBOX_DATA 0x0000000f
97 #define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
98 #define CPU_INT_STATUS_ENABLE_BIT_S 0
99 #define CPU_INT_STATUS_ENABLE_BIT 0x000000ff
101 #define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
103 #define ERROR_STATUS_ENABLE_RX_UNDERFLOW 0x00000002
105 #define ERROR_STATUS_ENABLE_TX_OVERFLOW_S 0
106 #define ERROR_STATUS_ENABLE_TX_OVERFLOW 0x00000001
108 #define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
109 #define COUNTER_INT_STATUS_ENABLE_BIT_S 0
110 #define COUNTER_INT_STATUS_ENABLE_BIT 0x000000ff
112 #define COUNT_ADDRESS 0x00000420
114 #define COUNT_DEC_ADDRESS 0x00000440
116 #define WINDOW_DATA_ADDRESS 0x00000474
117 #define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
118 #define WINDOW_READ_ADDR_ADDRESS 0x0000047c
119 #define CPU_DBG_SEL_ADDRESS 0x00000483
120 #define CPU_DBG_ADDRESS 0x00000484
122 #define LOCAL_SCRATCH_ADDRESS 0x000000c0
123 #define ATH6KL_OPTION_SLEEP_DISABLE 0x08
125 #define RTC_BASE_ADDRESS 0x00004000
126 #define GPIO_BASE_ADDRESS 0x00014000
127 #define MBOX_BASE_ADDRESS 0x00018000
128 #define ANALOG_INTF_BASE_ADDRESS 0x0001c000
131 #define ATH6KL_ANALOG_PLL_REGISTER (ANALOG_INTF_BASE_ADDRESS + 0x284)
144 #define ATH6KL_AR6003_HI_START_ADDR 0x00540600
145 #define ATH6KL_AR6004_HI_START_ADDR 0x00400800
164 u32 hi_app_host_interest; /* 0x00 */
167 u32 hi_failure_state; /* 0x04 */
170 u32 hi_dbglog_hdr; /* 0x08 */
172 u32 hi_unused1; /* 0x0c */
178 u32 hi_option_flag; /* 0x10 */
184 u32 hi_serial_enable; /* 0x14 */
187 u32 hi_dset_list_head; /* 0x18 */
190 u32 hi_app_start; /* 0x1c */
193 u32 hi_skip_clock_init; /* 0x20 */
194 u32 hi_core_clock_setting; /* 0x24 */
195 u32 hi_cpu_clock_setting; /* 0x28 */
196 u32 hi_system_sleep_setting; /* 0x2c */
197 u32 hi_xtal_control_setting; /* 0x30 */
198 u32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
199 u32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
200 u32 hi_ref_voltage_trim_setting; /* 0x3c */
201 u32 hi_clock_info; /* 0x40 */
209 u32 hi_bank0_addr_value; /* 0x44 */
210 u32 hi_bank0_read_value; /* 0x48 */
211 u32 hi_bank0_write_value; /* 0x4c */
212 u32 hi_bank0_config_value; /* 0x50 */
215 u32 hi_board_data; /* 0x54 */
216 u32 hi_board_data_initialized; /* 0x58 */
218 u32 hi_dset_ram_index_tbl; /* 0x5c */
220 u32 hi_desired_baud_rate; /* 0x60 */
221 u32 hi_dbglog_config; /* 0x64 */
222 u32 hi_end_ram_reserve_sz; /* 0x68 */
223 u32 hi_mbox_io_block_sz; /* 0x6c */
225 u32 hi_num_bpatch_streams; /* 0x70 -- unused */
226 u32 hi_mbox_isr_yield_limit; /* 0x74 */
228 u32 hi_refclk_hz; /* 0x78 */
229 u32 hi_ext_clk_detected; /* 0x7c */
230 u32 hi_dbg_uart_txpin; /* 0x80 */
231 u32 hi_dbg_uart_rxpin; /* 0x84 */
232 u32 hi_hci_uart_baud; /* 0x88 */
233 u32 hi_hci_uart_pin_assignments; /* 0x8C */
235 * NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts
238 u32 hi_hci_uart_baud_scale_val; /* 0x90 */
239 u32 hi_hci_uart_baud_step_val; /* 0x94 */
241 u32 hi_allocram_start; /* 0x98 */
242 u32 hi_allocram_sz; /* 0x9c */
243 u32 hi_hci_bridge_flags; /* 0xa0 */
244 u32 hi_hci_uart_support_pins; /* 0xa4 */
246 * NOTE: byte [0] = RESET pin (bit 7 is polarity),
249 u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
251 * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
256 u32 hi_board_ext_data; /* 0xac */
257 u32 hi_board_ext_data_config; /* 0xb0 */
260 * Bit [0] : valid
268 u32 hi_reset_flag; /* 0xb4 */
270 u32 hi_reset_flag_valid; /* 0xb8 */
271 u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
273 * 0xbc - [31:0]: idle timeout in ms
276 u32 hi_acs_flags; /* 0xc0 */
277 u32 hi_console_flags; /* 0xc4 */
278 u32 hi_nvram_state; /* 0xc8 */
279 u32 hi_option_flag2; /* 0xcc */
282 u32 hi_sw_version_override; /* 0xd0 */
283 u32 hi_abi_version_override; /* 0xd4 */
289 u32 hi_hp_rx_traffic_ratio; /* 0xd8 */
292 u32 hi_test_apps_related; /* 0xdc */
294 u32 hi_ota_testscript; /* 0xe0 */
296 u32 hi_cal_data; /* 0xe4 */
298 u32 hi_pktlog_num_buffers; /* 0xe8 */
306 #define HI_OPTION_FW_MODE_IBSS 0x0
307 #define HI_OPTION_FW_MODE_BSS_STA 0x1
308 #define HI_OPTION_FW_MODE_AP 0x2
310 #define HI_OPTION_FW_SUBMODE_NONE 0x0
311 #define HI_OPTION_FW_SUBMODE_P2PDEV 0x1
312 #define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2
313 #define HI_OPTION_FW_SUBMODE_P2PGO 0x3
315 #define HI_OPTION_NUM_DEV_SHIFT 0x9
317 #define HI_OPTION_FW_BRIDGE_SHIFT 0x04
322 | MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0|
326 #define HI_OPTION_FW_MODE_BITS 0x2
327 #define HI_OPTION_FW_MODE_SHIFT 0xC
329 #define HI_OPTION_FW_SUBMODE_BITS 0x2
330 #define HI_OPTION_FW_SUBMODE_SHIFT 0x14
333 #define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
338 (((target_type) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : 0))