Lines Matching refs:ath5k_hw_reg_write
257 ath5k_hw_reg_write(ah, usec_reg, AR5K_USEC); in ath5k_hw_init_core_clock()
299 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR); in ath5k_hw_set_sleep_clock()
308 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING); in ath5k_hw_set_sleep_clock()
313 ath5k_hw_reg_write(ah, 0x26, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
314 ath5k_hw_reg_write(ah, 0x0d, AR5K_PHY_SCAL); in ath5k_hw_set_sleep_clock()
315 ath5k_hw_reg_write(ah, 0x07, AR5K_PHY_SCLOCK); in ath5k_hw_set_sleep_clock()
316 ath5k_hw_reg_write(ah, 0x3f, AR5K_PHY_SDELAY); in ath5k_hw_set_sleep_clock()
320 ath5k_hw_reg_write(ah, 0x0a, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
321 ath5k_hw_reg_write(ah, 0x0c, AR5K_PHY_SCAL); in ath5k_hw_set_sleep_clock()
322 ath5k_hw_reg_write(ah, 0x03, AR5K_PHY_SCLOCK); in ath5k_hw_set_sleep_clock()
323 ath5k_hw_reg_write(ah, 0x20, AR5K_PHY_SDELAY); in ath5k_hw_set_sleep_clock()
343 ath5k_hw_reg_write(ah, 0x1f, AR5K_PHY_SCR); in ath5k_hw_set_sleep_clock()
344 ath5k_hw_reg_write(ah, AR5K_PHY_SLMT_32MHZ, AR5K_PHY_SLMT); in ath5k_hw_set_sleep_clock()
352 ath5k_hw_reg_write(ah, scal, AR5K_PHY_SCAL); in ath5k_hw_set_sleep_clock()
354 ath5k_hw_reg_write(ah, AR5K_PHY_SCLOCK_32MHZ, AR5K_PHY_SCLOCK); in ath5k_hw_set_sleep_clock()
355 ath5k_hw_reg_write(ah, AR5K_PHY_SDELAY_32MHZ, AR5K_PHY_SDELAY); in ath5k_hw_set_sleep_clock()
364 ath5k_hw_reg_write(ah, spending, AR5K_PHY_SPENDING); in ath5k_hw_set_sleep_clock()
408 ath5k_hw_reg_write(ah, val, AR5K_RESET_CTL); in ath5k_hw_nic_reset()
431 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG); in ath5k_hw_nic_reset()
493 ath5k_hw_reg_write(ah, AR5K_INIT_CFG, AR5K_CFG); in ath5k_hw_wisoc_reset()
528 ath5k_hw_reg_write(ah, in ath5k_hw_set_power_mode()
538 ath5k_hw_reg_write(ah, AR5K_SLEEP_CTL_SLE_SLP, in ath5k_hw_set_power_mode()
562 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE, in ath5k_hw_set_power_mode()
574 ath5k_hw_reg_write(ah, data | AR5K_SLEEP_CTL_SLE_WAKE, in ath5k_hw_set_power_mode()
589 ath5k_hw_reg_write(ah, staid, AR5K_STA_ID1); in ath5k_hw_set_power_mode()
811 ath5k_hw_reg_write(ah, AR5K_PHY_TURBO_MODE, in ath5k_hw_nic_wakeup()
819 ath5k_hw_reg_write(ah, clock, AR5K_PHY_PLL); in ath5k_hw_nic_wakeup()
824 ath5k_hw_reg_write(ah, mode, AR5K_PHY_MODE); in ath5k_hw_nic_wakeup()
825 ath5k_hw_reg_write(ah, turbo, AR5K_PHY_TURBO); in ath5k_hw_nic_wakeup()
855 ath5k_hw_reg_write(ah, in ath5k_hw_tweak_initval_settings()
874 ath5k_hw_reg_write(ah, 0x0000000f, AR5K_SEQ_MASK); in ath5k_hw_tweak_initval_settings()
879 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BLUETOOTH); in ath5k_hw_tweak_initval_settings()
898 ath5k_hw_reg_write(ah, fast_adc, in ath5k_hw_tweak_initval_settings()
907 ath5k_hw_reg_write(ah, AR5K_PHY_CCKTXCTL_WORLD, in ath5k_hw_tweak_initval_settings()
913 ath5k_hw_reg_write(ah, data, AR5K_PHY_FRAME_CTL); in ath5k_hw_tweak_initval_settings()
918 ath5k_hw_reg_write(ah, 0, AR5K_QCUDCU_CLKGT); in ath5k_hw_tweak_initval_settings()
920 ath5k_hw_reg_write(ah, AR5K_PHY_SCAL_32MHZ_5311, in ath5k_hw_tweak_initval_settings()
947 ath5k_hw_reg_write(ah, in ath5k_hw_tweak_initval_settings()
962 ath5k_hw_reg_write(ah, (AR5K_PHY_FRAME_CTL_INI | 0x1020), in ath5k_hw_tweak_initval_settings()
1002 ath5k_hw_reg_write(ah, in ath5k_hw_commit_eeprom_settings()
1009 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TX_PWR_ADJ); in ath5k_hw_commit_eeprom_settings()
1023 ath5k_hw_reg_write(ah, in ath5k_hw_commit_eeprom_settings()
1081 ath5k_hw_reg_write(ah, in ath5k_hw_commit_eeprom_settings()
1122 ath5k_hw_reg_write(ah, 0, AR5K_PHY_HEAVY_CLIP_ENABLE); in ath5k_hw_commit_eeprom_settings()
1280 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0)); in ath5k_hw_reset()
1282 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ | 0x40, in ath5k_hw_reset()
1312 ath5k_hw_reg_write(ah, s_seq[i], in ath5k_hw_reset()
1315 ath5k_hw_reg_write(ah, s_seq[0], in ath5k_hw_reset()
1320 ath5k_hw_reg_write(ah, tsf_up, AR5K_TSF_U32); in ath5k_hw_reset()
1321 ath5k_hw_reg_write(ah, tsf_lo, AR5K_TSF_L32); in ath5k_hw_reset()
1329 ath5k_hw_reg_write(ah, s_led[1], AR5K_GPIOCR); in ath5k_hw_reset()
1330 ath5k_hw_reg_write(ah, s_led[2], AR5K_GPIODO); in ath5k_hw_reset()