Lines Matching +full:phy +full:- +full:reset +full:- +full:duration
2 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
3 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
4 * Copyright (c) 2007-2008 Michael Taylor <mike.taylor@apprion.com>
28 * 5210 - http://nova.stanford.edu/~bbaas/ps/isscc2002_slides.pdf
30 * 5211 - http://www.hotchips.org/archives/hc14/3_Tue/16_mcfarland.pdf
33 * Atheros's ART program (Atheros Radio Test), on ath9k, on legacy-hal
42 * AR5210-Specific TXDP registers
46 #define AR5K_NOQCU_TXDP0 0x0000 /* Queue 0 - data */
47 #define AR5K_NOQCU_TXDP1 0x0004 /* Queue 1 - beacons */
70 #define AR5K_CFG_SWTD 0x00000001 /* Byte-swap TX descriptor (for big endian archs) */
71 #define AR5K_CFG_SWTB 0x00000002 /* Byte-swap TX buffer */
72 #define AR5K_CFG_SWRD 0x00000004 /* Byte-swap RX descriptor */
73 #define AR5K_CFG_SWRB 0x00000008 /* Byte-swap RX buffer */
74 #define AR5K_CFG_SWRG 0x00000010 /* Byte-swap Register access */
75 #define AR5K_CFG_IBSS 0x00000020 /* 0-BSS, 1-IBSS [5211+] */
96 * and first RTS duration register on 5211
104 #define AR5K_BCR_ADHOC 0x00000001 /* Ad-Hoc mode */
111 * First RTS duration register [5211]
114 #define AR5K_RTSD0_6 0x000000ff /* 6Mb RTS duration mask (?) */
115 #define AR5K_RTSD0_6_S 0 /* 6Mb RTS duration shift (?) */
126 * and second RTS duration register on 5211
135 * So SNAPPEDBCRVALID should also stand for "snapped BCR -values- valid", so i
144 #define AR5K_BSR_SNPADHOC 0x00000100 /* Ad-hoc mode set (?) */
152 * Second RTS duration register [5211]
198 #define AR5K_RXCFG_ZLFDMA 0x00000008 /* Enable Zero-length frame DMA */
254 * (reserved0-3)
270 * (reserved4-5)
285 * the logical OR from per-queue interrupt bits found on SISR registers
300 * NOTE: We don't have per-queue info for this
301 * one, but we can enable it per-queue through
307 #define AR5K_ISR_RXPHY 0x00004000 /* PHY error */
336 * Secondary status registers [5211+] (0 - 4)
338 * These give the status for each QCU, only QCUs 0-9 are
378 * Shadow read-and-clear interrupt status registers [5211+]
409 #define AR5K_IMR_RXPHY 0x00004000 /* PHY error*/
430 * Secondary interrupt mask registers [5211+] (0 - 4)
469 * DMA Debug registers 0-7
470 * 0xe0 - 0xfc
530 #define AR5K_CCFG_CCU_INIT 0x00100200 /* Initial value during reset */
545 * Card has 12 TX Queues but i see that only 0-9 are used (?)
547 * TXDP at addresses 0x0800 - 0x082c, a CBR (Constant Bit Rate)
548 * configuration register (0x08c0 - 0x08ec), a ready time configuration
549 * register (0x0900 - 0x092c), a misc configuration register (0x09c0 -
550 * 0x09ec) and a status register (0x0a00 - 0x0a2c). We also have some
567 #define AR5K_QCU_TXDP_BASE 0x0800 /* Register Address - Queue0 TXDP */
587 #define AR5K_QCU_CBRCFG_BASE 0x08c0 /* Register Address - Queue0 CBRCFG */
597 #define AR5K_QCU_RDYTIMECFG_BASE 0x0900 /* Register Address - Queue0 RDYTIMECFG */
606 #define AR5K_QCU_ONESHOTARM_SET 0x0940 /* Register Address -QCU "one shot arm set (?)" */
612 #define AR5K_QCU_ONESHOTARM_CLEAR 0x0980 /* Register Address -QCU "one shot arm clear (?)" */
618 #define AR5K_QCU_MISC_BASE 0x09c0 /* Register Address -Queue0 MISC */
630 #define AR5K_QCU_MISC_RDY_VEOL_POLICY 0x00000200 /* TXE reset when RDYTIME expired or VEOL */
631 #define AR5K_QCU_MISC_CBR_RESET_CNT 0x00000400 /* CBR threshold (counter) reset */
640 #define AR5K_QCU_STS_BASE 0x0a00 /* Register Address - Queue0 STS */
673 * (0x1000 - 0x102c), a local-IFS settings register (0x1040 - 0x106c),
674 * a retry limit register (0x1080 - 0x10ac), a channel time register
675 * (0x10c0 - 0x10ec), a misc-settings register (0x1100 - 0x112c) and
676 * a sequence number register (0x1140 - 0x116c). It seems that "global"
685 #define AR5K_DCU_QCUMASK_BASE 0x1000 /* Register Address -Queue0 DCU_QCUMASK */
692 #define AR5K_DCU_LCL_IFS_BASE 0x1040 /* Register Address -Queue0 DCU_LCL_IFS */
706 #define AR5K_DCU_RETRY_LMT_BASE 0x1080 /* Register Address -Queue0 DCU_RETRY_LMT */
709 #define AR5K_DCU_RETRY_LMT_STA_RTS 0x00003f00 /* STA RTS failure limit. If exceeded CW reset */
711 #define AR5K_DCU_RETRY_LMT_STA_DATA 0x000fc000 /* STA data failure limit. If exceeded CW reset. */
718 #define AR5K_DCU_CHAN_TIME_BASE 0x10c0 /* Register Address -Queue0 DCU_CHAN_TIME */
719 #define AR5K_DCU_CHAN_TIME_DUR 0x000fffff /* Channel time duration */
729 * with pending frames. Intra-frame lockout means we wait until
736 #define AR5K_DCU_MISC_BASE 0x1100 /* Register Address -Queue0 DCU_MISC */
740 reset policy (?) */
742 CW reset policy */
745 #define AR5K_DCU_MISC_HCFPOLL_ENABLE 0x00000800 /* CF - Poll enable */
747 #define AR5K_DCU_MISC_FRMPRFTCH_ENABLE 0x00002000 /* Enable frame pre-fetch */
755 #define AR5K_DCU_MISC_ARBLOCK_CTL_INTFRM 1 /* Intra-frame lockout */
759 #define AR5K_DCU_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Disable post-frame backoff */
794 * and it's used for generating pseudo-random
798 * used for idle sensing -multiplied with cwmin/max etc-)
803 #define AR5K_DCU_GBL_IFS_MISC_SIFS_DUR_USEC 0x000003f0 /* SIFS Duration mask */
805 #define AR5K_DCU_GBL_IFS_MISC_USEC_DUR 0x000ffc00 /* USEC Duration mask */
808 #define AR5K_DCU_GBL_IFS_MISC_SIFS_CNT_RST 0x00400000 /* SIFS cnt reset policy (?) */
809 #define AR5K_DCU_GBL_IFS_MISC_AIFS_CNT_RST 0x00800000 /* AIFS cnt reset policy (?) */
816 #define AR5K_DCU_FP_NOBURST_DCU_EN 0x00000001 /* Enable non-burst prefetch on DCU (?) */
817 #define AR5K_DCU_FP_NOBURST_EN 0x00000010 /* Enable non-burst prefetch (?) */
852 * Reset control register
855 #define AR5K_RESET_CTL_PCU 0x00000001 /* Protocol Control Unit reset */
856 #define AR5K_RESET_CTL_DMA 0x00000002 /* DMA (Rx/Tx) reset [5210] */
857 #define AR5K_RESET_CTL_BASEBAND 0x00000002 /* Baseband reset [5211+] */
858 #define AR5K_RESET_CTL_MAC 0x00000004 /* MAC reset (PCU+Baseband ?) [5210] */
859 #define AR5K_RESET_CTL_PHY 0x00000008 /* PHY reset [5210] */
860 #define AR5K_RESET_CTL_PCI 0x00000010 /* PCI Core reset (interrupts etc) */
866 #define AR5K_SLEEP_CTL_SLDUR 0x0000ffff /* Sleep duration mask */
874 #define AR5K_SLEEP_CTL_DUR_TIM_POL 0x00040000 /* Sleep duration timing policy */
875 #define AR5K_SLEEP_CTL_DUR_WRITE_POL 0x00080000 /* Sleep duration write policy */
936 * Mode 0 -> always input
937 * Mode 1 -> output when GPIODO for this GPIO is set to 0
938 * Mode 2 -> output when GPIODO for this GPIO is set to 1
939 * Mode 3 -> always output
989 * on 5424 and newer pci-e chips. */
999 * PCI-E Power management configuration
1008 #define AR5K_PCIE_PM_CTL_LDRESET_EN 0x00000008 /* Enable reset when link goes
1020 * PCI-E Workaround enable register
1025 * PCI-E Serializer/Deserializer
1036 * Here we got a difference between 5210/5211-12
1043 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
1048 * 5211 - write offset to AR5K_EEPROM_BASE
1054 * 5210 - enable eeprom access (AR5K_PCICFG_EEAE)
1057 * 5211 - write AR5K_EEPROM_CMD_RESET on AR5K_EEPROM_CMD
1064 * file posted in madwifi-devel mailing list.
1075 #define AR5K_EEPROM_DATA (ah->ah_version == AR5K_AR5210 ? \
1084 #define AR5K_EEPROM_CMD_RESET 0x00000004 /* EEPROM reset */
1091 #define AR5K_EEPROM_STATUS (ah->ah_version == AR5K_AR5210 ? \
1120 * Range 0x7000 - 0x7ce0
1128 * during channel reset (see reset func)
1145 #define AR5K_STA_ID1_ADHOC 0x00020000 /* Set Ad-Hoc mode */
1151 #define AR5K_STA_ID1_PCF (ah->ah_version == AR5K_AR5210 ? \
1207 #define AR5K_RSSI_THR_BMISS (ah->ah_version == AR5K_AR5210 ? \
1215 * easier we define a macro based on ah->ah_version for common
1241 #define AR5K_USEC (ah->ah_version == AR5K_AR5210 ? \
1261 #define AR5K_BEACON (ah->ah_version == AR5K_AR5210 ? \
1268 #define AR5K_BEACON_RESET_TSF 0x01000000 /* Force TSF reset */
1275 #define AR5K_CFP_PERIOD (ah->ah_version == AR5K_AR5210 ? \
1283 #define AR5K_TIMER0 (ah->ah_version == AR5K_AR5210 ? \
1291 #define AR5K_TIMER1 (ah->ah_version == AR5K_AR5210 ? \
1299 #define AR5K_TIMER2 (ah->ah_version == AR5K_AR5210 ? \
1307 #define AR5K_TIMER3 (ah->ah_version == AR5K_AR5210 ? \
1332 * CFP duration register
1336 #define AR5K_CFP_DUR (ah->ah_version == AR5K_AR5210 ? \
1344 #define AR5K_RX_FILTER (ah->ah_version == AR5K_AR5210 ? \
1354 #define AR5K_RX_FILTER_PHYERR_5212 0x00000100 /* Don't filter phy errors [5212+] */
1355 #define AR5K_RX_FILTER_RADARERR_5212 0x00000200 /* Don't filter phy radar errors [5212+] */
1359 ((ah->ah_version == AR5K_AR5211 ? \
1362 ((ah->ah_version == AR5K_AR5211 ? \
1370 #define AR5K_MCAST_FILTER0 (ah->ah_version == AR5K_AR5210 ? \
1378 #define AR5K_MCAST_FILTER1 (ah->ah_version == AR5K_AR5210 ? \
1410 #define AR5K_DIAG_SW (ah->ah_version == AR5K_AR5210 ? \
1420 #define AR5K_DIAG_SW_DIS_RX (ah->ah_version == AR5K_AR5210 ? \
1424 #define AR5K_DIAG_SW_LOOP_BACK (ah->ah_version == AR5K_AR5210 ? \
1428 #define AR5K_DIAG_SW_CORR_FCS (ah->ah_version == AR5K_AR5210 ? \
1432 #define AR5K_DIAG_SW_CHAN_INFO (ah->ah_version == AR5K_AR5210 ? \
1436 #define AR5K_DIAG_SW_EN_SCRAM_SEED (ah->ah_version == AR5K_AR5210 ? \
1444 #define AR5K_DIAG_SW_FRAME_NV0_5211 0x00020000 /* Accept frames of non-zero protocol number */
1445 #define AR5K_DIAG_SW_FRAME_NV0 (ah->ah_version == AR5K_AR5210 ? \
1459 #define AR5K_TSF_L32 (ah->ah_version == AR5K_AR5210 ? \
1467 #define AR5K_TSF_U32 (ah->ah_version == AR5K_AR5210 ? \
1515 * Back-off status register [5210]
1528 #define AR5K_NAV (ah->ah_version == AR5K_AR5210 ? \
1543 #define AR5K_RTS_OK (ah->ah_version == AR5K_AR5210 ? \
1551 #define AR5K_RTS_FAIL (ah->ah_version == AR5K_AR5210 ? \
1559 #define AR5K_ACK_FAIL (ah->ah_version == AR5K_AR5210 ? \
1567 #define AR5K_FCS_FAIL (ah->ah_version == AR5K_AR5210 ? \
1575 #define AR5K_BEACON_CNT (ah->ah_version == AR5K_AR5210 ? \
1714 #define AR5K_QUIET_CTL2_QT_DUR 0xffff0000 /* Mask for quiet period duration */
1736 * PHY error filter register
1787 * PHY Error Counters (same masks as AR5K_PHY_ERR_FIL)
1795 /* if the PHY Error Counters reach this maximum, we get MIB interrupts */
1805 * Range: 0x8147 - 0x818c
1809 * Rate -> ACK SIFS mapping table (32 entries)
1817 * Rate -> duration mapping table (32 entries)
1823 * Rate -> db mapping table
1830 * db -> Rate mapping table
1841 /*===PHY REGISTERS===*/
1844 * PHY registers start
1860 #define AR5K_PHY_TST2_ALT_RFDATA 0x00004000 /* Alternate RFDATA (5-2GHz switch ?) */
1873 * PHY frame control register [5110] /turbo mode register [5111+]
1888 * PHY agility command register
1902 * PHY timing register 3 [5112+]
1911 * PHY chip revision register
1916 * PHY activation register
1919 #define AR5K_PHY_ACT_ENABLE 0x00000001 /* Activate PHY */
1920 #define AR5K_PHY_ACT_DISABLE 0x00000002 /* Deactivate PHY */
1923 * PHY RF control registers
1949 * Pre-Amplifier control register
1950 * (XPA -> external pre-amplifier)
1959 * PHY settling register
1968 * PHY Gain registers
1971 #define AR5K_PHY_GAIN_TXRX_ATTEN 0x0003f000 /* TX-RX Attenuation */
1977 #define AR5K_PHY_GAIN_OFFSET_RXTX_FLAG 0x00020000 /* RX-TX flag (?) */
1992 * PHY signal register
2002 * PHY coarse agility control register
2012 * PHY agility control register
2015 #define AR5K_PHY_AGCCTL_CAL 0x00000001 /* Enable PHY calibration */
2023 * PHY noise floor status register (CCA = Clear Channel Assessment)
2028 #define AR5K_PHY_NF_THRESH62 0x0007f000 /* Thresh62 -check ANI patent- (field) */
2034 * PHY ADC saturation register [5110]
2043 * PHY Weak ofdm signal detection threshold registers (ANI) [5212+]
2067 * PHY sleep registers [5112+]
2081 * PHY PLL (Phase Locked Loop) control register
2085 /* 40MHz -> 5GHz band */
2089 #define AR5K_PHY_PLL_40MHZ (ah->ah_version == AR5K_AR5211 ? \
2091 /* 44MHz -> 2.4GHz band */
2094 #define AR5K_PHY_PLL_44MHZ (ah->ah_version == AR5K_AR5211 ? \
2133 * PHY RF stage register [5210]
2152 * PHY Antenna control register
2162 * PHY receiver delay register [5111+]
2168 * PHY max rx length register (?) [5111]
2173 * PHY timing register 4
2193 * PHY timing register 5
2194 * OFDM Self-correlator Cyclic RSSI threshold params
2207 * PHY-only warm reset register
2212 * PHY-only control register
2225 * PHY PAPD probe register [5111+]
2246 * PHY TX rate power registers [5112+]
2256 * PHY frame control register [5111+]
2260 #define AR5K_PHY_FRAME_CTL (ah->ah_version == AR5K_AR5210 ? \
2262 /*---[5111+]---*/
2270 /*---[5110/5111]---*/
2271 #define AR5K_PHY_FRAME_CTL_TIMING_ERR 0x01000000 /* PHY timing error */
2286 * PHY Tx Power adjustment register [5212A+]
2295 * PHY radar detection register [5111+]
2301 5-bits, units unknown {0..31}
2306 6-bits, dBm range {0..63}
2311 6-bits, dBm range {0..63}
2316 6-bits, dBm range {0..63}
2322 7-bits, standard power range
2327 * PHY antenna switch table registers
2333 * PHY Noise floor threshold
2358 * RF Bus access request register (for synth-only channel switching)
2404 * PHY timing IQ calibration result register [5111+]
2411 * PHY current RSSI register [5111+]
2416 * PHY RF Bus grant register
2422 * PHY ADC test register
2429 * PHY DAC test register
2436 * PHY PTAT register (?)
2441 * PHY Illegal TX rate register [5112+]
2446 * PHY SPUR Power register [5112+]
2454 * PHY Channel status register [5112+] (?)
2468 * PHY clock sleep registers [5112+]
2478 * PHY PAPD I (power?) table (?)
2485 * PHY PCDAC TX power table
2491 * PHY mode register [5111+]
2494 #define AR5K_PHY_MODE_MOD 0x00000001 /* PHY Modulation bit */
2509 * PHY CCK transmit control register [5111+ (?)]
2518 * PHY CCK Cross-correlator Barker RSSI threshold register [5212+]
2529 * PHY 2GHz gain register [5111+]
2576 * PHY PDADC Tx power table