Lines Matching full:ee
40 static u16 ath5k_eeprom_bin2freq(struct ath5k_eeprom_info *ee, u16 bin, in ath5k_eeprom_bin2freq() argument
49 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_bin2freq()
55 if (ee->ee_version > AR5K_EEPROM_VERSION_3_2) in ath5k_eeprom_bin2freq()
75 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_init_header() local
141 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) in ath5k_eeprom_init_header()
144 if (ee->ee_version >= AR5K_EEPROM_VERSION_5_0) { in ath5k_eeprom_init_header()
153 ee->ee_ob[AR5K_EEPROM_MODE_11B][0] = val & 0x7; in ath5k_eeprom_init_header()
154 ee->ee_db[AR5K_EEPROM_MODE_11B][0] = (val >> 3) & 0x7; in ath5k_eeprom_init_header()
157 ee->ee_ob[AR5K_EEPROM_MODE_11G][0] = val & 0x7; in ath5k_eeprom_init_header()
158 ee->ee_db[AR5K_EEPROM_MODE_11G][0] = (val >> 3) & 0x7; in ath5k_eeprom_init_header()
164 ee->ee_is_hb63 = true; in ath5k_eeprom_init_header()
166 ee->ee_is_hb63 = false; in ath5k_eeprom_init_header()
169 ee->ee_rfkill_pin = (u8) AR5K_REG_MS(val, AR5K_EEPROM_RFKILL_GPIO_SEL); in ath5k_eeprom_init_header()
170 ee->ee_rfkill_pol = val & AR5K_EEPROM_RFKILL_POLARITY ? true : false; in ath5k_eeprom_init_header()
179 ee->ee_serdes = (val == AR5K_EEPROM_PCIE_SERDES_SECTION) ? in ath5k_eeprom_init_header()
192 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_ants() local
198 ee->ee_switch_settling[mode] = (val >> 8) & 0x7f; in ath5k_eeprom_read_ants()
199 ee->ee_atn_tx_rx[mode] = (val >> 2) & 0x3f; in ath5k_eeprom_read_ants()
200 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; in ath5k_eeprom_read_ants()
203 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; in ath5k_eeprom_read_ants()
204 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; in ath5k_eeprom_read_ants()
205 ee->ee_ant_control[mode][i++] = val & 0x3f; in ath5k_eeprom_read_ants()
208 ee->ee_ant_control[mode][i++] = (val >> 10) & 0x3f; in ath5k_eeprom_read_ants()
209 ee->ee_ant_control[mode][i++] = (val >> 4) & 0x3f; in ath5k_eeprom_read_ants()
210 ee->ee_ant_control[mode][i] = (val << 2) & 0x3f; in ath5k_eeprom_read_ants()
213 ee->ee_ant_control[mode][i++] |= (val >> 14) & 0x3; in ath5k_eeprom_read_ants()
214 ee->ee_ant_control[mode][i++] = (val >> 8) & 0x3f; in ath5k_eeprom_read_ants()
215 ee->ee_ant_control[mode][i++] = (val >> 2) & 0x3f; in ath5k_eeprom_read_ants()
216 ee->ee_ant_control[mode][i] = (val << 4) & 0x3f; in ath5k_eeprom_read_ants()
219 ee->ee_ant_control[mode][i++] |= (val >> 12) & 0xf; in ath5k_eeprom_read_ants()
220 ee->ee_ant_control[mode][i++] = (val >> 6) & 0x3f; in ath5k_eeprom_read_ants()
221 ee->ee_ant_control[mode][i++] = val & 0x3f; in ath5k_eeprom_read_ants()
225 (ee->ee_ant_control[mode][0] << 4); in ath5k_eeprom_read_ants()
227 ee->ee_ant_control[mode][1] | in ath5k_eeprom_read_ants()
228 (ee->ee_ant_control[mode][2] << 6) | in ath5k_eeprom_read_ants()
229 (ee->ee_ant_control[mode][3] << 12) | in ath5k_eeprom_read_ants()
230 (ee->ee_ant_control[mode][4] << 18) | in ath5k_eeprom_read_ants()
231 (ee->ee_ant_control[mode][5] << 24); in ath5k_eeprom_read_ants()
233 ee->ee_ant_control[mode][6] | in ath5k_eeprom_read_ants()
234 (ee->ee_ant_control[mode][7] << 6) | in ath5k_eeprom_read_ants()
235 (ee->ee_ant_control[mode][8] << 12) | in ath5k_eeprom_read_ants()
236 (ee->ee_ant_control[mode][9] << 18) | in ath5k_eeprom_read_ants()
237 (ee->ee_ant_control[mode][10] << 24); in ath5k_eeprom_read_ants()
252 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_modes() local
256 ee->ee_n_piers[mode] = 0; in ath5k_eeprom_read_modes()
258 ee->ee_adc_desired_size[mode] = (s8)((val >> 8) & 0xff); in ath5k_eeprom_read_modes()
261 ee->ee_ob[mode][3] = (val >> 5) & 0x7; in ath5k_eeprom_read_modes()
262 ee->ee_db[mode][3] = (val >> 2) & 0x7; in ath5k_eeprom_read_modes()
263 ee->ee_ob[mode][2] = (val << 1) & 0x7; in ath5k_eeprom_read_modes()
266 ee->ee_ob[mode][2] |= (val >> 15) & 0x1; in ath5k_eeprom_read_modes()
267 ee->ee_db[mode][2] = (val >> 12) & 0x7; in ath5k_eeprom_read_modes()
268 ee->ee_ob[mode][1] = (val >> 9) & 0x7; in ath5k_eeprom_read_modes()
269 ee->ee_db[mode][1] = (val >> 6) & 0x7; in ath5k_eeprom_read_modes()
270 ee->ee_ob[mode][0] = (val >> 3) & 0x7; in ath5k_eeprom_read_modes()
271 ee->ee_db[mode][0] = val & 0x7; in ath5k_eeprom_read_modes()
275 ee->ee_ob[mode][1] = (val >> 4) & 0x7; in ath5k_eeprom_read_modes()
276 ee->ee_db[mode][1] = val & 0x7; in ath5k_eeprom_read_modes()
281 ee->ee_tx_end2xlna_enable[mode] = (val >> 8) & 0xff; in ath5k_eeprom_read_modes()
282 ee->ee_thr_62[mode] = val & 0xff; in ath5k_eeprom_read_modes()
285 ee->ee_thr_62[mode] = mode == AR5K_EEPROM_MODE_11A ? 15 : 28; in ath5k_eeprom_read_modes()
288 ee->ee_tx_end2xpa_disable[mode] = (val >> 8) & 0xff; in ath5k_eeprom_read_modes()
289 ee->ee_tx_frm2xpa_enable[mode] = val & 0xff; in ath5k_eeprom_read_modes()
292 ee->ee_pga_desired_size[mode] = (val >> 8) & 0xff; in ath5k_eeprom_read_modes()
295 ee->ee_noise_floor_thr[mode] = -((((val & 0xff) ^ 0xff)) + 1); in ath5k_eeprom_read_modes()
297 ee->ee_noise_floor_thr[mode] = val & 0xff; in ath5k_eeprom_read_modes()
300 ee->ee_noise_floor_thr[mode] = in ath5k_eeprom_read_modes()
304 ee->ee_xlna_gain[mode] = (val >> 5) & 0xff; in ath5k_eeprom_read_modes()
305 ee->ee_x_gain[mode] = (val >> 1) & 0xf; in ath5k_eeprom_read_modes()
306 ee->ee_xpd[mode] = val & 0x1; in ath5k_eeprom_read_modes()
310 ee->ee_fixed_bias[mode] = (val >> 13) & 0x1; in ath5k_eeprom_read_modes()
314 ee->ee_false_detect[mode] = (val >> 6) & 0x7f; in ath5k_eeprom_read_modes()
317 ee->ee_xr_power[mode] = val & 0x3f; in ath5k_eeprom_read_modes()
320 ee->ee_ob[mode][0] = val & 0x7; in ath5k_eeprom_read_modes()
321 ee->ee_db[mode][0] = (val >> 3) & 0x7; in ath5k_eeprom_read_modes()
326 ee->ee_i_gain[mode] = AR5K_EEPROM_I_GAIN; in ath5k_eeprom_read_modes()
327 ee->ee_cck_ofdm_power_delta = AR5K_EEPROM_CCK_OFDM_DELTA; in ath5k_eeprom_read_modes()
329 ee->ee_i_gain[mode] = (val >> 13) & 0x7; in ath5k_eeprom_read_modes()
332 ee->ee_i_gain[mode] |= (val << 3) & 0x38; in ath5k_eeprom_read_modes()
335 ee->ee_cck_ofdm_power_delta = (val >> 3) & 0xff; in ath5k_eeprom_read_modes()
337 ee->ee_scaled_cck_delta = (val >> 11) & 0x1f; in ath5k_eeprom_read_modes()
343 ee->ee_i_cal[mode] = (val >> 8) & 0x3f; in ath5k_eeprom_read_modes()
344 ee->ee_q_cal[mode] = (val >> 3) & 0x1f; in ath5k_eeprom_read_modes()
359 ee->ee_margin_tx_rx[mode] = val & 0x3f; in ath5k_eeprom_read_modes()
364 ee->ee_pwr_cal_b[0].freq = in ath5k_eeprom_read_modes()
365 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); in ath5k_eeprom_read_modes()
366 if (ee->ee_pwr_cal_b[0].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
367 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
369 ee->ee_pwr_cal_b[1].freq = in ath5k_eeprom_read_modes()
370 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); in ath5k_eeprom_read_modes()
371 if (ee->ee_pwr_cal_b[1].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
372 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
375 ee->ee_pwr_cal_b[2].freq = in ath5k_eeprom_read_modes()
376 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); in ath5k_eeprom_read_modes()
377 if (ee->ee_pwr_cal_b[2].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
378 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
381 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; in ath5k_eeprom_read_modes()
386 ee->ee_pwr_cal_g[0].freq = in ath5k_eeprom_read_modes()
387 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); in ath5k_eeprom_read_modes()
388 if (ee->ee_pwr_cal_g[0].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
389 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
391 ee->ee_pwr_cal_g[1].freq = in ath5k_eeprom_read_modes()
392 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); in ath5k_eeprom_read_modes()
393 if (ee->ee_pwr_cal_g[1].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
394 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
397 ee->ee_turbo_max_power[mode] = val & 0x7f; in ath5k_eeprom_read_modes()
398 ee->ee_xr_power[mode] = (val >> 7) & 0x3f; in ath5k_eeprom_read_modes()
401 ee->ee_pwr_cal_g[2].freq = in ath5k_eeprom_read_modes()
402 ath5k_eeprom_bin2freq(ee, val & 0xff, mode); in ath5k_eeprom_read_modes()
403 if (ee->ee_pwr_cal_g[2].freq != AR5K_EEPROM_CHANNEL_DIS) in ath5k_eeprom_read_modes()
404 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_modes()
407 ee->ee_margin_tx_rx[mode] = (val >> 8) & 0x3f; in ath5k_eeprom_read_modes()
410 ee->ee_i_cal[mode] = (val >> 5) & 0x3f; in ath5k_eeprom_read_modes()
411 ee->ee_q_cal[mode] = val & 0x1f; in ath5k_eeprom_read_modes()
415 ee->ee_cck_ofdm_gain_delta = val & 0xff; in ath5k_eeprom_read_modes()
423 if (ee->ee_version < AR5K_EEPROM_VERSION_5_0) in ath5k_eeprom_read_modes()
428 ee->ee_switch_settling_turbo[mode] = (val >> 6) & 0x7f; in ath5k_eeprom_read_modes()
430 ee->ee_atn_tx_rx_turbo[mode] = (val >> 13) & 0x7; in ath5k_eeprom_read_modes()
432 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x7) << 3; in ath5k_eeprom_read_modes()
433 ee->ee_margin_tx_rx_turbo[mode] = (val >> 3) & 0x3f; in ath5k_eeprom_read_modes()
435 ee->ee_adc_desired_size_turbo[mode] = (val >> 9) & 0x7f; in ath5k_eeprom_read_modes()
437 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x1) << 7; in ath5k_eeprom_read_modes()
438 ee->ee_pga_desired_size_turbo[mode] = (val >> 1) & 0xff; in ath5k_eeprom_read_modes()
440 if (AR5K_EEPROM_EEMAP(ee->ee_misc0) >= 2) in ath5k_eeprom_read_modes()
441 ee->ee_pd_gain_overlap = (val >> 9) & 0xf; in ath5k_eeprom_read_modes()
444 ee->ee_switch_settling_turbo[mode] = (val >> 8) & 0x7f; in ath5k_eeprom_read_modes()
446 ee->ee_atn_tx_rx_turbo[mode] = (val >> 15) & 0x7; in ath5k_eeprom_read_modes()
448 ee->ee_atn_tx_rx_turbo[mode] |= (val & 0x1f) << 1; in ath5k_eeprom_read_modes()
449 ee->ee_margin_tx_rx_turbo[mode] = (val >> 5) & 0x3f; in ath5k_eeprom_read_modes()
451 ee->ee_adc_desired_size_turbo[mode] = (val >> 11) & 0x7f; in ath5k_eeprom_read_modes()
453 ee->ee_adc_desired_size_turbo[mode] |= (val & 0x7) << 5; in ath5k_eeprom_read_modes()
454 ee->ee_pga_desired_size_turbo[mode] = (val >> 3) & 0xff; in ath5k_eeprom_read_modes()
469 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_init_modes() local
482 ee->ee_turbo_max_power[AR5K_EEPROM_MODE_11A] = in ath5k_eeprom_init_modes()
483 AR5K_EEPROM_HDR_T_5GHZ_DBM(ee->ee_header); in ath5k_eeprom_init_modes()
499 ee->ee_thr_62[AR5K_EEPROM_MODE_11A] = 15; in ath5k_eeprom_init_modes()
500 ee->ee_thr_62[AR5K_EEPROM_MODE_11B] = 28; in ath5k_eeprom_init_modes()
501 ee->ee_thr_62[AR5K_EEPROM_MODE_11G] = 28; in ath5k_eeprom_init_modes()
513 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_freq_list() local
519 ee->ee_n_piers[mode] = 0; in ath5k_eeprom_read_freq_list()
527 pc[i++].freq = ath5k_eeprom_bin2freq(ee, in ath5k_eeprom_read_freq_list()
529 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_freq_list()
535 pc[i++].freq = ath5k_eeprom_bin2freq(ee, in ath5k_eeprom_read_freq_list()
537 ee->ee_n_piers[mode]++; in ath5k_eeprom_read_freq_list()
550 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_init_11a_pcal_freq() local
551 struct ath5k_chan_pcal_info *pcal = ee->ee_pwr_cal_a; in ath5k_eeprom_init_11a_pcal_freq()
556 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) { in ath5k_eeprom_init_11a_pcal_freq()
588 ee->ee_n_piers[AR5K_EEPROM_MODE_11A] = 10; in ath5k_eeprom_init_11a_pcal_freq()
591 pcal[i].freq = ath5k_eeprom_bin2freq(ee, in ath5k_eeprom_init_11a_pcal_freq()
603 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_init_11bg_2413() local
608 pcal = ee->ee_pwr_cal_b; in ath5k_eeprom_init_11bg_2413()
611 pcal = ee->ee_pwr_cal_g; in ath5k_eeprom_init_11bg_2413()
669 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_free_pcal_info() local
675 if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_eeprom_free_pcal_info()
677 chinfo = ee->ee_pwr_cal_a; in ath5k_eeprom_free_pcal_info()
680 if (!AR5K_EEPROM_HDR_11B(ee->ee_header)) in ath5k_eeprom_free_pcal_info()
682 chinfo = ee->ee_pwr_cal_b; in ath5k_eeprom_free_pcal_info()
685 if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) in ath5k_eeprom_free_pcal_info()
687 chinfo = ee->ee_pwr_cal_g; in ath5k_eeprom_free_pcal_info()
693 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_free_pcal_info()
717 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_convert_pcal_info_5111() local
721 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_convert_pcal_info_5111()
724 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_convert_pcal_info_5111()
743 if (!((ee->ee_x_gain[mode] >> idx) & 0x1)) { in ath5k_eeprom_convert_pcal_info_5111()
752 ee->ee_pd_gains[mode] = 1; in ath5k_eeprom_convert_pcal_info_5111()
798 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_pcal_info_5111() local
804 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); in ath5k_eeprom_read_pcal_info_5111()
807 if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5111()
816 pcal = ee->ee_pwr_cal_a; in ath5k_eeprom_read_pcal_info_5111()
819 if (!AR5K_EEPROM_HDR_11B(ee->ee_header) && in ath5k_eeprom_read_pcal_info_5111()
820 !AR5K_EEPROM_HDR_11G(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5111()
823 pcal = ee->ee_pwr_cal_b; in ath5k_eeprom_read_pcal_info_5111()
830 ee->ee_n_piers[mode] = 3; in ath5k_eeprom_read_pcal_info_5111()
833 if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5111()
836 pcal = ee->ee_pwr_cal_g; in ath5k_eeprom_read_pcal_info_5111()
843 ee->ee_n_piers[mode] = 3; in ath5k_eeprom_read_pcal_info_5111()
849 for (i = 0; i < ee->ee_n_piers[mode]; i++) { in ath5k_eeprom_read_pcal_info_5111()
908 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_convert_pcal_info_5112() local
910 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_convert_pcal_info_5112()
914 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_convert_pcal_info_5112()
928 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { in ath5k_eeprom_convert_pcal_info_5112()
1021 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_pcal_info_5112() local
1024 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_read_pcal_info_5112()
1037 if ((ee->ee_x_gain[mode] >> i) & 0x1) in ath5k_eeprom_read_pcal_info_5112()
1040 ee->ee_pd_gains[mode] = pd_gains; in ath5k_eeprom_read_pcal_info_5112()
1050 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); in ath5k_eeprom_read_pcal_info_5112()
1054 gen_chan_info = ee->ee_pwr_cal_a; in ath5k_eeprom_read_pcal_info_5112()
1057 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); in ath5k_eeprom_read_pcal_info_5112()
1058 if (AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5112()
1062 gen_chan_info = ee->ee_pwr_cal_b; in ath5k_eeprom_read_pcal_info_5112()
1065 offset = AR5K_EEPROM_GROUPS_START(ee->ee_version); in ath5k_eeprom_read_pcal_info_5112()
1066 if (AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5112()
1068 else if (AR5K_EEPROM_HDR_11B(ee->ee_header)) in ath5k_eeprom_read_pcal_info_5112()
1072 gen_chan_info = ee->ee_pwr_cal_g; in ath5k_eeprom_read_pcal_info_5112()
1078 for (i = 0; i < ee->ee_n_piers[mode]; i++) { in ath5k_eeprom_read_pcal_info_5112()
1115 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_3) { in ath5k_eeprom_read_pcal_info_5112()
1154 ath5k_pdgains_size_2413(struct ath5k_eeprom_info *ee, unsigned int mode) in ath5k_pdgains_size_2413() argument
1159 sz = pdgains_size[ee->ee_pd_gains[mode] - 1]; in ath5k_pdgains_size_2413()
1160 sz *= ee->ee_n_piers[mode]; in ath5k_pdgains_size_2413()
1168 ath5k_cal_data_offset_2413(struct ath5k_eeprom_info *ee, int mode) in ath5k_cal_data_offset_2413() argument
1170 u32 offset = AR5K_EEPROM_CAL_DATA_START(ee->ee_misc4); in ath5k_cal_data_offset_2413()
1174 if (AR5K_EEPROM_HDR_11B(ee->ee_header)) in ath5k_cal_data_offset_2413()
1175 offset += ath5k_pdgains_size_2413(ee, in ath5k_cal_data_offset_2413()
1180 if (AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_cal_data_offset_2413()
1181 offset += ath5k_pdgains_size_2413(ee, in ath5k_cal_data_offset_2413()
1200 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_convert_pcal_info_2413() local
1202 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_convert_pcal_info_2413()
1206 for (pier = 0; pier < ee->ee_n_piers[mode]; pier++) { in ath5k_eeprom_convert_pcal_info_2413()
1220 for (pdg = 0; pdg < ee->ee_pd_gains[mode]; pdg++) { in ath5k_eeprom_convert_pcal_info_2413()
1228 if (pdg == ee->ee_pd_gains[mode] - 1) in ath5k_eeprom_convert_pcal_info_2413()
1267 if (pdg == ee->ee_pd_gains[mode] - 1) in ath5k_eeprom_convert_pcal_info_2413()
1284 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_pcal_info_2413() local
1287 u8 *pdgain_idx = ee->ee_pdc_to_idx[mode]; in ath5k_eeprom_read_pcal_info_2413()
1300 if ((ee->ee_x_gain[mode] >> idx) & 0x1) in ath5k_eeprom_read_pcal_info_2413()
1304 ee->ee_pd_gains[mode] = pd_gains; in ath5k_eeprom_read_pcal_info_2413()
1309 offset = ath5k_cal_data_offset_2413(ee, mode); in ath5k_eeprom_read_pcal_info_2413()
1312 if (!AR5K_EEPROM_HDR_11A(ee->ee_header)) in ath5k_eeprom_read_pcal_info_2413()
1317 chinfo = ee->ee_pwr_cal_a; in ath5k_eeprom_read_pcal_info_2413()
1320 if (!AR5K_EEPROM_HDR_11B(ee->ee_header)) in ath5k_eeprom_read_pcal_info_2413()
1325 chinfo = ee->ee_pwr_cal_b; in ath5k_eeprom_read_pcal_info_2413()
1328 if (!AR5K_EEPROM_HDR_11G(ee->ee_header)) in ath5k_eeprom_read_pcal_info_2413()
1333 chinfo = ee->ee_pwr_cal_g; in ath5k_eeprom_read_pcal_info_2413()
1339 for (i = 0; i < ee->ee_n_piers[mode]; i++) { in ath5k_eeprom_read_pcal_info_2413()
1475 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_target_rate_pwr_info() local
1482 offset = AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1); in ath5k_eeprom_read_target_rate_pwr_info()
1483 rate_target_pwr_num = &ee->ee_rate_target_pwr_num[mode]; in ath5k_eeprom_read_target_rate_pwr_info()
1486 offset += AR5K_EEPROM_TARGET_PWR_OFF_11A(ee->ee_version); in ath5k_eeprom_read_target_rate_pwr_info()
1487 rate_pcal_info = ee->ee_rate_tpwr_a; in ath5k_eeprom_read_target_rate_pwr_info()
1488 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_5GHZ_RATE_CHAN; in ath5k_eeprom_read_target_rate_pwr_info()
1491 offset += AR5K_EEPROM_TARGET_PWR_OFF_11B(ee->ee_version); in ath5k_eeprom_read_target_rate_pwr_info()
1492 rate_pcal_info = ee->ee_rate_tpwr_b; in ath5k_eeprom_read_target_rate_pwr_info()
1493 ee->ee_rate_target_pwr_num[mode] = 2; /* 3rd is g mode's 1st */ in ath5k_eeprom_read_target_rate_pwr_info()
1496 offset += AR5K_EEPROM_TARGET_PWR_OFF_11G(ee->ee_version); in ath5k_eeprom_read_target_rate_pwr_info()
1497 rate_pcal_info = ee->ee_rate_tpwr_g; in ath5k_eeprom_read_target_rate_pwr_info()
1498 ee->ee_rate_target_pwr_num[mode] = AR5K_EEPROM_N_2GHZ_CHAN; in ath5k_eeprom_read_target_rate_pwr_info()
1505 if (ee->ee_version <= AR5K_EEPROM_VERSION_3_2) { in ath5k_eeprom_read_target_rate_pwr_info()
1509 ath5k_eeprom_bin2freq(ee, (val >> 9) & 0x7f, mode); in ath5k_eeprom_read_target_rate_pwr_info()
1530 ath5k_eeprom_bin2freq(ee, (val >> 8) & 0xff, mode); in ath5k_eeprom_read_target_rate_pwr_info()
1570 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_pcal_info() local
1576 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 1)) in ath5k_eeprom_read_pcal_info()
1579 (AR5K_EEPROM_EEMAP(ee->ee_misc0) == 2)) in ath5k_eeprom_read_pcal_info()
1603 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_ctl_info() local
1612 fmask = AR5K_EEPROM_FREQ_M(ee->ee_version); in ath5k_eeprom_read_ctl_info()
1613 offset = AR5K_EEPROM_CTL(ee->ee_version); in ath5k_eeprom_read_ctl_info()
1614 ee->ee_ctls = AR5K_EEPROM_N_CTLS(ee->ee_version); in ath5k_eeprom_read_ctl_info()
1615 for (i = 0; i < ee->ee_ctls; i += 2) { in ath5k_eeprom_read_ctl_info()
1617 ee->ee_ctl[i] = (val >> 8) & 0xff; in ath5k_eeprom_read_ctl_info()
1618 ee->ee_ctl[i + 1] = val & 0xff; in ath5k_eeprom_read_ctl_info()
1622 if (ee->ee_version >= AR5K_EEPROM_VERSION_4_0) in ath5k_eeprom_read_ctl_info()
1623 offset += AR5K_EEPROM_TARGET_PWRSTART(ee->ee_misc1) - in ath5k_eeprom_read_ctl_info()
1626 offset += AR5K_EEPROM_GROUPS_START(ee->ee_version); in ath5k_eeprom_read_ctl_info()
1628 rep = ee->ee_ctl_pwr; in ath5k_eeprom_read_ctl_info()
1629 for (i = 0; i < ee->ee_ctls; i++) { in ath5k_eeprom_read_ctl_info()
1630 switch (ee->ee_ctl[i] & AR5K_CTL_MODE_M) { in ath5k_eeprom_read_ctl_info()
1639 if (ee->ee_ctl[i] == 0) { in ath5k_eeprom_read_ctl_info()
1640 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) in ath5k_eeprom_read_ctl_info()
1647 if (ee->ee_version >= AR5K_EEPROM_VERSION_3_3) { in ath5k_eeprom_read_ctl_info()
1698 rep[j].freq = ath5k_eeprom_bin2freq(ee, in ath5k_eeprom_read_ctl_info()
1710 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom; in ath5k_eeprom_read_spur_chans() local
1715 offset = AR5K_EEPROM_CTL(ee->ee_version) + in ath5k_eeprom_read_spur_chans()
1716 AR5K_EEPROM_N_CTLS(ee->ee_version); in ath5k_eeprom_read_spur_chans()
1718 if (ee->ee_version < AR5K_EEPROM_VERSION_5_3) { in ath5k_eeprom_read_spur_chans()
1720 ee->ee_spur_chans[0][0] = AR5K_EEPROM_NO_SPUR; in ath5k_eeprom_read_spur_chans()
1722 ee->ee_spur_chans[0][1] = AR5K_EEPROM_5413_SPUR_CHAN_1; in ath5k_eeprom_read_spur_chans()
1723 ee->ee_spur_chans[1][1] = AR5K_EEPROM_5413_SPUR_CHAN_2; in ath5k_eeprom_read_spur_chans()
1724 ee->ee_spur_chans[2][1] = AR5K_EEPROM_NO_SPUR; in ath5k_eeprom_read_spur_chans()
1725 } else if (ee->ee_version >= AR5K_EEPROM_VERSION_5_3) { in ath5k_eeprom_read_spur_chans()
1728 ee->ee_spur_chans[i][0] = val; in ath5k_eeprom_read_spur_chans()
1731 ee->ee_spur_chans[i][1] = val; in ath5k_eeprom_read_spur_chans()