Lines Matching +full:tx +full:- +full:ts +full:- +full:max
2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
34 * Here we handle the processing of the low-level hw descriptors
35 * that hw reads and writes via DMA for each TX and RX attempt (that means
36 * we can also have descriptors for failed TX/RX tries). We have two kind of
37 * descriptors for RX and TX, control descriptors tell the hw how to send or
49 * TX Control descriptors *
53 * ath5k_hw_setup_2word_tx_desc() - Initialize a 2-word tx control descriptor
60 * @tx_power: Tx power in 0.5dB steps
62 * @tx_tries0: Max number of retransmissions
69 * Internal function to initialize a 2-Word TX control descriptor
72 * Returns 0 on success or -EINVAL on false input
91 tx_ctl = &desc->ud.ds_tx5210.tx_ctl; in ath5k_hw_setup_2word_tx_desc()
95 * - Zero retries don't make sense. in ath5k_hw_setup_2word_tx_desc()
96 * - A zero rate will put the HW into a mode where it continuously sends in ath5k_hw_setup_2word_tx_desc()
102 return -EINVAL; in ath5k_hw_setup_2word_tx_desc()
107 return -EINVAL; in ath5k_hw_setup_2word_tx_desc()
111 memset(&desc->ud.ds_tx5210, 0, sizeof(struct ath5k_hw_5210_tx_desc)); in ath5k_hw_setup_2word_tx_desc()
118 frame_len = pkt_len - padsize + FCS_LEN; in ath5k_hw_setup_2word_tx_desc()
121 return -EINVAL; in ath5k_hw_setup_2word_tx_desc()
123 tx_ctl->tx_control_0 = frame_len & AR5K_2W_TX_DESC_CTL0_FRAME_LEN; in ath5k_hw_setup_2word_tx_desc()
132 return -EINVAL; in ath5k_hw_setup_2word_tx_desc()
134 tx_ctl->tx_control_1 = pkt_len & AR5K_2W_TX_DESC_CTL1_BUF_LEN; in ath5k_hw_setup_2word_tx_desc()
139 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_setup_2word_tx_desc()
141 return -EINVAL; in ath5k_hw_setup_2word_tx_desc()
142 tx_ctl->tx_control_0 |= in ath5k_hw_setup_2word_tx_desc()
146 /*Differences between 5210-5211*/ in ath5k_hw_setup_2word_tx_desc()
147 if (ah->ah_version == AR5K_AR5210) { in ath5k_hw_setup_2word_tx_desc()
161 tx_ctl->tx_control_0 |= in ath5k_hw_setup_2word_tx_desc()
166 tx_ctl->tx_control_0 |= in ath5k_hw_setup_2word_tx_desc()
170 tx_ctl->tx_control_1 |= in ath5k_hw_setup_2word_tx_desc()
176 tx_ctl->tx_control_##_c |= \ in ath5k_hw_setup_2word_tx_desc()
181 tx_ctl->tx_control_##_c |= \ in ath5k_hw_setup_2word_tx_desc()
188 if (ah->ah_version == AR5K_AR5211) { in ath5k_hw_setup_2word_tx_desc()
200 tx_ctl->tx_control_0 |= in ath5k_hw_setup_2word_tx_desc()
202 tx_ctl->tx_control_1 |= in ath5k_hw_setup_2word_tx_desc()
210 if ((ah->ah_version == AR5K_AR5210) && in ath5k_hw_setup_2word_tx_desc()
212 tx_ctl->tx_control_1 |= rtscts_duration & in ath5k_hw_setup_2word_tx_desc()
219 * ath5k_hw_setup_4word_tx_desc() - Initialize a 4-word tx control descriptor
226 * @tx_power: Tx power in 0.5dB steps
228 * @tx_tries0: Max number of retransmissions
235 * Internal function to initialize a 4-Word TX control descriptor
238 * Returns 0 on success or -EINVAL on false input
262 tx_ctl = &desc->ud.ds_tx5212.tx_ctl; in ath5k_hw_setup_4word_tx_desc()
266 * - Zero retries don't make sense. in ath5k_hw_setup_4word_tx_desc()
267 * - A zero rate will put the HW into a mode where it continuously sends in ath5k_hw_setup_4word_tx_desc()
273 return -EINVAL; in ath5k_hw_setup_4word_tx_desc()
278 return -EINVAL; in ath5k_hw_setup_4word_tx_desc()
281 tx_power += ah->ah_txpower.txp_offset; in ath5k_hw_setup_4word_tx_desc()
286 memset(&desc->ud.ds_tx5212.tx_stat, 0, in ath5k_hw_setup_4word_tx_desc()
287 sizeof(desc->ud.ds_tx5212.tx_stat)); in ath5k_hw_setup_4word_tx_desc()
294 frame_len = pkt_len - padsize + FCS_LEN; in ath5k_hw_setup_4word_tx_desc()
297 return -EINVAL; in ath5k_hw_setup_4word_tx_desc()
308 return -EINVAL; in ath5k_hw_setup_4word_tx_desc()
347 return -EINVAL; in ath5k_hw_setup_4word_tx_desc()
353 tx_ctl->tx_control_0 = txctl0; in ath5k_hw_setup_4word_tx_desc()
354 tx_ctl->tx_control_1 = txctl1; in ath5k_hw_setup_4word_tx_desc()
355 tx_ctl->tx_control_2 = txctl2; in ath5k_hw_setup_4word_tx_desc()
356 tx_ctl->tx_control_3 = txctl3; in ath5k_hw_setup_4word_tx_desc()
362 * ath5k_hw_setup_mrr_tx_desc() - Initialize an MRR tx control descriptor
366 * @tx_tries1: Max number of retransmissions for transmission series 1
368 * @tx_tries2: Max number of retransmissions for transmission series 2
370 * @tx_tries3: Max number of retransmissions for transmission series 3
372 * Multi rate retry (MRR) tx control descriptors are available only on AR5212
373 * MACs, they are part of the normal 4-word tx control descriptor (see above)
376 * Returns 0 on success or -EINVAL on invalid input
388 if (ah->ah_version < AR5K_AR5212) in ath5k_hw_setup_mrr_tx_desc()
402 return -EINVAL; in ath5k_hw_setup_mrr_tx_desc()
405 if (ah->ah_version == AR5K_AR5212) { in ath5k_hw_setup_mrr_tx_desc()
406 tx_ctl = &desc->ud.ds_tx5212.tx_ctl; in ath5k_hw_setup_mrr_tx_desc()
410 tx_ctl->tx_control_2 |= \ in ath5k_hw_setup_mrr_tx_desc()
413 tx_ctl->tx_control_3 |= \ in ath5k_hw_setup_mrr_tx_desc()
432 * TX Status descriptors *
436 * ath5k_hw_proc_2word_tx_status() - Process a tx status descriptor on 5210/1
439 * @ts: The &struct ath5k_tx_status
444 struct ath5k_tx_status *ts) in ath5k_hw_proc_2word_tx_status() argument
448 tx_status = &desc->ud.ds_tx5210.tx_stat; in ath5k_hw_proc_2word_tx_status()
451 if (unlikely((tx_status->tx_status_1 & AR5K_DESC_TX_STATUS1_DONE) == 0)) in ath5k_hw_proc_2word_tx_status()
452 return -EINPROGRESS; in ath5k_hw_proc_2word_tx_status()
457 ts->ts_tstamp = AR5K_REG_MS(tx_status->tx_status_0, in ath5k_hw_proc_2word_tx_status()
459 ts->ts_shortretry = AR5K_REG_MS(tx_status->tx_status_0, in ath5k_hw_proc_2word_tx_status()
461 ts->ts_final_retry = AR5K_REG_MS(tx_status->tx_status_0, in ath5k_hw_proc_2word_tx_status()
463 /*TODO: ts->ts_virtcol + test*/ in ath5k_hw_proc_2word_tx_status()
464 ts->ts_seqnum = AR5K_REG_MS(tx_status->tx_status_1, in ath5k_hw_proc_2word_tx_status()
466 ts->ts_rssi = AR5K_REG_MS(tx_status->tx_status_1, in ath5k_hw_proc_2word_tx_status()
468 ts->ts_antenna = 1; in ath5k_hw_proc_2word_tx_status()
469 ts->ts_status = 0; in ath5k_hw_proc_2word_tx_status()
470 ts->ts_final_idx = 0; in ath5k_hw_proc_2word_tx_status()
472 if (!(tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK)) { in ath5k_hw_proc_2word_tx_status()
473 if (tx_status->tx_status_0 & in ath5k_hw_proc_2word_tx_status()
475 ts->ts_status |= AR5K_TXERR_XRETRY; in ath5k_hw_proc_2word_tx_status()
477 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN) in ath5k_hw_proc_2word_tx_status()
478 ts->ts_status |= AR5K_TXERR_FIFO; in ath5k_hw_proc_2word_tx_status()
480 if (tx_status->tx_status_0 & AR5K_DESC_TX_STATUS0_FILTERED) in ath5k_hw_proc_2word_tx_status()
481 ts->ts_status |= AR5K_TXERR_FILT; in ath5k_hw_proc_2word_tx_status()
488 * ath5k_hw_proc_4word_tx_status() - Process a tx status descriptor on 5212
491 * @ts: The &struct ath5k_tx_status
496 struct ath5k_tx_status *ts) in ath5k_hw_proc_4word_tx_status() argument
501 tx_status = &desc->ud.ds_tx5212.tx_stat; in ath5k_hw_proc_4word_tx_status()
503 txstat1 = READ_ONCE(tx_status->tx_status_1); in ath5k_hw_proc_4word_tx_status()
507 return -EINPROGRESS; in ath5k_hw_proc_4word_tx_status()
509 txstat0 = READ_ONCE(tx_status->tx_status_0); in ath5k_hw_proc_4word_tx_status()
514 ts->ts_tstamp = AR5K_REG_MS(txstat0, in ath5k_hw_proc_4word_tx_status()
516 ts->ts_shortretry = AR5K_REG_MS(txstat0, in ath5k_hw_proc_4word_tx_status()
518 ts->ts_final_retry = AR5K_REG_MS(txstat0, in ath5k_hw_proc_4word_tx_status()
520 ts->ts_seqnum = AR5K_REG_MS(txstat1, in ath5k_hw_proc_4word_tx_status()
522 ts->ts_rssi = AR5K_REG_MS(txstat1, in ath5k_hw_proc_4word_tx_status()
524 ts->ts_antenna = (txstat1 & in ath5k_hw_proc_4word_tx_status()
526 ts->ts_status = 0; in ath5k_hw_proc_4word_tx_status()
528 ts->ts_final_idx = AR5K_REG_MS(txstat1, in ath5k_hw_proc_4word_tx_status()
531 /* TX error */ in ath5k_hw_proc_4word_tx_status()
534 ts->ts_status |= AR5K_TXERR_XRETRY; in ath5k_hw_proc_4word_tx_status()
537 ts->ts_status |= AR5K_TXERR_FIFO; in ath5k_hw_proc_4word_tx_status()
540 ts->ts_status |= AR5K_TXERR_FILT; in ath5k_hw_proc_4word_tx_status()
552 * ath5k_hw_setup_rx_desc() - Initialize an rx control descriptor
565 rx_ctl = &desc->ud.ds_rx.rx_ctl; in ath5k_hw_setup_rx_desc()
574 memset(&desc->ud.ds_rx, 0, sizeof(struct ath5k_hw_all_rx_desc)); in ath5k_hw_setup_rx_desc()
577 return -EINVAL; in ath5k_hw_setup_rx_desc()
580 rx_ctl->rx_control_1 = size & AR5K_DESC_RX_CTL1_BUF_LEN; in ath5k_hw_setup_rx_desc()
583 rx_ctl->rx_control_1 |= AR5K_DESC_RX_CTL1_INTREQ; in ath5k_hw_setup_rx_desc()
589 * ath5k_hw_proc_5210_rx_status() - Process the rx status descriptor on 5210/1
597 * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e
607 rx_status = &desc->ud.ds_rx.rx_stat; in ath5k_hw_proc_5210_rx_status()
610 if (unlikely(!(rx_status->rx_status_1 & in ath5k_hw_proc_5210_rx_status()
612 return -EINPROGRESS; in ath5k_hw_proc_5210_rx_status()
619 rs->rs_datalen = rx_status->rx_status_0 & in ath5k_hw_proc_5210_rx_status()
621 rs->rs_rssi = AR5K_REG_MS(rx_status->rx_status_0, in ath5k_hw_proc_5210_rx_status()
623 rs->rs_rate = AR5K_REG_MS(rx_status->rx_status_0, in ath5k_hw_proc_5210_rx_status()
625 rs->rs_more = !!(rx_status->rx_status_0 & in ath5k_hw_proc_5210_rx_status()
632 rs->rs_tstamp = AR5K_REG_MS(rx_status->rx_status_1, in ath5k_hw_proc_5210_rx_status()
635 if (ah->ah_version == AR5K_AR5211) in ath5k_hw_proc_5210_rx_status()
636 rs->rs_antenna = AR5K_REG_MS(rx_status->rx_status_0, in ath5k_hw_proc_5210_rx_status()
639 rs->rs_antenna = (rx_status->rx_status_0 & in ath5k_hw_proc_5210_rx_status()
646 if (rx_status->rx_status_1 & AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID) in ath5k_hw_proc_5210_rx_status()
647 rs->rs_keyix = AR5K_REG_MS(rx_status->rx_status_1, in ath5k_hw_proc_5210_rx_status()
650 rs->rs_keyix = AR5K_RXKEYIX_INVALID; in ath5k_hw_proc_5210_rx_status()
655 if (!(rx_status->rx_status_1 & in ath5k_hw_proc_5210_rx_status()
657 if (rx_status->rx_status_1 & in ath5k_hw_proc_5210_rx_status()
659 rs->rs_status |= AR5K_RXERR_CRC; in ath5k_hw_proc_5210_rx_status()
662 if ((ah->ah_version == AR5K_AR5210) && in ath5k_hw_proc_5210_rx_status()
663 (rx_status->rx_status_1 & in ath5k_hw_proc_5210_rx_status()
665 rs->rs_status |= AR5K_RXERR_FIFO; in ath5k_hw_proc_5210_rx_status()
667 if (rx_status->rx_status_1 & in ath5k_hw_proc_5210_rx_status()
669 rs->rs_status |= AR5K_RXERR_PHY; in ath5k_hw_proc_5210_rx_status()
670 rs->rs_phyerr = AR5K_REG_MS(rx_status->rx_status_1, in ath5k_hw_proc_5210_rx_status()
674 if (rx_status->rx_status_1 & in ath5k_hw_proc_5210_rx_status()
676 rs->rs_status |= AR5K_RXERR_DECRYPT; in ath5k_hw_proc_5210_rx_status()
683 * ath5k_hw_proc_5212_rx_status() - Process the rx status descriptor on 5212
691 * Returns 0 on success or -EINPROGRESS in case we haven't received the who;e
702 rx_status = &desc->ud.ds_rx.rx_stat; in ath5k_hw_proc_5212_rx_status()
703 rxstat1 = READ_ONCE(rx_status->rx_status_1); in ath5k_hw_proc_5212_rx_status()
707 return -EINPROGRESS; in ath5k_hw_proc_5212_rx_status()
710 rxstat0 = READ_ONCE(rx_status->rx_status_0); in ath5k_hw_proc_5212_rx_status()
715 rs->rs_datalen = rxstat0 & AR5K_5212_RX_DESC_STATUS0_DATA_LEN; in ath5k_hw_proc_5212_rx_status()
716 rs->rs_rssi = AR5K_REG_MS(rxstat0, in ath5k_hw_proc_5212_rx_status()
718 rs->rs_rate = AR5K_REG_MS(rxstat0, in ath5k_hw_proc_5212_rx_status()
720 rs->rs_antenna = AR5K_REG_MS(rxstat0, in ath5k_hw_proc_5212_rx_status()
722 rs->rs_more = !!(rxstat0 & AR5K_5212_RX_DESC_STATUS0_MORE); in ath5k_hw_proc_5212_rx_status()
723 rs->rs_tstamp = AR5K_REG_MS(rxstat1, in ath5k_hw_proc_5212_rx_status()
730 rs->rs_keyix = AR5K_REG_MS(rxstat1, in ath5k_hw_proc_5212_rx_status()
733 rs->rs_keyix = AR5K_RXKEYIX_INVALID; in ath5k_hw_proc_5212_rx_status()
740 rs->rs_status |= AR5K_RXERR_CRC; in ath5k_hw_proc_5212_rx_status()
743 rs->rs_status |= AR5K_RXERR_PHY; in ath5k_hw_proc_5212_rx_status()
744 rs->rs_phyerr = AR5K_REG_MS(rxstat1, in ath5k_hw_proc_5212_rx_status()
746 if (!ah->ah_capabilities.cap_has_phyerr_counters) in ath5k_hw_proc_5212_rx_status()
747 ath5k_ani_phy_error_report(ah, rs->rs_phyerr); in ath5k_hw_proc_5212_rx_status()
751 rs->rs_status |= AR5K_RXERR_DECRYPT; in ath5k_hw_proc_5212_rx_status()
754 rs->rs_status |= AR5K_RXERR_MIC; in ath5k_hw_proc_5212_rx_status()
765 * ath5k_hw_init_desc_functions() - Init function pointers inside ah
775 if (ah->ah_version == AR5K_AR5212) { in ath5k_hw_init_desc_functions()
776 ah->ah_setup_tx_desc = ath5k_hw_setup_4word_tx_desc; in ath5k_hw_init_desc_functions()
777 ah->ah_proc_tx_desc = ath5k_hw_proc_4word_tx_status; in ath5k_hw_init_desc_functions()
778 ah->ah_proc_rx_desc = ath5k_hw_proc_5212_rx_status; in ath5k_hw_init_desc_functions()
779 } else if (ah->ah_version <= AR5K_AR5211) { in ath5k_hw_init_desc_functions()
780 ah->ah_setup_tx_desc = ath5k_hw_setup_2word_tx_desc; in ath5k_hw_init_desc_functions()
781 ah->ah_proc_tx_desc = ath5k_hw_proc_2word_tx_status; in ath5k_hw_init_desc_functions()
782 ah->ah_proc_rx_desc = ath5k_hw_proc_5210_rx_status; in ath5k_hw_init_desc_functions()
784 return -ENOTSUPP; in ath5k_hw_init_desc_functions()