Lines Matching +full:0 +full:x00a34000
36 #define HAL_SHADOW_BASE_ADDR 0x000008fc
44 #define HAL_SEQ_WCSS_UMAC_OFFSET 0x00a00000
45 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000
46 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000
47 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x01b80000
48 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x01b81000
49 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x01b82000
50 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x01b83000
51 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000
53 #define HAL_CE_WFSS_CE_REG_BASE 0x01b80000
55 #define HAL_TCL_SW_CONFIG_BANK_ADDR 0x00a4408c
58 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000020
59 #define HAL_TCL1_RING_DSCP_TID_MAP 0x00000240
60 #define HAL_TCL1_RING_BASE_LSB 0x00000900
61 #define HAL_TCL1_RING_BASE_MSB 0x00000904
79 #define HAL_TCL2_RING_BASE_LSB 0x00000978
105 #define HAL_TCL1_RING_HP 0x00002000
106 #define HAL_TCL1_RING_TP 0x00002004
107 #define HAL_TCL2_RING_HP 0x00002008
108 #define HAL_TCL_RING_HP 0x00002028
116 #define HAL_TCL_STATUS_RING_HP 0x00002048
119 #define HAL_TCL_PPE2TCL1_RING_BASE_LSB 0x00000c48
120 #define HAL_TCL_PPE2TCL1_RING_HP 0x00002038
125 #define HAL_WBM_PPE_RELEASE_RING_HP 0x00003020
128 #define HAL_REO1_GEN_ENABLE 0x00000000
131 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004
132 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008
133 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c
134 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010
159 #define HAL_REO1_RING_HP 0x00003048
160 #define HAL_REO1_RING_TP 0x0000304c
161 #define HAL_REO2_RING_HP 0x00003050
170 #define HAL_REO_SW0_RING_HP 0x00003088
177 #define HAL_REO_CMD_HP 0x00003020
186 #define HAL_SW2REO_RING_HP 0x00003028
187 #define HAL_SW2REO1_RING_HP 0x00003030
190 #define HAL_CE_SRC_RING_BASE_LSB 0x00000000
191 #define HAL_CE_DST_RING_BASE_LSB 0x00000000
192 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058
193 #define HAL_CE_DST_RING_CTRL 0x000000b0
196 #define HAL_CE_DST_RING_HP 0x00000400
197 #define HAL_CE_DST_STATUS_RING_HP 0x00000408
202 #define HAL_REO_STATUS_HP 0x000030a8
229 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b8
238 #define HAL_WBM_SW_RELEASE_RING_HP 0x00003010
239 #define HAL_WBM_SW1_RELEASE_RING_HP 0x00003018
249 #define HAL_WBM0_RELEASE_RING_HP 0x000030c8
250 #define HAL_WBM1_RELEASE_RING_HP 0x000030d0
253 #define HAL_WBM_SW_COOKIE_CFG0 0x00000040
254 #define HAL_WBM_SW_COOKIE_CFG1 0x00000044
255 #define HAL_WBM_SW_COOKIE_CFG2 0x00000090
256 #define HAL_WBM_SW_COOKIE_CONVERT_CFG 0x00000094
258 #define HAL_WBM_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0)
262 #define HAL_WBM_SW_COOKIE_CFG_RELEASE_PATH_EN BIT(0)
275 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
276 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
277 #define HAL_TCL1_RING_MISC_MSI_RING_ID_DISABLE BIT(0)
284 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)
285 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0)
287 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
289 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0)
290 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0)
301 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0)
303 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0)
309 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)
311 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0)
316 #define HAL_REO1_SW_COOKIE_CFG_CMEM_BASE_ADDR_MSB GENMASK(7, 0)
324 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0)
326 #define HAL_ADDR_LSB_REG_MASK 0xffffffff
334 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0)
341 #define HAL_WBM_IDLE_LINK_RING_MISC_RIND_ID_DISABLE BIT(0)
343 #define BASE_ADDR_MATCH_TAG_VAL 0x5
345 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff
346 #define HAL_REO_REO2SW0_RING_BASE_MSB_RING_SIZE 0x000fffff
347 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff
348 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff
349 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
350 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff
351 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff
352 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
353 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff
354 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff
355 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff
356 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x000fffff
357 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff
358 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff
359 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff
360 #define HAL_RXDMA_RING_MAX_SIZE_BE 0x000fffff
361 #define HAL_WBM2PPE_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff
369 HAL_SRNG_RING_ID_REO2SW0 = 0,
495 #define HAL_SRNG_REG_GRP_R0 0
554 HAL_REO_CMD_GET_QUEUE_STATS = 0,
573 HAL_REO_CMD_SUCCESS = 0,
577 HAL_REO_CMD_DRAIN = 0xff,
609 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008
610 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010
611 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020
612 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000
613 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000
614 #define HAL_SRNG_FLAGS_HIGH_THRESH_INTR_EN 0x00080000
615 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000
774 * descriptor list, where the device 0 WBM is chosen in case of a multi-device config
780 * @HAL_RX_BUF_RBM_SW0_BM: For ring 0 -- returned to host
804 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000
806 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0)
893 #define HAL_HASH_ROUTING_RING_TCL 0
914 u32 rx_bitmap[8]; /* Bitmap from 0-255 */