ath/ath10k/rx_desc.h

14 	RX_ATTENTION_FLAGS_FIRST_MPDU          = BIT(0),
58  *		0.  The PPDU start status will only be valid when this bit
67  *		address 1 bit 0 is set indicating mcast/bcast and the BSSID
228  *		ring 0.  Field is filled in by the RX_DMA.
244 	HTT_RX_MPDU_ENCRYPT_WEP40            = 0,
257 #define RX_MPDU_START_INFO0_PEER_IDX_MASK     0x000007ff
258 #define RX_MPDU_START_INFO0_PEER_IDX_LSB      0
259 #define RX_MPDU_START_INFO0_SEQ_NUM_MASK      0x0fff0000
261 #define RX_MPDU_START_INFO0_ENCRYPT_TYPE_MASK 0xf0000000
269 #define RX_MPDU_START_INFO1_TID_MASK 0xf0000000
319  *		0: WEP40
330  *		Bits [31:0] of the PN number extracted from the IV field
331  *		WEP: IV = {key_id_octet, pn2, pn1, pn0}.  Only pn[23:0] is
334  *		WEPSeed[1], pn1}.  Only pn[47:0] is valid.
335  *		AES-CCM: IV = {pn5, pn4, pn3, pn2, key_id_octet, 0x0, pn1,
336  *		pn0}.  Only pn[47:0] is valid.
337  *		WAPI: IV = {key_id_octet, 0x0, pn15, pn14, pn13, pn12, pn11,
340  *		pn[47:0] are valid.
362 #define RX_MPDU_END_INFO0_RESERVED_0_MASK     0x00001fff
363 #define RX_MPDU_END_INFO0_RESERVED_0_LSB      0
364 #define RX_MPDU_END_INFO0_POST_DELIM_CNT_MASK 0x0fff0000
416 #define RX_MSDU_START_INFO0_MSDU_LENGTH_MASK    0x00003fff
417 #define RX_MSDU_START_INFO0_MSDU_LENGTH_LSB     0
418 #define RX_MSDU_START_INFO0_IP_OFFSET_MASK      0x000fc000
420 #define RX_MSDU_START_INFO0_RING_MASK_MASK      0x00f00000
422 #define RX_MSDU_START_INFO0_TCP_UDP_OFFSET_MASK 0x7f000000
425 #define RX_MSDU_START_INFO1_MSDU_NUMBER_MASK    0x000000ff
426 #define RX_MSDU_START_INFO1_MSDU_NUMBER_LSB     0
427 #define RX_MSDU_START_INFO1_DECAP_FORMAT_MASK   0x00000300
429 #define RX_MSDU_START_INFO1_SA_IDX_MASK         0x07ff0000
438 #define RX_MSDU_START_INFO2_DA_IDX_MASK         0x000007ff
439 #define RX_MSDU_START_INFO2_DA_IDX_LSB          0
440 #define RX_MSDU_START_INFO2_IP_PROTO_FIELD_MASK 0x00ff0000
448  *     - 0 bytes for no security
458 	RX_MSDU_DECAP_RAW = 0,
520  *		Only valid if tcp_prot or udp_prot is set.  The value 0
528  *		IPv4 option: dest_addr[31:0], src_addr [31:0], {24'b0,
529  *		protocol[7:0]}.
530  *		IPv6 option: dest_addr[127:0], src_addr [127:0], {24'b0,
531  *		next_header[7:0]}
532  *		UDP case: sort_port[15:0], dest_port[15:0]
533  *		TCP case: sort_port[15:0], dest_port[15:0],
534  *		{header_length[3:0], 6'b0, flags[5:0], window_size[15:0]},
535  *		{16'b0, urgent_ptr[15:0]}, all options except 32-bit
545  *		0: RAW: No decapsulation
571  *		the TCP payload is 0.
581 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_MASK 0x00003fff
582 #define RX_MSDU_END_INFO0_REPORTED_MPDU_LENGTH_LSB  0
598 #define RX_MSDU_END_INFO1_TCP_FLAG_MASK     0x000001ff
599 #define RX_MSDU_END_INFO1_TCP_FLAG_LSB      0
600 #define RX_MSDU_END_INFO1_L3_HDR_PAD_MASK   0x00001c00
602 #define RX_MSDU_END_INFO1_WINDOW_SIZE_MASK  0xffff0000
606 #define RX_MSDU_END_INFO2_DA_OFFSET_MASK    0x0000003f
607 #define RX_MSDU_END_INFO2_DA_OFFSET_LSB     0
608 #define RX_MSDU_END_INFO2_SA_OFFSET_MASK    0x00000fc0
610 #define RX_MSDU_END_INFO2_TYPE_OFFSET_MASK  0x0003f000
667  *		WAPI PN bits [63:0] are in the pn field of the rx_mpdu_start
690  *		have both first_mpdu and last_mpdu bits set to 0.
713 #define HTT_RX_PPDU_START_PREAMBLE_LEGACY        0x04
714 #define HTT_RX_PPDU_START_PREAMBLE_HT            0x08
715 #define HTT_RX_PPDU_START_PREAMBLE_HT_WITH_TXBF  0x09
716 #define HTT_RX_PPDU_START_PREAMBLE_VHT           0x0C
717 #define HTT_RX_PPDU_START_PREAMBLE_VHT_WITH_TXBF 0x0D
719 #define RX_PPDU_START_INFO0_IS_GREENFIELD BIT(0)
721 #define RX_PPDU_START_INFO1_L_SIG_RATE_MASK    0x0000000f
722 #define RX_PPDU_START_INFO1_L_SIG_RATE_LSB     0
723 #define RX_PPDU_START_INFO1_L_SIG_LENGTH_MASK  0x0001ffe0
725 #define RX_PPDU_START_INFO1_L_SIG_TAIL_MASK    0x00fc0000
727 #define RX_PPDU_START_INFO1_PREAMBLE_TYPE_MASK 0xff000000
732 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_MASK 0x00ffffff
733 #define RX_PPDU_START_INFO2_HT_SIG_VHT_SIG_A_1_LSB  0
735 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_MASK 0x00ffffff
736 #define RX_PPDU_START_INFO3_HT_SIG_VHT_SIG_A_2_LSB  0
739 #define RX_PPDU_START_INFO4_VHT_SIG_B_MASK 0x1fffffff
740 #define RX_PPDU_START_INFO4_VHT_SIG_B_LSB  0
742 #define RX_PPDU_START_INFO5_SERVICE_MASK 0x0000ffff
743 #define RX_PPDU_START_INFO5_SERVICE_LSB  0
767  *		RSSI of RX PPDU on chain 0 of primary 20 MHz bandwidth.
768  *		Value of 0x80 indicates invalid.
771  *		RSSI of RX PPDU on chain 0 of secondary 20 MHz bandwidth.
772  *		Value of 0x80 indicates invalid.
775  *		RSSI of RX PPDU on chain 0 of secondary 40 MHz bandwidth.
776  *		Value of 0x80 indicates invalid.
779  *		RSSI of RX PPDU on chain 0 of secondary 80 MHz bandwidth.
780  *		Value of 0x80 indicates invalid.
784  *		Value of 0x80 indicates invalid.
788  *		Value of 0x80 indicates invalid.
792  *		Value of 0x80 indicates invalid.
796  *		Value of 0x80 indicates invalid.
800  *		Value of 0x80 indicates invalid.
804  *		Value of 0x80 indicates invalid.
808  *		Value of 0x80 indicates invalid.
812  *		Value of 0x80 indicates invalid.
816  *		Value of 0x80 indicates invalid.
820  *		Value of 0x80 indicates invalid.
824  *		Value of 0x80 indicates invalid.
828  *		Value of 0x80 indicates invalid.
832  *		bandwidths.  Value of 0x80 indicates invalid.
835  *		Reserved: HW should fill with 0, FW should ignore.
841  *		Reserved: HW should fill with 0, FW should ignore.
844  *		If l_sig_rate_select is 0:
845  *		0x8: OFDM 48 Mbps
846  *		0x9: OFDM 24 Mbps
847  *		0xA: OFDM 12 Mbps
848  *		0xB: OFDM 6 Mbps
849  *		0xC: OFDM 54 Mbps
850  *		0xD: OFDM 36 Mbps
851  *		0xE: OFDM 18 Mbps
852  *		0xF: OFDM 9 Mbps
854  *		0x8: CCK 11 Mbps long preamble
855  *		0x9: CCK 5.5 Mbps long preamble
856  *		0xA: CCK 2 Mbps long preamble
857  *		0xB: CCK 1 Mbps long preamble
858  *		0xC: CCK 11 Mbps short preamble
859  *		0xD: CCK 5.5 Mbps short preamble
860  *		0xE: CCK 2 Mbps short preamble
877  *		0x4: Legacy (OFDM/CCK)
878  *		0x8: HT
879  *		0x9: HT with TxBF
880  *		0xC: VHT
881  *		0xD: VHT with TxBF
882  *		0x80 - 0xFF: Reserved for special baseband data types such
886  *		If preamble_type == 0x8 or 0x9
888  *		If preamble_type == 0xC or 0xD
894  *		Reserved: HW should fill with 0, FW should ignore.
897  *		If preamble_type == 0x8 or 0x9
899  *		If preamble_type == 0xC or 0xD
909  *		Reserved: HW should fill with 0, FW should ignore.
913  *		0s since the BB does not plan on decoding VHT SIG-B.
916  *		Reserved: HW should fill with 0, FW should ignore.
920  *		packets will have service field of 0.
923  *		Reserved: HW should fill with 0, FW should ignore.
926 #define RX_PPDU_END_FLAGS_PHY_ERR             BIT(0)
930 #define RX_PPDU_END_INFO0_RX_ANTENNA_MASK     0x00ffffff
931 #define RX_PPDU_END_INFO0_RX_ANTENNA_LSB      0
935 #define RX_PPDU_END_INFO1_PEER_IDX_MASK       0x1ffc
937 #define RX_PPDU_END_INFO1_BB_DATA             BIT(0)
971 #define RX_PPDU_END_RTT_CORRELATION_VALUE_MASK 0x00ffffff
972 #define RX_PPDU_END_RTT_CORRELATION_VALUE_LSB  0
973 #define RX_PPDU_END_RTT_UNUSED_MASK            0x7f000000
987 #define RX_PKT_END_INFO0_RX_SUCCESS              BIT(0)
994 #define RX_LOCATION_INFO_RTT_CORR_VAL_MASK       0x0001ffff
995 #define RX_LOCATION_INFO_RTT_CORR_VAL_LSB        0
996 #define RX_LOCATION_INFO_FAC_STATUS_MASK         0x000c0000
998 #define RX_LOCATION_INFO_PKT_BW_MASK             0x00700000
1000 #define RX_LOCATION_INFO_RTT_TX_FRAME_PHASE_MASK 0x01800000
1020 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_MASK		0x00003fff
1021 #define RX_LOCATION_INFO0_RTT_FAC_LEGACY_LSB		0
1022 #define RX_LOCATION_INFO0_RTT_FAC_VHT_MASK		0x1fff8000
1024 #define RX_LOCATION_INFO0_RTT_STRONGEST_CHAIN_MASK	0xc0000000
1029 #define RX_LOCATION_INFO1_RTT_PREAMBLE_TYPE_MASK	0x0000000c
1031 #define RX_LOCATION_INFO1_PKT_BW_MASK			0x00000030
1033 #define RX_LOCATION_INFO1_SKIP_P_SKIP_BTCF_MASK		0x0000ff00
1035 #define RX_LOCATION_INFO1_RTT_MSC_RATE_MASK		0x000f0000
1037 #define RX_LOCATION_INFO1_RTT_PBD_LEG_BW_MASK		0x00300000
1039 #define RX_LOCATION_INFO1_TIMING_BACKOFF_MASK		0x07c00000
1041 #define RX_LOCATION_INFO1_RTT_TX_FRAME_PHASE_MASK	0x18000000
1043 #define RX_LOCATION_INFO1_RTT_CFR_STATUS		BIT(0)
1095 	RX_PHY_PPDU_END_INFO1_ERR_VHT_NDP            = BIT(0),
1116 #define RX_PPDU_END_RX_TIMING_OFFSET_MASK          0x00000fff
1117 #define RX_PPDU_END_RX_TIMING_OFFSET_LSB           0
1119 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_MASK        0x00ffffff
1120 #define RX_PPDU_END_RX_INFO_RX_ANTENNA_LSB         0
1182  *		EVM for pilot 0.  Contain EVM for streams: 0, 1, 2 and 3.
1185  *		EVM for pilot 1.  Contain EVM for streams: 0, 1, 2 and 3.
1188  *		EVM for pilot 2.  Contain EVM for streams: 0, 1, 2 and 3.
1191  *		EVM for pilot 3.  Contain EVM for streams: 0, 1, 2 and 3.
1194  *		EVM for pilot 4.  Contain EVM for streams: 0, 1, 2 and 3.
1197  *		EVM for pilot 5.  Contain EVM for streams: 0, 1, 2 and 3.
1200  *		EVM for pilot 6.  Contain EVM for streams: 0, 1, 2 and 3.
1203  *		EVM for pilot 7.  Contain EVM for streams: 0, 1, 2 and 3.
1206  *		EVM for pilot 8.  Contain EVM for streams: 0, 1, 2 and 3.
1209  *		EVM for pilot 9.  Contain EVM for streams: 0, 1, 2 and 3.
1212  *		EVM for pilot 10.  Contain EVM for streams: 0, 1, 2 and 3.
1215  *		EVM for pilot 11.  Contain EVM for streams: 0, 1, 2 and 3.
1218  *		EVM for pilot 12.  Contain EVM for streams: 0, 1, 2 and 3.
1221  *		EVM for pilot 13.  Contain EVM for streams: 0, 1, 2 and 3.
1224  *		EVM for pilot 14.  Contain EVM for streams: 0, 1, 2 and 3.
1227  *		EVM for pilot 15.  Contain EVM for streams: 0, 1, 2 and 3.
1245  *		nsec.  The value starts at 0 and increments to 79 and
1246  *		returns to 0 and repeats.  This information is valid for
1264  *		Reserved: HW should fill with 0, FW should ignore.
1281  *		Reserved: HW should fill with 0, FW should ignore.
1285  *		PPDUs where the BB descriptor preamble type is 0x80 to 0xFF
1290  *		Reserved: HW should fill with 0, FW should ignore.
1296  *		to 0.
1299 #define FW_RX_DESC_INFO0_DISCARD  BIT(0)
1302 #define FW_RX_DESC_INFO0_EXT_MASK 0xC0
1309 #define FW_RX_DESC_FLAGS_FIRST_MSDU (1 << 0)