Lines Matching +full:0 +full:x8014
24 #define QCA988X_2_0_DEVICE_ID_UBNT (0x11ac)
25 #define QCA988X_2_0_DEVICE_ID (0x003c)
26 #define QCA6164_2_1_DEVICE_ID (0x0041)
27 #define QCA6174_2_1_DEVICE_ID (0x003e)
28 #define QCA6174_3_2_DEVICE_ID (0x0042)
29 #define QCA99X0_2_0_DEVICE_ID (0x0040)
30 #define QCA9888_2_0_DEVICE_ID (0x0056)
31 #define QCA9984_1_0_DEVICE_ID (0x0046)
32 #define QCA9377_1_0_DEVICE_ID (0x0042)
33 #define QCA9887_1_0_DEVICE_ID (0x0050)
36 #define QCA988X_HW_1_0_CHIP_ID_REV 0x0
39 #define QCA988X_HW_2_0_VERSION 0x4100016c
40 #define QCA988X_HW_2_0_CHIP_ID_REV 0x2
41 #define QCA988X_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA988X/hw2.0"
42 #define QCA988X_HW_2_0_PATCH_LOAD_ADDR 0x1234
45 #define QCA9887_HW_1_0_VERSION 0x4100016d
46 #define QCA9887_HW_1_0_CHIP_ID_REV 0
47 #define QCA9887_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9887/hw1.0"
48 #define QCA9887_HW_1_0_PATCH_LOAD_ADDR 0x1234
51 #define QCA6174_HW_1_0_VERSION 0x05000000
52 #define QCA6174_HW_1_1_VERSION 0x05000001
53 #define QCA6174_HW_1_3_VERSION 0x05000003
54 #define QCA6174_HW_2_1_VERSION 0x05010000
55 #define QCA6174_HW_3_0_VERSION 0x05020000
56 #define QCA6174_HW_3_2_VERSION 0x05030000
59 #define QCA9377_HW_1_0_DEV_VERSION 0x05020000
60 #define QCA9377_HW_1_1_DEV_VERSION 0x05020001
63 QCA6174_PCI_REV_1_1 = 0x11,
64 QCA6174_PCI_REV_1_3 = 0x13,
65 QCA6174_PCI_REV_2_0 = 0x20,
66 QCA6174_PCI_REV_3_0 = 0x30,
70 QCA6174_HW_1_0_CHIP_ID_REV = 0,
81 QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
82 QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
86 #define QCA6174_HW_2_1_PATCH_LOAD_ADDR 0x1234
88 #define QCA6174_HW_3_0_FW_DIR ATH10K_FW_DIR "/QCA6174/hw3.0"
89 #define QCA6174_HW_3_0_PATCH_LOAD_ADDR 0x1234
92 #define QCA99X0_HW_1_0_CHIP_ID_REV 0x0
95 #define QCA99X0_HW_2_0_DEV_VERSION 0x01000000
96 #define QCA99X0_HW_2_0_CHIP_ID_REV 0x1
97 #define QCA99X0_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA99X0/hw2.0"
98 #define QCA99X0_HW_2_0_PATCH_LOAD_ADDR 0x1234
101 #define QCA9984_HW_1_0_DEV_VERSION 0x1000000
102 #define QCA9984_HW_DEV_TYPE 0xa
103 #define QCA9984_HW_1_0_CHIP_ID_REV 0x0
104 #define QCA9984_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9984/hw1.0"
105 #define QCA9984_HW_1_0_PATCH_LOAD_ADDR 0x1234
108 #define QCA9888_HW_2_0_DEV_VERSION 0x1000000
109 #define QCA9888_HW_DEV_TYPE 0xc
110 #define QCA9888_HW_2_0_CHIP_ID_REV 0x0
111 #define QCA9888_HW_2_0_FW_DIR ATH10K_FW_DIR "/QCA9888/hw2.0"
112 #define QCA9888_HW_2_0_PATCH_LOAD_ADDR 0x1234
115 #define QCA9377_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA9377/hw1.0"
116 #define QCA9377_HW_1_0_PATCH_LOAD_ADDR 0x1234
119 #define QCA4019_HW_1_0_DEV_VERSION 0x01000000
120 #define QCA4019_HW_1_0_FW_DIR ATH10K_FW_DIR "/QCA4019/hw1.0"
121 #define QCA4019_HW_1_0_PATCH_LOAD_ADDR 0x1234
125 #define WCN3990_HW_1_0_FW_DIR ATH10K_FW_DIR "/WCN3990/hw1.0"
165 ATH10K_FW_IE_FW_VERSION = 0,
186 ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
200 ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
217 ATH10K_BD_IE_BOARD = 0,
222 ATH10K_BD_IE_BOARD_NAME = 0,
414 ATH10K_HW_TXRX_RAW = 0,
427 ATH10K_MCAST2UCAST_DISABLED = 0,
432 ATH10K_HW_RATE_OFDM_48M = 0,
443 ATH10K_HW_RATE_CCK_LP_11M = 0,
463 ATH10K_HW_CC_WRAP_DISABLED = 0,
466 * wraparound which resets to 0x7fffffff instead of 0. All
474 * by 1, i.e reset to 0x7fffffff, and other counters will be
484 ATH10K_HW_REFCLK_48_MHZ = 0,
665 return 0; in ath10k_tx_data_rssi_get_pad_bytes()
674 return 0; in ath10k_is_rssi_enable()
681 #define TARGET_DMA_BURST_SIZE 0
682 #define TARGET_MAC_AGGR_DELIM 0
687 #define TARGET_NUM_OFFLOAD_PEERS 0
688 #define TARGET_NUM_OFFLOAD_REORDER_BUFS 0
691 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
692 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
701 #define TARGET_NUM_MCAST_GROUPS 0
702 #define TARGET_NUM_MCAST_TABLE_ELEMS 0
705 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
706 #define TARGET_VOW_CONFIG 0
708 #define TARGET_MAX_FRAG_ENTRIES 0
714 #define TARGET_10X_DMA_BURST_SIZE 0
715 #define TARGET_10X_MAC_AGGR_DELIM 0
723 #define TARGET_10X_NUM_OFFLOAD_PEERS 0
724 #define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS 0
731 #define TARGET_10X_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
732 #define TARGET_10X_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2))
740 #define TARGET_10X_NUM_MCAST_GROUPS 0
741 #define TARGET_10X_NUM_MCAST_TABLE_ELEMS 0
745 #define TARGET_10X_VOW_CONFIG 0
747 #define TARGET_10X_MAX_FRAG_ENTRIES 0
750 #define TARGET_10_2_DMA_BURST_SIZE 0
781 #define TARGET_10_4_ACTIVE_PEERS 0
786 #define TARGET_10_4_NUM_OFFLOAD_PEERS 0
787 #define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS 0
807 #define TARGET_10_4_NUM_MCAST_GROUPS 0
808 #define TARGET_10_4_NUM_MCAST_TABLE_ELEMS 0
809 #define TARGET_10_4_MCAST2UCAST_MODE 0
814 #define TARGET_10_4_MAC_AGGR_DELIM 0
816 #define TARGET_10_4_VOW_CONFIG 0
820 #define TARGET_10_4_SMART_ANT_CAP 0
821 #define TARGET_10_4_BK_MIN_FREE 0
822 #define TARGET_10_4_BE_MIN_FREE 0
823 #define TARGET_10_4_VI_MIN_FREE 0
824 #define TARGET_10_4_VO_MIN_FREE 0
826 #define TARGET_10_4_THERMAL_THROTTLING_CONFIG 0
827 #define TARGET_10_4_ATF_CONFIG 0
829 #define TARGET_10_4_QWRAP_CONFIG 0
850 #define MSI_ASSIGN_FW 0
859 #define RTC_STATE_V_LSB 0
860 #define RTC_STATE_V_MASK 0x00000007
861 #define RTC_STATE_ADDRESS 0x0000
862 #define PCIE_SOC_WAKE_V_MASK 0x00000001
863 #define PCIE_SOC_WAKE_ADDRESS 0x0004
864 #define PCIE_SOC_WAKE_RESET 0x00000000
865 #define SOC_GLOBAL_RESET_ADDRESS 0x0008
869 #define MAC_COEX_BASE_ADDRESS 0x00006000
870 #define BT_COEX_BASE_ADDRESS 0x00007000
871 #define SOC_PCIE_BASE_ADDRESS 0x00008000
873 #define WLAN_UART_BASE_ADDRESS 0x0000c000
874 #define WLAN_SI_BASE_ADDRESS 0x00010000
875 #define WLAN_GPIO_BASE_ADDRESS 0x00014000
876 #define WLAN_ANALOG_INTF_BASE_ADDRESS 0x0001c000
878 #define EFUSE_BASE_ADDRESS 0x00030000
879 #define FPGA_REG_BASE_ADDRESS 0x00039000
880 #define WLAN_UART2_BASE_ADDRESS 0x00054c00
890 #define DBI_BASE_ADDRESS 0x00060000
891 #define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS 0x0006c000
894 #define SOC_RESET_CONTROL_ADDRESS 0x00000000
895 #define SOC_RESET_CONTROL_OFFSET 0x00000000
898 #define SOC_RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
899 #define SOC_CPU_CLOCK_OFFSET 0x00000020
900 #define SOC_CPU_CLOCK_STANDARD_LSB 0
901 #define SOC_CPU_CLOCK_STANDARD_MASK 0x00000003
902 #define SOC_CLOCK_CONTROL_OFFSET 0x00000028
903 #define SOC_CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
904 #define SOC_SYSTEM_SLEEP_OFFSET 0x000000c4
905 #define SOC_LPO_CAL_OFFSET 0x000000e0
907 #define SOC_LPO_CAL_ENABLE_MASK 0x00100000
908 #define SOC_LF_TIMER_CONTROL0_ADDRESS 0x00000050
909 #define SOC_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
913 #define SOC_CHIP_ID_REV_MASK 0x00000f00
915 #define WLAN_RESET_CONTROL_COLD_RST_MASK 0x00000008
916 #define WLAN_RESET_CONTROL_WARM_RST_MASK 0x00000004
917 #define WLAN_SYSTEM_SLEEP_DISABLE_LSB 0
918 #define WLAN_SYSTEM_SLEEP_DISABLE_MASK 0x00000001
920 #define WLAN_GPIO_PIN0_ADDRESS 0x00000028
922 #define WLAN_GPIO_PIN0_CONFIG_MASK 0x00007800
924 #define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060
925 #define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
926 #define WLAN_GPIO_PIN1_CONFIG_MASK 0x00007800
927 #define WLAN_GPIO_PIN10_ADDRESS 0x00000050
928 #define WLAN_GPIO_PIN11_ADDRESS 0x00000054
929 #define WLAN_GPIO_PIN12_ADDRESS 0x00000058
930 #define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
932 #define CLOCK_GPIO_OFFSET 0xffffffff
933 #define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
934 #define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0
936 #define SI_CONFIG_OFFSET 0x00000000
938 #define SI_CONFIG_ERR_INT_MASK 0x00080000
940 #define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
942 #define SI_CONFIG_I2C_MASK 0x00010000
944 #define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
946 #define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
948 #define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
949 #define SI_CONFIG_DIVIDER_LSB 0
950 #define SI_CONFIG_DIVIDER_MASK 0x0000000f
951 #define SI_CS_OFFSET 0x00000004
953 #define SI_CS_DONE_ERR_MASK 0x00000400
955 #define SI_CS_DONE_INT_MASK 0x00000200
957 #define SI_CS_START_MASK 0x00000100
959 #define SI_CS_RX_CNT_MASK 0x000000f0
960 #define SI_CS_TX_CNT_LSB 0
961 #define SI_CS_TX_CNT_MASK 0x0000000f
963 #define SI_TX_DATA0_OFFSET 0x00000008
964 #define SI_TX_DATA1_OFFSET 0x0000000c
965 #define SI_RX_DATA0_OFFSET 0x00000010
966 #define SI_RX_DATA1_OFFSET 0x00000014
968 #define CORE_CTRL_CPU_INTR_MASK 0x00002000
969 #define CORE_CTRL_PCIE_REG_31_MASK 0x00000800
970 #define CORE_CTRL_ADDRESS 0x0000
971 #define PCIE_INTR_ENABLE_ADDRESS 0x0008
972 #define PCIE_INTR_CAUSE_ADDRESS 0x000c
975 #define CPU_INTR_ADDRESS 0x0010
976 #define FW_RAM_CONFIG_ADDRESS 0x0018
984 #define FW_IND_HOST_READY 0x80000000
990 #define DRAM_BASE_ADDRESS 0x00400000
992 #define PCIE_BAR_REG_ADDRESS 0x40030
994 #define MISSING 0
1013 #define LOCAL_SCRATCH_OFFSET 0x18
1068 #define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010
1070 #define QCA9887_EEPROM_SELECT_READ 0xa10000a0
1071 #define QCA9887_EEPROM_ADDR_HI_MASK 0x0000ff00
1073 #define QCA9887_EEPROM_ADDR_LO_MASK 0x00ff0000
1076 #define MBOX_RESET_CONTROL_ADDRESS 0x00000000
1077 #define MBOX_HOST_INT_STATUS_ADDRESS 0x00000800
1079 #define MBOX_HOST_INT_STATUS_ERROR_MASK 0x00000080
1081 #define MBOX_HOST_INT_STATUS_CPU_MASK 0x00000040
1083 #define MBOX_HOST_INT_STATUS_COUNTER_MASK 0x00000010
1084 #define MBOX_CPU_INT_STATUS_ADDRESS 0x00000801
1085 #define MBOX_ERROR_INT_STATUS_ADDRESS 0x00000802
1087 #define MBOX_ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
1089 #define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
1090 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
1091 #define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
1092 #define MBOX_COUNTER_INT_STATUS_ADDRESS 0x00000803
1093 #define MBOX_COUNTER_INT_STATUS_COUNTER_LSB 0
1094 #define MBOX_COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
1095 #define MBOX_RX_LOOKAHEAD_VALID_ADDRESS 0x00000805
1096 #define MBOX_INT_STATUS_ENABLE_ADDRESS 0x00000828
1098 #define MBOX_INT_STATUS_ENABLE_ERROR_MASK 0x00000080
1100 #define MBOX_INT_STATUS_ENABLE_CPU_MASK 0x00000040
1102 #define MBOX_INT_STATUS_ENABLE_INT_MASK 0x00000020
1104 #define MBOX_INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
1105 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB 0
1106 #define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
1107 #define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS 0x00000819
1108 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB 0
1109 #define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
1110 #define MBOX_CPU_STATUS_ENABLE_ASSERT_MASK 0x00000001
1111 #define MBOX_ERROR_STATUS_ENABLE_ADDRESS 0x0000081a
1113 #define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
1114 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
1115 #define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
1116 #define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000081b
1117 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
1118 #define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
1119 #define MBOX_COUNT_ADDRESS 0x00000820
1120 #define MBOX_COUNT_DEC_ADDRESS 0x00000840
1121 #define MBOX_WINDOW_DATA_ADDRESS 0x00000874
1122 #define MBOX_WINDOW_WRITE_ADDR_ADDRESS 0x00000878
1123 #define MBOX_WINDOW_READ_ADDR_ADDRESS 0x0000087c
1124 #define MBOX_CPU_DBG_SEL_ADDRESS 0x00000883
1125 #define MBOX_CPU_DBG_ADDRESS 0x00000884
1126 #define MBOX_RTC_BASE_ADDRESS 0x00000000
1127 #define MBOX_GPIO_BASE_ADDRESS 0x00005000
1128 #define MBOX_MBOX_BASE_ADDRESS 0x00008000
1139 #define WAVE1_PCU_ACK_CTS_TIMEOUT 0x8014
1140 #define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX 0x00003FFF
1141 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK 0x00003FFF
1142 #define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB 0
1143 #define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK 0x3FFF0000
1146 #define WAVE1_PCU_GBL_IFS_SLOT 0x1070
1147 #define WAVE1_PCU_GBL_IFS_SLOT_MASK 0x0000FFFF
1148 #define WAVE1_PCU_GBL_IFS_SLOT_MAX 0x0000FFFF
1149 #define WAVE1_PCU_GBL_IFS_SLOT_LSB 0
1150 #define WAVE1_PCU_GBL_IFS_SLOT_RESV0 0xFFFF0000
1152 #define WAVE1_PHYCLK 0x801C
1153 #define WAVE1_PHYCLK_USEC_MASK 0x0000007F
1154 #define WAVE1_PHYCLK_USEC_LSB 0
1157 #define SOC_CORE_CLK_CTRL_OFFSET 0x00000114
1158 #define SOC_CORE_CLK_CTRL_DIV_LSB 0
1159 #define SOC_CORE_CLK_CTRL_DIV_MASK 0x00000007
1161 #define EFUSE_OFFSET 0x0000032c
1163 #define EFUSE_XTAL_SEL_MASK 0x00000700
1165 #define BB_PLL_CONFIG_OFFSET 0x000002f4
1166 #define BB_PLL_CONFIG_FRAC_LSB 0
1167 #define BB_PLL_CONFIG_FRAC_MASK 0x0003ffff
1169 #define BB_PLL_CONFIG_OUTDIV_MASK 0x001c0000
1171 #define WLAN_PLL_SETTLE_OFFSET 0x0018
1172 #define WLAN_PLL_SETTLE_TIME_LSB 0
1173 #define WLAN_PLL_SETTLE_TIME_MASK 0x000007ff
1175 #define WLAN_PLL_CONTROL_OFFSET 0x0014
1176 #define WLAN_PLL_CONTROL_DIV_LSB 0
1177 #define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff
1179 #define WLAN_PLL_CONTROL_REFDIV_MASK 0x00003c00
1181 #define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000
1183 #define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000
1185 #define RTC_SYNC_STATUS_OFFSET 0x0244
1187 #define RTC_SYNC_STATUS_PLL_CHANGING_MASK 0x00000020
1190 /* CPU_ADDR_MSB is a register, bit[3:0] is to specify which memory
1192 * If host wants to access 0xX12345 at target, then CPU_ADDR_MSB[3:0]
1193 * is 0xX.
1194 * The following MACROs are defined to get the 0xX and the size limit.
1198 #define REGION_ACCESS_SIZE_LIMIT 0x100000