Lines Matching +full:hw +full:- +full:settle +full:- +full:time +full:- +full:us
1 // SPDX-License-Identifier: ISC
3 * Copyright (c) 2014-2017 Qualcomm Atheros, Inc.
11 #include "hw.h"
13 #include "wmi-ops.h"
557 survey->filled |= SURVEY_INFO_TIME | in ath10k_hw_fill_survey_time()
560 wraparound_type = ar->hw_params.cc_wraparound_type; in ath10k_hw_fill_survey_time()
567 survey->filled &= ~SURVEY_INFO_TIME_BUSY; in ath10k_hw_fill_survey_time()
582 cc -= cc_prev - cc_fix; in ath10k_hw_fill_survey_time()
583 rcc -= rcc_prev - rcc_fix; in ath10k_hw_fill_survey_time()
585 survey->time = CCNT_TO_MSEC(ar, cc); in ath10k_hw_fill_survey_time()
586 survey->time_busy = CCNT_TO_MSEC(ar, rcc); in ath10k_hw_fill_survey_time()
605 mutex_lock(&ar->conf_mutex); in ath10k_hw_qca988x_set_coverage_class()
608 if ((ar->state != ATH10K_STATE_ON) && in ath10k_hw_qca988x_set_coverage_class()
609 (ar->state != ATH10K_STATE_RESTARTED)) { in ath10k_hw_qca988x_set_coverage_class()
610 spin_lock_bh(&ar->data_lock); in ath10k_hw_qca988x_set_coverage_class()
612 ar->fw_coverage.coverage_class = value; in ath10k_hw_qca988x_set_coverage_class()
613 spin_unlock_bh(&ar->data_lock); in ath10k_hw_qca988x_set_coverage_class()
629 value = ar->fw_coverage.coverage_class; in ath10k_hw_qca988x_set_coverage_class()
634 if (value == ar->fw_coverage.coverage_class && in ath10k_hw_qca988x_set_coverage_class()
635 slottime_reg == ar->fw_coverage.reg_slottime_conf && in ath10k_hw_qca988x_set_coverage_class()
636 timeout_reg == ar->fw_coverage.reg_ack_cts_timeout_conf && in ath10k_hw_qca988x_set_coverage_class()
637 phyclk_reg == ar->fw_coverage.reg_phyclk) in ath10k_hw_qca988x_set_coverage_class()
641 if (slottime_reg != ar->fw_coverage.reg_slottime_conf) in ath10k_hw_qca988x_set_coverage_class()
642 ar->fw_coverage.reg_slottime_orig = slottime_reg; in ath10k_hw_qca988x_set_coverage_class()
643 if (timeout_reg != ar->fw_coverage.reg_ack_cts_timeout_conf) in ath10k_hw_qca988x_set_coverage_class()
644 ar->fw_coverage.reg_ack_cts_timeout_orig = timeout_reg; in ath10k_hw_qca988x_set_coverage_class()
645 ar->fw_coverage.reg_phyclk = phyclk_reg; in ath10k_hw_qca988x_set_coverage_class()
648 slottime_reg = ar->fw_coverage.reg_slottime_orig; in ath10k_hw_qca988x_set_coverage_class()
649 timeout_reg = ar->fw_coverage.reg_ack_cts_timeout_orig; in ath10k_hw_qca988x_set_coverage_class()
663 … "failed to set coverage class: expected slot time of 9 or 20us in HW register. It is %uus.\n", in ath10k_hw_qca988x_set_coverage_class()
670 * delay (3us per coverage class). in ath10k_hw_qca988x_set_coverage_class()
718 spin_lock_bh(&ar->data_lock); in ath10k_hw_qca988x_set_coverage_class()
719 ar->fw_coverage.coverage_class = value; in ath10k_hw_qca988x_set_coverage_class()
720 spin_unlock_bh(&ar->data_lock); in ath10k_hw_qca988x_set_coverage_class()
722 ar->fw_coverage.reg_slottime_conf = slottime_reg; in ath10k_hw_qca988x_set_coverage_class()
723 ar->fw_coverage.reg_ack_cts_timeout_conf = timeout_reg; in ath10k_hw_qca988x_set_coverage_class()
726 mutex_unlock(&ar->conf_mutex); in ath10k_hw_qca988x_set_coverage_class()
730 * ath10k_hw_qca6174_enable_pll_clock() - enable the qca6174 hw pll clock
746 struct ath10k_hw_params *hw; in ath10k_hw_qca6174_enable_pll_clock() local
749 hw = &ar->hw_params; in ath10k_hw_qca6174_enable_pll_clock()
751 if (ar->regs->core_clk_div_address == 0 || in ath10k_hw_qca6174_enable_pll_clock()
752 ar->regs->cpu_pll_init_address == 0 || in ath10k_hw_qca6174_enable_pll_clock()
753 ar->regs->cpu_speed_address == 0) in ath10k_hw_qca6174_enable_pll_clock()
754 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
756 clk_div_addr = ar->regs->core_clk_div_address; in ath10k_hw_qca6174_enable_pll_clock()
757 pll_init_addr = ar->regs->cpu_pll_init_address; in ath10k_hw_qca6174_enable_pll_clock()
758 speed_addr = ar->regs->cpu_speed_address; in ath10k_hw_qca6174_enable_pll_clock()
760 /* Read efuse register to find out the right hw clock configuration */ in ath10k_hw_qca6174_enable_pll_clock()
764 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
766 /* sanitize if the hw refclk index is out of the boundary */ in ath10k_hw_qca6174_enable_pll_clock()
768 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
770 hw_clk = &hw->hw_clk[MS(reg_val, EFUSE_XTAL_SEL)]; in ath10k_hw_qca6174_enable_pll_clock()
776 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
779 reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) | in ath10k_hw_qca6174_enable_pll_clock()
780 SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV)); in ath10k_hw_qca6174_enable_pll_clock()
783 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
785 /* Set the correct settle time value to pll_settle register */ in ath10k_hw_qca6174_enable_pll_clock()
789 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
792 reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME); in ath10k_hw_qca6174_enable_pll_clock()
795 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
801 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
807 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
814 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
820 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
822 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | in ath10k_hw_qca6174_enable_pll_clock()
823 SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) | in ath10k_hw_qca6174_enable_pll_clock()
827 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
835 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
840 wait_limit--; in ath10k_hw_qca6174_enable_pll_clock()
846 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
852 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
858 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
866 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
871 wait_limit--; in ath10k_hw_qca6174_enable_pll_clock()
877 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
883 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
889 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
895 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
900 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
907 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
910 ret = ath10k_bmi_write_memory(ar, speed_addr, &hw->target_cpu_freq, in ath10k_hw_qca6174_enable_pll_clock()
911 sizeof(hw->target_cpu_freq)); in ath10k_hw_qca6174_enable_pll_clock()
913 return -EINVAL; in ath10k_hw_qca6174_enable_pll_clock()
948 size = REGION_ACCESS_SIZE_LIMIT - addr; in ath10k_hw_diag_segment_msb_download()
949 remain_size = length - size; in ath10k_hw_diag_segment_msb_download()
1019 return -EINVAL; in ath10k_hw_diag_fast_download()
1025 if (__le32_to_cpu(hdr->magic_num) != BMI_SGMTFILE_MAGIC_NUM) { in ath10k_hw_diag_fast_download()
1028 hdr->magic_num); in ath10k_hw_diag_fast_download()
1029 return -EINVAL; in ath10k_hw_diag_fast_download()
1032 if (hdr->file_flags != 0) { in ath10k_hw_diag_fast_download()
1035 hdr->file_flags); in ath10k_hw_diag_fast_download()
1036 return -EINVAL; in ath10k_hw_diag_fast_download()
1039 metadata = (struct bmi_segmented_metadata *)hdr->data; in ath10k_hw_diag_fast_download()
1040 left = length - sizeof(*hdr); in ath10k_hw_diag_fast_download()
1046 ret = -EINVAL; in ath10k_hw_diag_fast_download()
1049 base_addr = __le32_to_cpu(metadata->addr); in ath10k_hw_diag_fast_download()
1050 base_len = __le32_to_cpu(metadata->length); in ath10k_hw_diag_fast_download()
1051 buf = metadata->data; in ath10k_hw_diag_fast_download()
1052 left -= sizeof(*metadata); in ath10k_hw_diag_fast_download()
1071 ret = -EINVAL; in ath10k_hw_diag_fast_download()
1079 ret = -EINVAL; in ath10k_hw_diag_fast_download()
1099 left -= base_len; in ath10k_hw_diag_fast_download()
1110 return (resp->data_tx_completion.flags2 & HTT_TX_CMPL_FLAG_DATA_RSSI); in ath10k_htt_tx_rssi_enable()
1115 return (resp->data_tx_completion.flags2 & in ath10k_htt_tx_rssi_enable_wcn3990()
1124 if (resp->data_tx_completion.flags2 & HTT_TX_DATA_APPEND_RETRIES) in ath10k_get_htt_tx_data_rssi_pad()
1128 if (resp->data_tx_completion.flags2 & HTT_TX_DATA_APPEND_TIMESTAMP) in ath10k_get_htt_tx_data_rssi_pad()