Lines Matching +full:0 +full:x0007ffff
18 .rtc_soc_base_address = 0x00004000,
19 .rtc_wmac_base_address = 0x00005000,
20 .soc_core_base_address = 0x00009000,
21 .wlan_mac_base_address = 0x00020000,
22 .ce_wrapper_base_address = 0x00057000,
23 .ce0_base_address = 0x00057400,
24 .ce1_base_address = 0x00057800,
25 .ce2_base_address = 0x00057c00,
26 .ce3_base_address = 0x00058000,
27 .ce4_base_address = 0x00058400,
28 .ce5_base_address = 0x00058800,
29 .ce6_base_address = 0x00058c00,
30 .ce7_base_address = 0x00059000,
31 .soc_reset_control_si0_rst_mask = 0x00000001,
32 .soc_reset_control_ce_rst_mask = 0x00040000,
33 .soc_chip_id_address = 0x000000ec,
34 .scratch_3_address = 0x00000030,
35 .fw_indicator_address = 0x00009030,
36 .pcie_local_base_address = 0x00080000,
37 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
38 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
39 .pcie_intr_fw_mask = 0x00000400,
40 .pcie_intr_ce_mask_all = 0x0007f800,
41 .pcie_intr_clr_address = 0x00000014,
45 .rtc_soc_base_address = 0x00000800,
46 .rtc_wmac_base_address = 0x00001000,
47 .soc_core_base_address = 0x0003a000,
48 .wlan_mac_base_address = 0x00010000,
49 .ce_wrapper_base_address = 0x00034000,
50 .ce0_base_address = 0x00034400,
51 .ce1_base_address = 0x00034800,
52 .ce2_base_address = 0x00034c00,
53 .ce3_base_address = 0x00035000,
54 .ce4_base_address = 0x00035400,
55 .ce5_base_address = 0x00035800,
56 .ce6_base_address = 0x00035c00,
57 .ce7_base_address = 0x00036000,
58 .soc_reset_control_si0_rst_mask = 0x00000000,
59 .soc_reset_control_ce_rst_mask = 0x00000001,
60 .soc_chip_id_address = 0x000000f0,
61 .scratch_3_address = 0x00000028,
62 .fw_indicator_address = 0x0003a028,
63 .pcie_local_base_address = 0x00080000,
64 .ce_wrap_intr_sum_host_msi_lsb = 0x00000008,
65 .ce_wrap_intr_sum_host_msi_mask = 0x0000ff00,
66 .pcie_intr_fw_mask = 0x00000400,
67 .pcie_intr_ce_mask_all = 0x0007f800,
68 .pcie_intr_clr_address = 0x00000014,
69 .cpu_pll_init_address = 0x00404020,
70 .cpu_speed_address = 0x00404024,
71 .core_clk_div_address = 0x00404028,
75 .rtc_soc_base_address = 0x00080000,
76 .rtc_wmac_base_address = 0x00000000,
77 .soc_core_base_address = 0x00082000,
78 .wlan_mac_base_address = 0x00030000,
79 .ce_wrapper_base_address = 0x0004d000,
80 .ce0_base_address = 0x0004a000,
81 .ce1_base_address = 0x0004a400,
82 .ce2_base_address = 0x0004a800,
83 .ce3_base_address = 0x0004ac00,
84 .ce4_base_address = 0x0004b000,
85 .ce5_base_address = 0x0004b400,
86 .ce6_base_address = 0x0004b800,
87 .ce7_base_address = 0x0004bc00,
93 * CE8 0x0004c000
94 * CE9 0x0004c400
95 * CE10 0x0004c800
96 * CE11 0x0004cc00
98 .soc_reset_control_si0_rst_mask = 0x00000001,
99 .soc_reset_control_ce_rst_mask = 0x00000100,
100 .soc_chip_id_address = 0x000000ec,
101 .scratch_3_address = 0x00040050,
102 .fw_indicator_address = 0x00040050,
103 .pcie_local_base_address = 0x00000000,
104 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
105 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
106 .pcie_intr_fw_mask = 0x00100000,
107 .pcie_intr_ce_mask_all = 0x000fff00,
108 .pcie_intr_clr_address = 0x00000010,
112 .rtc_soc_base_address = 0x00080000,
113 .soc_core_base_address = 0x00082000,
114 .wlan_mac_base_address = 0x00030000,
115 .ce_wrapper_base_address = 0x0004d000,
116 .ce0_base_address = 0x0004a000,
117 .ce1_base_address = 0x0004a400,
118 .ce2_base_address = 0x0004a800,
119 .ce3_base_address = 0x0004ac00,
120 .ce4_base_address = 0x0004b000,
121 .ce5_base_address = 0x0004b400,
122 .ce6_base_address = 0x0004b800,
123 .ce7_base_address = 0x0004bc00,
128 * CE8 0x0004c000
129 * CE9 0x0004c400
130 * CE10 0x0004c800
131 * CE11 0x0004cc00
133 .soc_reset_control_si0_rst_mask = 0x00000001,
134 .soc_reset_control_ce_rst_mask = 0x00000100,
135 .soc_chip_id_address = 0x000000ec,
136 .fw_indicator_address = 0x0004f00c,
137 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
138 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
139 .pcie_intr_fw_mask = 0x00100000,
140 .pcie_intr_ce_mask_all = 0x000fff00,
141 .pcie_intr_clr_address = 0x00000010,
149 .ce_desc_meta_data_mask = 0xFFFC,
158 .ce_desc_meta_data_mask = 0xFFFC,
161 .rfkill_cfg = 0,
170 .ce_desc_meta_data_mask = 0xFFF0,
179 .ce_desc_meta_data_mask = 0xFFF0,
186 .ce_desc_meta_data_mask = 0xFFF0,
191 .rtc_soc_base_address = 0x00000000,
192 .rtc_wmac_base_address = 0x00000000,
193 .soc_core_base_address = 0x00000000,
194 .ce_wrapper_base_address = 0x0024C000,
195 .ce0_base_address = 0x00240000,
196 .ce1_base_address = 0x00241000,
197 .ce2_base_address = 0x00242000,
198 .ce3_base_address = 0x00243000,
199 .ce4_base_address = 0x00244000,
200 .ce5_base_address = 0x00245000,
201 .ce6_base_address = 0x00246000,
202 .ce7_base_address = 0x00247000,
203 .ce8_base_address = 0x00248000,
204 .ce9_base_address = 0x00249000,
205 .ce10_base_address = 0x0024A000,
206 .ce11_base_address = 0x0024B000,
207 .soc_chip_id_address = 0x000000f0,
208 .soc_reset_control_si0_rst_mask = 0x00000001,
209 .soc_reset_control_ce_rst_mask = 0x00000100,
210 .ce_wrap_intr_sum_host_msi_lsb = 0x0000000c,
211 .ce_wrap_intr_sum_host_msi_mask = 0x00fff000,
212 .pcie_intr_fw_mask = 0x00100000,
216 .msb = 0x00000010,
217 .lsb = 0x00000010,
222 .msb = 0x00000012,
223 .lsb = 0x00000012,
228 .msb = 0x00000000,
229 .lsb = 0x00000000,
230 .mask = GENMASK(15, 0),
234 .addr = 0x00000018,
241 .mask = GENMASK(0, 0),
249 .dstr_lmask = 0x00000010,
250 .dstr_hmask = 0x00000008,
251 .srcr_lmask = 0x00000004,
252 .srcr_hmask = 0x00000002,
253 .cc_mask = 0x00000001,
254 .wm_mask = 0x0000001E,
255 .addr = 0x00000030,
259 .axi_err = 0x00000100,
260 .dstr_add_err = 0x00000200,
261 .srcr_len_err = 0x00000100,
262 .dstr_mlen_vio = 0x00000080,
263 .dstr_overflow = 0x00000040,
264 .srcr_overflow = 0x00000020,
265 .err_mask = 0x000003E0,
266 .addr = 0x00000038,
270 .msb = 0x00000000,
271 .lsb = 0x00000010,
276 .msb = 0x0000000f,
277 .lsb = 0x00000000,
278 .mask = GENMASK(15, 0),
282 .addr = 0x0000004c,
283 .low_rst = 0x00000000,
284 .high_rst = 0x00000000,
290 .lsb = 0x00000010,
295 .msb = 0x0000000f,
296 .lsb = 0x00000000,
297 .mask = GENMASK(15, 0),
301 .addr = 0x00000050,
302 .low_rst = 0x00000000,
303 .high_rst = 0x00000000,
310 .mask = 0x00080000,
311 .enable = 0x00000000,
315 .sr_base_addr_lo = 0x00000000,
316 .sr_base_addr_hi = 0x00000004,
317 .sr_size_addr = 0x00000008,
318 .dr_base_addr_lo = 0x0000000c,
319 .dr_base_addr_hi = 0x00000010,
320 .dr_size_addr = 0x00000014,
321 .misc_ie_addr = 0x00000034,
322 .sr_wr_index_addr = 0x0000003c,
323 .dst_wr_index_addr = 0x00000040,
324 .current_srri_addr = 0x00000044,
325 .current_drri_addr = 0x00000048,
326 .ce_rri_low = 0x0024C004,
327 .ce_rri_high = 0x0024C008,
328 .host_ie_addr = 0x0000002c,
343 .ce_desc_meta_data_mask = 0xFFF0,
348 .msb = 0x00000010,
349 .lsb = 0x00000010,
354 .msb = 0x00000011,
355 .lsb = 0x00000011,
360 .msb = 0x0000000f,
361 .lsb = 0x00000000,
362 .mask = GENMASK(15, 0),
366 .addr = 0x00000010,
367 .hw_mask = 0x0007ffff,
368 .sw_mask = 0x0007ffff,
369 .hw_wr_mask = 0x00000000,
370 .sw_wr_mask = 0x0007ffff,
371 .reset_mask = 0xffffffff,
372 .reset = 0x00000080,
379 .msb = 0x00000003,
380 .lsb = 0x00000003,
385 .msb = 0x00000000,
386 .mask = GENMASK(0, 0),
387 .status_reset = 0x00000000,
392 .msb = 0x00000000,
393 .lsb = 0x00000000,
394 .mask = GENMASK(0, 0),
398 .copy_complete_reset = 0x00000000,
403 .dstr_lmask = 0x00000010,
404 .dstr_hmask = 0x00000008,
405 .srcr_lmask = 0x00000004,
406 .srcr_hmask = 0x00000002,
407 .cc_mask = 0x00000001,
408 .wm_mask = 0x0000001E,
409 .addr = 0x00000030,
413 .axi_err = 0x00000400,
414 .dstr_add_err = 0x00000200,
415 .srcr_len_err = 0x00000100,
416 .dstr_mlen_vio = 0x00000080,
417 .dstr_overflow = 0x00000040,
418 .srcr_overflow = 0x00000020,
419 .err_mask = 0x000007E0,
420 .addr = 0x00000038,
424 .msb = 0x0000001f,
425 .lsb = 0x00000010,
430 .msb = 0x0000000f,
431 .lsb = 0x00000000,
432 .mask = GENMASK(15, 0),
436 .addr = 0x0000004c,
437 .low_rst = 0x00000000,
438 .high_rst = 0x00000000,
444 .lsb = 0x00000010,
449 .msb = 0x0000000f,
450 .lsb = 0x00000000,
451 .mask = GENMASK(15, 0),
455 .addr = 0x00000050,
456 .low_rst = 0x00000000,
457 .high_rst = 0x00000000,
463 .sr_base_addr_lo = 0x00000000,
464 .sr_size_addr = 0x00000004,
465 .dr_base_addr_lo = 0x00000008,
466 .dr_size_addr = 0x0000000c,
467 .ce_cmd_addr = 0x00000018,
468 .misc_ie_addr = 0x00000034,
469 .sr_wr_index_addr = 0x0000003c,
470 .dst_wr_index_addr = 0x00000040,
471 .current_srri_addr = 0x00000044,
472 .current_drri_addr = 0x00000048,
473 .host_ie_addr = 0x0000002c,
486 .div = 0xe,
487 .rnfrac = 0x2aaa8,
489 .refdiv = 0,
494 .div = 0x24,
495 .rnfrac = 0x2aaa8,
497 .refdiv = 0,
502 .div = 0x1d,
503 .rnfrac = 0x15551,
505 .refdiv = 0,
510 .div = 0x1b,
511 .rnfrac = 0x4ec4,
513 .refdiv = 0,
518 .div = 0x12,
519 .rnfrac = 0x34b49,
521 .refdiv = 0,
526 .div = 0x12,
527 .rnfrac = 0x15551,
529 .refdiv = 0,
534 .div = 0x12,
535 .rnfrac = 0x26665,
537 .refdiv = 0,
542 .div = 0x1b,
543 .rnfrac = 0x4ec4,
545 .refdiv = 0,
553 u32 cc_fix = 0; in ath10k_hw_fill_survey_time()
554 u32 rcc_fix = 0; in ath10k_hw_fill_survey_time()
566 cc_fix = 0x7fffffff; in ath10k_hw_fill_survey_time()
572 cc_fix = 0x7fffffff; in ath10k_hw_fill_survey_time()
575 rcc_fix = 0x7fffffff; in ath10k_hw_fill_survey_time()
628 if (value < 0) in ath10k_hw_qca988x_set_coverage_class()
701 * coverage class is larger than 0. This is important as we need to in ath10k_hw_qca988x_set_coverage_class()
708 if (value > 0) { in ath10k_hw_qca988x_set_coverage_class()
711 fw_dbglog_mask = ~0; in ath10k_hw_qca988x_set_coverage_class()
739 * Return: 0 if successfully enable the pll, otherwise EINVAL
751 if (ar->regs->core_clk_div_address == 0 || in ath10k_hw_qca6174_enable_pll_clock()
752 ar->regs->cpu_pll_init_address == 0 || in ath10k_hw_qca6174_enable_pll_clock()
753 ar->regs->cpu_speed_address == 0) in ath10k_hw_qca6174_enable_pll_clock()
843 } while (wait_limit > 0); in ath10k_hw_qca6174_enable_pll_clock()
855 reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS); in ath10k_hw_qca6174_enable_pll_clock()
874 } while (wait_limit > 0); in ath10k_hw_qca6174_enable_pll_clock()
915 return 0; in ath10k_hw_qca6174_enable_pll_clock()
929 * 2. Target address( 0 ~ 00100000 & 0x00400000~0x00500000)
954 "failed to download the first %d bytes segment to address:0x%x: %d\n", in ath10k_hw_diag_segment_msb_download()
968 "failed to download the second %d bytes segment to address:0x%x: %d\n", in ath10k_hw_diag_segment_msb_download()
978 "failed to download the only %d bytes segment to address:0x%x: %d\n", in ath10k_hw_diag_segment_msb_download()
1011 u32 base_addr = 0; in ath10k_hw_diag_fast_download()
1012 u32 base_len = 0; in ath10k_hw_diag_fast_download()
1013 u32 left = 0; in ath10k_hw_diag_fast_download()
1016 int ret = 0; in ath10k_hw_diag_fast_download()
1027 "Not a supported firmware, magic_num:0x%x\n", in ath10k_hw_diag_fast_download()
1032 if (hdr->file_flags != 0) { in ath10k_hw_diag_fast_download()
1034 "Not a supported firmware, file_flags:0x%x\n", in ath10k_hw_diag_fast_download()
1042 while (left > 0) { in ath10k_hw_diag_fast_download()
1058 base_len = 0; in ath10k_hw_diag_fast_download()
1062 base_len = 0; in ath10k_hw_diag_fast_download()
1064 ret = 0; in ath10k_hw_diag_fast_download()
1102 if (ret == 0) in ath10k_hw_diag_fast_download()
1122 int pad_bytes = 0; in ath10k_get_htt_tx_data_rssi_pad()
1126 sizeof(extd.msdus_rssi[0]); in ath10k_get_htt_tx_data_rssi_pad()
1129 pad_bytes += sizeof(extd.t_stamp) / sizeof(extd.msdus_rssi[0]); in ath10k_get_htt_tx_data_rssi_pad()