net/wan/hd64572.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * hd64572.h	Description of the Hitachi HD64572 (SCA-II), valid for
8  * Copyright:   (c) 2000-2001 Cyclades Corp.
15  * PC300 initial CVS version (3.4.0-pre1)
33 #define WCRM	0x25	/* Wait Control Register M */
47 #define	DRX_REG(reg, chan)	(reg + 0x40*chan)		/* DMA Rx */
49 #define	TRX_REG(reg, chan)	(reg + 0x20*chan)		/* Timer Rx */
52 #define IR0_DRX(val, chan)	((val)<<(8*(chan)))		/* Int DMA Rx */
65 #define RXS	0x13c	/* RX clock source */
67 #define EXS	0x13e	/* External clock input selection */
69 #define TMCR	0x145	/* Time constant (Rx) */
85 #define TRBL	0x100	/* TX/RX buffer reg L */
86 #define TRBK	0x101	/* TX/RX buffer reg K */
87 #define TRBJ	0x102	/* TX/RX buffer reg J */
88 #define TRBH	0x103	/* TX/RX buffer reg H */
91 #define RRC	0x14a	/* RX Ready control reg */
98 #define TFN	0x143	/* Inter-transmit-frame Time Fill Ctl Reg */
100 #define RBN	0x111	/* Rx Buffer Number Reg */
104 #define RNR	0x154	/* Rx DMA Request Ctl Reg */
105 #define RCR	0x156	/* Rx DMA Critical Request Reg */
125 #define BOLR		0x0c		/* Back-off Length Reg */
126 #define DSR_RX(chan)	(0x48 + 2*chan)	/* DMA Status Reg (Rx) */
128 #define DIR_RX(chan)	(0x4c + 2*chan)	/* DMA Interrupt Enable Reg (Rx) */
130 #define FCT_RX(chan)	(0x50 + 2*chan)	/* Frame End Interrupt Counter (Rx) */
132 #define DMR_RX(chan)	(0x54 + 2*chan)	/* DMA Mode Reg (Rx) */
134 #define DCR_RX(chan)	(0x58 + 2*chan)	/* DMA Command Reg (Rx) */
143 #define DARL	0x80	/* Dest Addr Register L (single-block, RX only) */
144 #define DARH	0x81	/* Dest Addr Register H (single-block, RX only) */
145 #define DARB	0x82	/* Dest Addr Register B (single-block, RX only) */
146 #define DARBH	0x83	/* Dest Addr Register BH (single-block, RX only) */
147 #define SARL	0x80	/* Source Addr Register L (single-block, TX only) */
148 #define SARH	0x81	/* Source Addr Register H (single-block, TX only) */
149 #define SARB	0x82	/* Source Addr Register B (single-block, TX only) */
150 #define DARBH	0x83	/* Source Addr Register BH (single-block, TX only) */
151 #define BARL	0x80	/* Buffer Addr Register L (chained-block) */
152 #define BARH	0x81	/* Buffer Addr Register H (chained-block) */
153 #define BARB	0x82	/* Buffer Addr Register B (chained-block) */
154 #define BARBH	0x83	/* Buffer Addr Register BH (chained-block) */
163 #define BFLL	0x90	/* RX Buffer Length L (only RX) */
164 #define BFLH	0x91	/* RX Buffer Length H (only RX) */
183 	u8 unused;		/* pads to 4-byte boundary */
193 	6	-		Short Frame
194 	5	-		Abort
195 	4	-		Residual bit
197 	2	-		CRC
199 	0	EOT		-
231 #define TECNTM	0x161	/* Tx EOM Counter M */
237 #define RECNTL	0x168	/* Rx EOM Counter L */
238 #define RECNTM	0x169	/* Rx EOM Counter M */
239 #define RECNTH	0x16a	/* Rx EOM Counter H */
240 #define RECCR	0x16b	/* Rx EOM Counter Ctl Reg */
284 #define MD0_HDLC        0x80	/* Bit-sync HDLC mode */
360 #define CLK_LINE    	0x00	/* clock line input */
362 #define CLK_TX_RXCLK	0x60	/* TX clock from RX clock */