net/wan/hd64572.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * hd64572.h	Description of the Hitachi HD64572 (SCA-II), valid for
8  * Copyright:   (c) 2000-2001 Cyclades Corp.
15  * PC300 initial CVS version (3.4.0-pre1)
98 #define TFN	0x143	/* Inter-transmit-frame Time Fill Ctl Reg */
125 #define BOLR		0x0c		/* Back-off Length Reg */
130 #define FCT_RX(chan)	(0x50 + 2*chan)	/* Frame End Interrupt Counter (Rx) */
131 #define FCT_TX(chan)	(0x51 + 2*chan)	/* Frame End Interrupt Counter (Tx) */
143 #define DARL	0x80	/* Dest Addr Register L (single-block, RX only) */
144 #define DARH	0x81	/* Dest Addr Register H (single-block, RX only) */
145 #define DARB	0x82	/* Dest Addr Register B (single-block, RX only) */
146 #define DARBH	0x83	/* Dest Addr Register BH (single-block, RX only) */
147 #define SARL	0x80	/* Source Addr Register L (single-block, TX only) */
148 #define SARH	0x81	/* Source Addr Register H (single-block, TX only) */
149 #define SARB	0x82	/* Source Addr Register B (single-block, TX only) */
150 #define DARBH	0x83	/* Source Addr Register BH (single-block, TX only) */
151 #define BARL	0x80	/* Buffer Addr Register L (chained-block) */
152 #define BARH	0x81	/* Buffer Addr Register H (chained-block) */
153 #define BARB	0x82	/* Buffer Addr Register B (chained-block) */
154 #define BARBH	0x83	/* Buffer Addr Register BH (chained-block) */
183 	u8 unused;		/* pads to 4-byte boundary */
193 	6	-		Short Frame
194 	5	-		Abort
195 	4	-		Residual bit
197 	2	-		CRC
199 	0	EOT		-
201 #define DST_EOT		0x01	/* End of transmit command */
209 #define DST_EOM		0x80	/* End of Message  */
213 #define ST_TX_EOM     0x80	/* End of frame */
216 #define ST_TX_EOT     0x01	/* End of transmission */
218 #define ST_RX_EOM     0x80	/* End of frame */
284 #define MD0_HDLC        0x80	/* Bit-sync HDLC mode */