135 		iowrite32be(gumr, &priv->uf_regs->gumr);  in uhdlc_init()
148 	iowrite32be(0, &priv->uf_regs->upsmr);  in uhdlc_init()
162 		iowrite32be(upsmr, &priv->uf_regs->upsmr);  in uhdlc_init()
169 		iowrite32be(gumr, &priv->uf_regs->gumr);  in uhdlc_init()
268 	iowrite32be(priv->dma_rx_bd, &priv->ucc_pram->rbase);  in uhdlc_init()
269 	iowrite32be(priv->dma_tx_bd, &priv->ucc_pram->tbase);  in uhdlc_init()
272 	iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->rstate);  in uhdlc_init()
273 	iowrite32be(BMR_GBL | BMR_BIG_ENDIAN, &priv->ucc_pram->tstate);  in uhdlc_init()
276 	iowrite32be(CRC_16BIT_MASK, &priv->ucc_pram->c_mask);  in uhdlc_init()
277 	iowrite32be(CRC_16BIT_PRES, &priv->ucc_pram->c_pres);  in uhdlc_init()
660 	iowrite32be(ucce, uccf->p_ucce);  in ucc_hdlc_irq_handler()
668 			iowrite32be(uccm, uccf->p_uccm);  in ucc_hdlc_irq_handler()
881 	iowrite32be(priv->cmxsi1cr_h, &qe_mux_reg->cmxsi1cr_h);  in resume_clk_config()
882 	iowrite32be(priv->cmxsi1cr_l, &qe_mux_reg->cmxsi1cr_l);  in resume_clk_config()
884 	iowrite32be(priv->cmxsi1syr, &qe_mux_reg->cmxsi1syr);  in resume_clk_config()
951 	iowrite32be(priv->gumr, &uf_regs->gumr);  in uhdlc_resume()
961 	iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset, &uf_regs->utfb);  in uhdlc_resume()
962 	iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset, &uf_regs->urfb);  in uhdlc_resume()
967 	iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);  in uhdlc_resume()
968 	iowrite32be(0xffffffff, &uf_regs->ucce);  in uhdlc_resume()
982 	iowrite32be(0, &uf_regs->upsmr);  in uhdlc_resume()