Lines Matching +full:0 +full:xcfff
46 #define PLA_IDR 0xc000
47 #define PLA_RCR 0xc010
48 #define PLA_RCR1 0xc012
49 #define PLA_RMS 0xc016
50 #define PLA_RXFIFO_CTRL0 0xc0a0
51 #define PLA_RXFIFO_FULL 0xc0a2
52 #define PLA_RXFIFO_CTRL1 0xc0a4
53 #define PLA_RX_FIFO_FULL 0xc0a6
54 #define PLA_RXFIFO_CTRL2 0xc0a8
55 #define PLA_RX_FIFO_EMPTY 0xc0aa
56 #define PLA_DMY_REG0 0xc0b0
57 #define PLA_FMC 0xc0b4
58 #define PLA_CFG_WOL 0xc0b6
59 #define PLA_TEREDO_CFG 0xc0bc
60 #define PLA_TEREDO_WAKE_BASE 0xc0c4
61 #define PLA_MAR 0xcd00
62 #define PLA_BACKUP 0xd000
63 #define PLA_BDC_CR 0xd1a0
64 #define PLA_TEREDO_TIMER 0xd2cc
65 #define PLA_REALWOW_TIMER 0xd2e8
66 #define PLA_UPHY_TIMER 0xd388
67 #define PLA_SUSPEND_FLAG 0xd38a
68 #define PLA_INDICATE_FALG 0xd38c
69 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
70 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
71 #define PLA_EXTRA_STATUS 0xd398
72 #define PLA_GPHY_CTRL 0xd3ae
73 #define PLA_POL_GPIO_CTRL 0xdc6a
74 #define PLA_EFUSE_DATA 0xdd00
75 #define PLA_EFUSE_CMD 0xdd02
76 #define PLA_LEDSEL 0xdd90
77 #define PLA_LED_FEATURE 0xdd92
78 #define PLA_PHYAR 0xde00
79 #define PLA_BOOT_CTRL 0xe004
80 #define PLA_LWAKE_CTRL_REG 0xe007
81 #define PLA_GPHY_INTR_IMR 0xe022
82 #define PLA_EEE_CR 0xe040
83 #define PLA_EEE_TXTWSYS 0xe04c
84 #define PLA_EEE_TXTWSYS_2P5G 0xe058
85 #define PLA_EEEP_CR 0xe080
86 #define PLA_MAC_PWR_CTRL 0xe0c0
87 #define PLA_MAC_PWR_CTRL2 0xe0ca
88 #define PLA_MAC_PWR_CTRL3 0xe0cc
89 #define PLA_MAC_PWR_CTRL4 0xe0ce
90 #define PLA_WDT6_CTRL 0xe428
91 #define PLA_TCR0 0xe610
92 #define PLA_TCR1 0xe612
93 #define PLA_MTPS 0xe615
94 #define PLA_TXFIFO_CTRL 0xe618
95 #define PLA_TXFIFO_FULL 0xe61a
96 #define PLA_RSTTALLY 0xe800
97 #define PLA_CR 0xe813
98 #define PLA_CRWECR 0xe81c
99 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
100 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
101 #define PLA_CONFIG5 0xe822
102 #define PLA_PHY_PWR 0xe84c
103 #define PLA_OOB_CTRL 0xe84f
104 #define PLA_CPCR 0xe854
105 #define PLA_MISC_0 0xe858
106 #define PLA_MISC_1 0xe85a
107 #define PLA_OCP_GPHY_BASE 0xe86c
108 #define PLA_TALLYCNT 0xe890
109 #define PLA_SFF_STS_7 0xe8de
110 #define PLA_PHYSTATUS 0xe908
111 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
112 #define PLA_USB_CFG 0xe952
113 #define PLA_BP_BA 0xfc26
114 #define PLA_BP_0 0xfc28
115 #define PLA_BP_1 0xfc2a
116 #define PLA_BP_2 0xfc2c
117 #define PLA_BP_3 0xfc2e
118 #define PLA_BP_4 0xfc30
119 #define PLA_BP_5 0xfc32
120 #define PLA_BP_6 0xfc34
121 #define PLA_BP_7 0xfc36
122 #define PLA_BP_EN 0xfc38
124 #define USB_USB2PHY 0xb41e
125 #define USB_SSPHYLINK1 0xb426
126 #define USB_SSPHYLINK2 0xb428
127 #define USB_L1_CTRL 0xb45e
128 #define USB_U2P3_CTRL 0xb460
129 #define USB_CSR_DUMMY1 0xb464
130 #define USB_CSR_DUMMY2 0xb466
131 #define USB_DEV_STAT 0xb808
132 #define USB_CONNECT_TIMER 0xcbf8
133 #define USB_MSC_TIMER 0xcbfc
134 #define USB_BURST_SIZE 0xcfc0
135 #define USB_FW_FIX_EN0 0xcfca
136 #define USB_FW_FIX_EN1 0xcfcc
137 #define USB_LPM_CONFIG 0xcfd8
138 #define USB_ECM_OPTION 0xcfee
139 #define USB_CSTMR 0xcfef /* RTL8153A */
140 #define USB_MISC_2 0xcfff
141 #define USB_ECM_OP 0xd26b
142 #define USB_GPHY_CTRL 0xd284
143 #define USB_SPEED_OPTION 0xd32a
144 #define USB_FW_CTRL 0xd334 /* RTL8153B */
145 #define USB_FC_TIMER 0xd340
146 #define USB_USB_CTRL 0xd406
147 #define USB_PHY_CTRL 0xd408
148 #define USB_TX_AGG 0xd40a
149 #define USB_RX_BUF_TH 0xd40c
150 #define USB_USB_TIMER 0xd428
151 #define USB_RX_EARLY_TIMEOUT 0xd42c
152 #define USB_RX_EARLY_SIZE 0xd42e
153 #define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */
154 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
155 #define USB_TX_DMA 0xd434
156 #define USB_UPT_RXDMA_OWN 0xd437
157 #define USB_UPHY3_MDCMDIO 0xd480
158 #define USB_TOLERANCE 0xd490
159 #define USB_LPM_CTRL 0xd41a
160 #define USB_BMU_RESET 0xd4b0
161 #define USB_BMU_CONFIG 0xd4b4
162 #define USB_U1U2_TIMER 0xd4da
163 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
164 #define USB_RX_AGGR_NUM 0xd4ee
165 #define USB_UPS_CTRL 0xd800
166 #define USB_POWER_CUT 0xd80a
167 #define USB_MISC_0 0xd81a
168 #define USB_MISC_1 0xd81f
169 #define USB_AFE_CTRL2 0xd824
170 #define USB_UPHY_XTAL 0xd826
171 #define USB_UPS_CFG 0xd842
172 #define USB_UPS_FLAGS 0xd848
173 #define USB_WDT1_CTRL 0xe404
174 #define USB_WDT11_CTRL 0xe43c
185 #define USB_BP_8 0xfc38 /* RTL8153B */
186 #define USB_BP_9 0xfc3a
187 #define USB_BP_10 0xfc3c
188 #define USB_BP_11 0xfc3e
189 #define USB_BP_12 0xfc40
190 #define USB_BP_13 0xfc42
191 #define USB_BP_14 0xfc44
192 #define USB_BP_15 0xfc46
193 #define USB_BP2_EN 0xfc48
196 #define OCP_ALDPS_CONFIG 0x2010
197 #define OCP_EEE_CONFIG1 0x2080
198 #define OCP_EEE_CONFIG2 0x2092
199 #define OCP_EEE_CONFIG3 0x2094
200 #define OCP_BASE_MII 0xa400
201 #define OCP_EEE_AR 0xa41a
202 #define OCP_EEE_DATA 0xa41c
203 #define OCP_PHY_STATUS 0xa420
204 #define OCP_INTR_EN 0xa424
205 #define OCP_NCTL_CFG 0xa42c
206 #define OCP_POWER_CFG 0xa430
207 #define OCP_EEE_CFG 0xa432
208 #define OCP_SRAM_ADDR 0xa436
209 #define OCP_SRAM_DATA 0xa438
210 #define OCP_DOWN_SPEED 0xa442
211 #define OCP_EEE_ABLE 0xa5c4
212 #define OCP_EEE_ADV 0xa5d0
213 #define OCP_EEE_LPABLE 0xa5d2
214 #define OCP_10GBT_CTRL 0xa5d4
215 #define OCP_10GBT_STAT 0xa5d6
216 #define OCP_EEE_ADV2 0xa6d4
217 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
218 #define OCP_PHY_PATCH_STAT 0xb800
219 #define OCP_PHY_PATCH_CMD 0xb820
220 #define OCP_PHY_LOCK 0xb82e
221 #define OCP_ADC_IOFFSET 0xbcfc
222 #define OCP_ADC_CFG 0xbc06
223 #define OCP_SYSCLK_CFG 0xc416
226 #define SRAM_GREEN_CFG 0x8011
227 #define SRAM_LPF_CFG 0x8012
228 #define SRAM_GPHY_FW_VER 0x801e
229 #define SRAM_10M_AMP1 0x8080
230 #define SRAM_10M_AMP2 0x8082
231 #define SRAM_IMPEDANCE 0x8084
232 #define SRAM_PHY_LOCK 0xb82e
235 #define RCR_AAP 0x00000001
236 #define RCR_APM 0x00000002
237 #define RCR_AM 0x00000004
238 #define RCR_AB 0x00000008
247 #define RXFIFO_THR1_NORMAL 0x00080002
248 #define RXFIFO_THR1_OOB 0x01800003
251 #define RXFIFO_FULL_MASK 0xfff
254 #define RXFIFO_THR2_FULL 0x00000060
255 #define RXFIFO_THR2_HIGH 0x00000038
256 #define RXFIFO_THR2_OOB 0x0000004a
257 #define RXFIFO_THR2_NORMAL 0x00a0
260 #define RXFIFO_THR3_FULL 0x00000078
261 #define RXFIFO_THR3_HIGH 0x00000048
262 #define RXFIFO_THR3_OOB 0x0000005a
263 #define RXFIFO_THR3_NORMAL 0x0110
266 #define TXFIFO_THR_NORMAL 0x00400008
267 #define TXFIFO_THR_NORMAL2 0x01000008
270 #define ECM_ALDPS 0x0002
273 #define FMC_FCR_MCU_EN 0x0001
276 #define EEEP_CR_EEEP_TX 0x0002
279 #define WDT6_SET_MODE 0x0010
282 #define TCR0_TX_EMPTY 0x0800
283 #define TCR0_AUTO_FIFO 0x0080
286 #define VERSION_MASK 0x7cf0
296 #define TALLY_RESET 0x0001
299 #define CR_RST 0x10
300 #define CR_RE 0x08
301 #define CR_TE 0x04
304 #define CRWECR_NORAML 0x00
305 #define CRWECR_CONFIG 0xc0
308 #define NOW_IS_OOB 0x80
309 #define TXFIFO_EMPTY 0x20
310 #define RXFIFO_EMPTY 0x10
311 #define LINK_LIST_READY 0x02
312 #define DIS_MCU_CLROOB 0x01
316 #define RXDY_GATED_EN 0x0008
319 #define RE_INIT_LL 0x8000
320 #define MCU_BORW_EN 0x4000
323 #define FLOW_CTRL_EN BIT(0)
324 #define CPCR_RX_VLAN 0x0040
327 #define MAGIC_EN 0x0001
330 #define TEREDO_SEL 0x8000
331 #define TEREDO_WAKE_MASK 0x7f00
332 #define TEREDO_RS_EVENT_MASK 0x00fe
333 #define OOB_TEREDO_EN 0x0001
336 #define ALDPS_PROXY_MODE 0x0001
343 #define LINK_ON_WAKE_EN 0x0010
344 #define LINK_OFF_WAKE_EN 0x0008
347 #define LANWAKE_CLR_EN BIT(0)
354 #define BWF_EN 0x0040
355 #define MWF_EN 0x0020
356 #define UWF_EN 0x0010
357 #define LAN_WAKE_EN 0x0002
360 #define LED_MODE_MASK 0x0700
363 #define TX_10M_IDLE_EN 0x0080
364 #define PFM_PWM_SWITCH 0x0040
368 #define D3_CLK_GATED_EN 0x00004000
369 #define MCU_CLK_RATIO 0x07010f07
370 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
371 #define ALDPS_SPDWN_RATIO 0x0f87
374 #define EEE_SPDWN_RATIO 0x8007
376 #define EEE_SPDWN_RATIO_MASK 0xff
380 #define PKT_AVAIL_SPDWN_EN 0x0100
381 #define SUSPEND_SPDWN_EN 0x0004
382 #define U1U2_SPDWN_EN 0x0002
383 #define L1_SPDWN_EN 0x0001
386 #define PWRSAVE_SPDWN_EN 0x1000
387 #define RXDV_SPDWN_EN 0x0800
388 #define TX10MIDLE_EN 0x0100
390 #define TP100_SPDWN_EN 0x0020
391 #define TP500_SPDWN_EN 0x0010
392 #define TP1000_SPDWN_EN 0x0008
393 #define EEE_SPDWN_EN 0x0001
396 #define GPHY_STS_MSK 0x0001
397 #define SPEED_DOWN_MSK 0x0002
398 #define SPDWN_RXDV_MSK 0x0004
399 #define SPDWN_LINKCHG_MSK 0x0008
402 #define PHYAR_FLAG 0x80000000
405 #define EEE_RX_EN 0x0001
406 #define EEE_TX_EN 0x0002
409 #define AUTOLOAD_DONE 0x0002
415 #define LINK_CHG_EVENT BIT(0)
418 #define UPCOMING_RUNTIME_D3 BIT(0)
421 #define DEBUG_OE BIT(0)
422 #define DEBUG_LTSSM 0x0082
428 #define POLL_LINK_CHG BIT(0)
438 #define USB2PHY_SUSPEND 0x0001
439 #define USB2PHY_L1 0x0002
445 #define pwd_dn_scale_mask 0x3ffe
449 #define DYNAMIC_BURST 0x0001
452 #define EP4_FULL_FC 0x0001
455 #define STAT_SPEED_MASK 0x0006
456 #define STAT_SPEED_HIGH 0x0000
457 #define STAT_SPEED_FULL 0x0002
466 #define LPM_U1U2_EN BIT(0)
469 #define TX_AGG_MAX_THRESHOLD 0x03
472 #define RX_THR_SUPPER 0x0c350180
473 #define RX_THR_HIGH 0x7a120180
474 #define RX_THR_SLOW 0xffff0180
475 #define RX_THR_B 0x00010001
478 #define TEST_MODE_DISABLE 0x00000001
479 #define TX_SIZE_ADJUST1 0x00000100
482 #define BMU_RESET_EP_IN 0x01
483 #define BMU_RESET_EP_OUT 0x02
489 #define OWN_UPDATE BIT(0)
496 #define RX_AGGR_NUM_MASK 0x1ff
499 #define POWER_CUT 0x0100
502 #define RESUME_INDICATE 0x0001
508 #define FORCE_SUPER BIT(0)
511 #define UPS_FORCE_PWR_DOWN BIT(0)
514 #define EN_ALL_SPEED BIT(0)
535 #define RX_AGG_DISABLE 0x0010
536 #define RX_ZERO_EN 0x0080
539 #define U2P3_ENABLE 0x0001
543 #define PWR_EN 0x0001
544 #define PHASE2_EN 0x0008
549 #define PCUT_STATUS 0x0001
557 #define WTD1_EN BIT(0)
560 #define TIMER11_EN 0x0001
564 #define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */
566 #define LPM_TIMER_MASK 0x0c
567 #define LPM_TIMER_500MS 0x04 /* 500 ms */
568 #define LPM_TIMER_500US 0x0c /* 500 us */
569 #define ROK_EXIT_LPM 0x02
572 #define SEN_VAL_MASK 0xf800
573 #define SEN_VAL_NORMAL 0xa000
574 #define SEL_RXIDLE 0x0100
580 #define SAW_CNT_1MS_MASK 0x0fff
584 #define UPS_FLAGS_R_TUNE BIT(0)
589 #define UPS_FLAGS_SPEED_MASK (0xf << 16)
615 #define ENPWRSAVE 0x8000
616 #define ENPDNPS 0x0200
617 #define LINKENA 0x0100
618 #define DIS_SDSAVE 0x0010
621 #define PHY_STAT_MASK 0x0007
633 #define EEE_CLKDIV_EN 0x8000
634 #define EN_ALDPS 0x0004
635 #define EN_10M_PLLOFF 0x0001
638 #define RG_TXLPI_MSK_HFDUP 0x8000
639 #define RG_MATCLR_EN 0x4000
640 #define EEE_10_CAP 0x2000
641 #define EEE_NWAY_EN 0x1000
642 #define TX_QUIET_EN 0x0200
643 #define RX_QUIET_EN 0x0100
644 #define sd_rise_time_mask 0x0070
646 #define RG_RXLPI_MSK_HFDUP 0x0008
647 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
650 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
651 #define RG_DACQUIET_EN 0x0400
652 #define RG_LDVQUIET_EN 0x0200
653 #define RG_CKRSEL 0x0020
654 #define RG_EEEPRG_EN 0x0010
657 #define fast_snr_mask 0xff80
658 #define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */
659 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
660 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
664 #define FUN_ADDR 0x0000
665 #define FUN_DATA 0x4000
666 /* bit[4:0] device addr */
669 #define CTAP_SHORT_EN 0x0040
670 #define EEE10_EN 0x0010
677 #define EN_10M_BGOFF 0x0080
683 #define TXDIS_STATE 0x01
684 #define ABD_STATE 0x02
693 #define PATCH_LOCK BIT(0)
696 #define CKADSEL_L 0x0100
697 #define ADC_EN 0x0080
698 #define EN_EMI_L 0x0040
709 #define LPF_AUTO_TUNE 0x8000
712 #define GDAC_IB_UPALL 0x0008
715 #define AMP_DN 0x0200
718 #define RX_DRIVING_MASK 0x6000
721 #define PHY_PATCH_LOCK 0x0001
724 #define AD_MASK 0xfee0
725 #define BND_MASK 0x0004
726 #define BD_MASK 0x0001
727 #define EFUSE 0xcfdb
728 #define PASS_THRU_MASK 0x1
730 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
738 _1000bps = 0x10,
739 _100bps = 0x08,
740 _10bps = 0x04,
741 LINK_STATUS = 0x02,
742 FULL_DUP = 0x01,
757 #define INTR_LINK 0x0004
768 RTL8152_INACCESSIBLE = 0,
782 #define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e
783 #define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054
784 #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082
785 #define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c
786 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387
787 #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062
807 #define RX_LEN_MASK 0x7fff
833 #define GTTCPHO_MAX 0x7fU
834 #define TX_LEN_MAX 0x3ffffU
842 #define MSS_MAX 0x7ffU
844 #define TCPHO_MAX 0x7ffU
990 FW_FLAGS_USB = 0,
1004 FW_FIXUP_AND = 0,
1147 RTL_FW_END = 0,
1165 RTL_VER_UNKNOWN = 0,
1188 TX_CSUM_SUCCESS = 0,
1193 #define RTL_ADVERTISED_10_HALF BIT(0)
1249 if (ret >= 0) { in r8152_control_msg()
1250 tp->reg_access_reset_count = 0; in r8152_control_msg()
1313 if (ret < 0) in get_registers()
1314 memset(data, 0xff, size); in get_registers()
1352 int ret = 0; in generic_ocp_read()
1361 if ((u32)index + (u32)size > 0xffff) in generic_ocp_read()
1367 if (ret < 0) in generic_ocp_read()
1375 if (ret < 0) in generic_ocp_read()
1380 size = 0; in generic_ocp_read()
1405 if ((u32)index + (u32)size > 0xffff) in generic_ocp_write()
1413 /* Split the first DWORD if the byte_en is not 0xff */ in generic_ocp_write()
1416 if (ret < 0) in generic_ocp_write()
1427 /* Split the last DWORD if the byte_en is not 0xff */ in generic_ocp_write()
1436 if (ret < 0) in generic_ocp_write()
1446 if (ret < 0) in generic_ocp_write()
1451 size = 0; in generic_ocp_write()
1516 data &= 0xffff; in ocp_read_word()
1523 u32 mask = 0xffff; in ocp_write_word()
1554 data &= 0xff; in ocp_read_byte()
1561 u32 mask = 0xff; in ocp_write_byte()
1584 ocp_base = addr & 0xf000; in ocp_reg_read()
1590 ocp_index = (addr & 0x0fff) | 0xb000; in ocp_reg_read()
1598 ocp_base = addr & 0xf000; in ocp_reg_write()
1604 ocp_index = (addr & 0x0fff) | 0xb000; in ocp_reg_write()
1679 if (ret < 0) in __rtl8152_set_mac_address()
1723 mac_strlen = 0x16; in vendor_mac_passthru_addr_read()
1727 if ((ocp_data & AD_MASK) == 0x1000) { in vendor_mac_passthru_addr_read()
1738 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { in vendor_mac_passthru_addr_read()
1747 mac_strlen = 0x17; in vendor_mac_passthru_addr_read()
1762 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || in vendor_mac_passthru_addr_read()
1763 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { in vendor_mac_passthru_addr_read()
1769 if (!(ret == 0 && is_valid_ether_addr(buf))) { in vendor_mac_passthru_addr_read()
1794 if (ret < 0) { in determine_ethernet_addr()
1802 if (ret < 0) in determine_ethernet_addr()
1808 if (ret < 0) { in determine_ethernet_addr()
1817 return 0; in determine_ethernet_addr()
1830 if (ret < 0) in set_ethernet_addr()
1873 case 0: in read_bulk_callback()
1887 urb->actual_length = 0; in read_bulk_callback()
1974 case 0: /* success */ in intr_callback()
1997 if (INTR_LINK & __le16_to_cpu(d[0])) { in intr_callback()
2000 schedule_delayed_work(&tp->schedule, 0); in intr_callback()
2006 schedule_delayed_work(&tp->schedule, 0); in intr_callback()
2060 rx_agg->urb = usb_alloc_urb(0, mflags); in alloc_rx_agg()
2098 for (i = 0; i < RTL8152_MAX_TX; i++) { in free_all_mem()
2131 atomic_set(&tp->rx_count, 0); in alloc_all_mem()
2133 for (i = 0; i < RTL8152_MAX_RX; i++) { in alloc_all_mem()
2138 for (i = 0; i < RTL8152_MAX_TX; i++) { in alloc_all_mem()
2154 urb = usb_alloc_urb(0, GFP_KERNEL); in alloc_all_mem()
2169 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); in alloc_all_mem()
2182 return 0; in alloc_all_mem()
2237 if (skb_checksum_help(skb) < 0) in r8152_csum_workaround()
2267 swab16(opts2 & 0xffff)); in rtl_rx_vlan_tag()
2274 u32 opts1, opts2 = 0; in r8152_tx_csum()
2286 "Invalid transport offset 0x%x for TSO\n", in r8152_tx_csum()
2298 if (skb_cow_head(skb, 0)) { in r8152_tx_csum()
2319 "Invalid transport offset 0x%x\n", in r8152_tx_csum()
2370 agg->skb_num = 0; in r8152_tx_agg_fill()
2371 agg->skb_len = 0; in r8152_tx_agg_fill()
2403 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { in r8152_tx_agg_fill()
2439 if (ret < 0) in r8152_tx_agg_fill()
2447 if (ret < 0) in r8152_tx_agg_fill()
2527 int ret = 0, work_done = 0; in rx_bottom()
2560 int len_used = 0; in rx_bottom()
2577 if (urb->status != 0 || urb->actual_length < ETH_ZLEN) in rx_bottom()
2623 rx_frag_head_sz = 0; in rx_bottom()
2627 rx_frag_head_sz = 0; in rx_bottom()
2650 skb_add_rx_frag(skb, 0, agg->page, in rx_bottom()
2698 urb->actual_length = 0; in rx_bottom()
2748 } while (res == 0); in tx_bottom()
2777 return 0; in r8152_poll()
2800 return 0; in r8152_submit_rx()
2814 urb->actual_length = 0; in r8152_submit_rx()
2863 schedule_delayed_work(&tp->schedule, 0); in rtl8152_set_rx_mode()
2883 mc_filter[1] = 0xffffffff; in _rtl8152_set_rx_mode()
2884 mc_filter[0] = 0xffffffff; in _rtl8152_set_rx_mode()
2890 mc_filter[1] = 0xffffffff; in _rtl8152_set_rx_mode()
2891 mc_filter[0] = 0xffffffff; in _rtl8152_set_rx_mode()
2893 mc_filter[1] = 0; in _rtl8152_set_rx_mode()
2894 mc_filter[0] = 0; in _rtl8152_set_rx_mode()
2908 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); in _rtl8152_set_rx_mode()
2909 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); in _rtl8152_set_rx_mode()
2944 schedule_delayed_work(&tp->schedule, 0); in rtl8152_start_xmit()
3004 for (i = 0; i < 1000; i++) { in rtl8152_nic_reset()
3062 int ret = 0, i = 0; in rtl_start_rx()
3083 } else if (unlikely(ret < 0)) { in rtl_start_rx()
3137 return 0; in rtl_stop_rx()
3195 return 0; in rtl_enable()
3330 for (i = 0; i < RTL8152_MAX_TX; i++) in rtl_disable()
3335 for (i = 0; i < 1000; i++) { in rtl_disable()
3344 for (i = 0; i < 1000; i++) { in rtl_disable()
3421 if (ret < 0) in rtl8152_set_features()
3446 u32 wolopts = 0; in __rtl_get_wol()
3524 0x0403); in r8156_mac_clk_spd()
3528 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */ in r8156_mac_clk_spd()
3542 memset(u1u2, 0xff, sizeof(u1u2)); in r8153_u1u2en()
3544 memset(u1u2, 0x00, sizeof(u1u2)); in r8153_u1u2en()
3576 u32 ups_flags = 0; in r8153b_ups_flags()
3651 u32 ups_flags = 0; in r8156_ups_flags()
3682 ups_flags |= ups_flags_speed(0); in r8156_ups_flags()
3717 ups_flags |= 0 << 5; in r8156_ups_flags()
3722 case 0: in r8156_ups_flags()
3748 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ in r8153b_green_en()
3749 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ in r8153b_green_en()
3750 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ in r8153b_green_en()
3752 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ in r8153b_green_en()
3753 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ in r8153b_green_en()
3754 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ in r8153b_green_en()
3765 for (i = 0; i < 500; i++) { in r8153_phy_status()
3808 for (i = 0; i < 500; i++) { in r8153b_ups_en()
3850 for (i = 0; i < 500; i++) { in r8153c_ups_en()
4105 /* The bit 0 ~ 7 are relative with teredo settings. They are in r8153_teredo_off()
4108 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); in r8153_teredo_off()
4113 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); in r8153_teredo_off()
4114 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); in r8153_teredo_off()
4131 u16 bp[16] = {0}; in rtl_clear_bp()
4143 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0); in rtl_clear_bp()
4152 ocp_write_byte(tp, type, PLA_BP_EN, 0); in rtl_clear_bp()
4161 ocp_write_word(tp, type, USB_BP2_EN, 0); in rtl_clear_bp()
4170 ocp_write_word(tp, type, PLA_BP_BA, 0); in rtl_clear_bp()
4186 check = 0; in rtl_phy_patch_request()
4193 for (i = 0; wait && i < 5000; i++) { in rtl_phy_patch_request()
4211 return 0; in rtl_phy_patch_request()
4223 sram_write(tp, 0x0000, 0x0000); in rtl_patch_key_set()
4229 sram_write(tp, key_addr, 0x0000); in rtl_patch_key_set()
4243 return 0; in rtl_pre_ram_code()
4248 rtl_patch_key_set(tp, key_addr, 0); in rtl_post_ram_code()
4252 return 0; in rtl_post_ram_code()
4295 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) { in rtl8152_is_fw_phy_speed_up_ok()
4421 fw_reg = 0xa014; in rtl8152_is_fw_phy_nc_ok()
4422 ba_reg = 0xa012; in rtl8152_is_fw_phy_nc_ok()
4423 patch_en_addr = 0xa01a; in rtl8152_is_fw_phy_nc_ok()
4424 mode_reg = 0xb820; in rtl8152_is_fw_phy_nc_ok()
4425 bp_start = 0xa000; in rtl8152_is_fw_phy_nc_ok()
4500 fw_reg = 0xf800; in rtl8152_is_fw_mac_ok()
4502 bp_en_addr = 0; in rtl8152_is_fw_mac_ok()
4516 fw_reg = 0xf800; in rtl8152_is_fw_mac_ok()
4523 fw_reg = 0xf800; in rtl8152_is_fw_mac_ok()
4538 fw_reg = 0xf800; in rtl8152_is_fw_mac_ok()
4551 fw_reg = 0xe600; in rtl8152_is_fw_mac_ok()
4636 alg = crypto_alloc_shash("sha256", 0, 0); in rtl8152_fw_verify_checksum()
4678 unsigned long fw_flags = 0; in rtl8152_check_firmware()
4953 return 0; in rtl8152_check_firmware()
4990 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB); in rtl_ram_code_speed_up()
4999 for (i = 0; i < 1000; i++) { in rtl_ram_code_speed_up()
5031 return 0; in rtl8152_fw_phy_ver()
5081 for (i = 0; i < num; i++) in rtl8152_fw_phy_union_apply()
5091 for (i = 0; i < num; i++) in rtl8152_fw_phy_union_apply()
5095 for (i = 0; i < num; i++) in rtl8152_fw_phy_union_apply()
5123 for (i = 0; i < num; i++) in rtl8152_fw_phy_nc_apply()
5131 for (i = 0; i < num; i++) { in rtl8152_fw_phy_nc_apply()
5181 if (generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, in rtl8152_fw_mac_apply()
5182 data, type) < 0) { in rtl8152_fw_mac_apply()
5193 mac->bp, type) < 0) { in rtl8152_fw_mac_apply()
5217 u16 key_addr = 0; in rtl8152_apply_firmware()
5307 rc = 0; in rtl8152_request_firmware()
5312 if (rc < 0) in rtl8152_request_firmware()
5316 if (rc < 0) in rtl8152_request_firmware()
5356 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); in r8152_mmd_read()
5365 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); in r8152_mmd_write()
5449 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); in rtl_eee_enable()
5464 ocp_reg_write(tp, OCP_EEE_ADV, 0); in rtl_eee_enable()
5477 ocp_reg_write(tp, OCP_EEE_ADV, 0); in rtl_eee_enable()
5518 for (i = 0; i < 1000; i++) { in wait_oob_link_list_ready()
5534 for (i = 0; i < 100; i++) { in r8156b_wait_loading_flash()
5555 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); in r8152b_exit_oob()
5656 for (i = 0; i < 104; i++) { in r8153_pre_firmware_1()
5666 return 0; in r8153_pre_firmware_1()
5678 return 0; in r8153_post_firmware_1()
5691 return 0; in r8153_pre_firmware_2()
5701 ocp_data |= BIT(0); in r8153_post_firmware_2()
5719 return 0; in r8153_post_firmware_2()
5734 return 0; in r8153_post_firmware_3()
5743 return 0; in r8153b_pre_firmware_1()
5754 ocp_data |= BIT(0); in r8153b_post_firmware_1()
5770 return 0; in r8153b_post_firmware_1()
5785 return 0; in r8153c_post_firmware_1()
5797 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e); in r8156a_post_firmware_1()
5798 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9); in r8156a_post_firmware_1()
5800 return 0; in r8156a_post_firmware_1()
5816 for (i = 0; i < 20; i++) { in r8153_aldps_en()
5820 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) in r8153_aldps_en()
5857 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); in r8153_hw_phy_cfg()
5864 sram_write(tp, SRAM_LPF_CFG, 0xf70f); in r8153_hw_phy_cfg()
5867 sram_write(tp, SRAM_10M_AMP1, 0x00af); in r8153_hw_phy_cfg()
5868 sram_write(tp, SRAM_10M_AMP2, 0x0208); in r8153_hw_phy_cfg()
5922 data = r8153_phy_status(tp, 0); in r8153b_hw_phy_cfg()
5949 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake in r8153b_hw_phy_cfg()
5953 ocp_data = r8152_efuse_read(tp, 0x7d); in r8153b_hw_phy_cfg()
5954 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); in r8153b_hw_phy_cfg()
5955 if (data != 0xffff) in r8153b_hw_phy_cfg()
5959 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] in r8153b_hw_phy_cfg()
5962 ocp_data = ocp_reg_read(tp, 0xc426); in r8153b_hw_phy_cfg()
5963 ocp_data &= 0x3fff; in r8153b_hw_phy_cfg()
5991 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); in r8153b_hw_phy_cfg()
6109 * type. Set it to zero. bits[7:0] are the W1C bits about in r8153_enter_oob()
6112 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); in r8153_enter_oob()
6192 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); in rtl8156_enable()
6194 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); in rtl8156_enable()
6197 /* USB 0xb45e[3:0] l1_nyet_hird */ in rtl8156_enable()
6199 ocp_data &= ~0xf; in rtl8156_enable()
6201 ocp_data |= 0xf; in rtl8156_enable()
6203 ocp_data |= 0x1; in rtl8156_enable()
6219 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 0); in rtl8156_disable()
6220 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0); in rtl8156_disable()
6255 ocp_data &= ~0xf; in rtl8156b_enable()
6257 ocp_data |= 0xf; in rtl8156b_enable()
6259 ocp_data |= 0x1; in rtl8156b_enable()
6277 int ret = 0; in rtl8152_set_speed()
6317 tp->mii.full_duplex = 0; in rtl8152_set_speed()
6392 tp->mii.force_media = 0; in rtl8152_set_speed()
6403 for (i = 0; i < 50; i++) { in rtl8152_set_speed()
6405 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) in rtl8152_set_speed()
6603 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02); in rtl8153c_up()
6604 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08); in rtl8153c_up()
6688 ocp_data |= 0x08; in rtl8156_up()
6699 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); in rtl8156_up()
6747 * type. Set it to zero. bits[7:0] are the W1C bits about in rtl8156_down()
6750 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); in rtl8156_down()
6774 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); in rtl8152_in_nway()
6775 tp->ocp_base = 0x2000; in rtl8152_in_nway()
6776 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ in rtl8152_in_nway()
6777 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); in rtl8152_in_nway()
6780 if (nway_state & 0xc000) in rtl8152_in_nway()
6788 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; in rtl8153_in_nway()
6800 /* Select force mode through 0xa5b4 bit 15 in r8156_mdio_force_mode()
6801 * 0: MDIO force mode in r8156_mdio_force_mode()
6804 data = ocp_reg_read(tp, 0xa5b4); in r8156_mdio_force_mode()
6807 ocp_reg_write(tp, 0xa5b4, data); in r8156_mdio_force_mode()
6858 if (usb_autopm_get_interface(tp->intf) < 0) in rtl_work_func_t()
6865 schedule_delayed_work(&tp->schedule, 0); in rtl_work_func_t()
6897 if (usb_autopm_get_interface(tp->intf) < 0) in rtl_hw_phy_work_func_t()
6953 int res = 0; in rtl8152_open()
6965 if (res < 0) in rtl8152_open()
6994 return 0; in rtl8152_open()
7008 int res = 0; in rtl8152_close()
7021 if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { in rtl8152_close()
7103 for (i = 0; i < 500; i++) { in r8153_init()
7113 data = r8153_phy_status(tp, 0); in r8153_init()
7144 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) in r8153_init()
7151 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) in r8153_init()
7192 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); in r8153_init()
7243 for (i = 0; i < 500; i++) { in r8153b_init()
7253 data = r8153_phy_status(tp, 0); in r8153b_init()
7265 /* MSC timer = 0xfff * 8ms = 32760 ms */ in r8153b_init()
7266 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); in r8153b_init()
7295 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { in r8153b_init()
7330 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0); in r8153c_init()
7332 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data); in r8153c_init()
7334 for (i = 0; i < 500; i++) { in r8153c_init()
7344 data = r8153_phy_status(tp, 0); in r8153c_init()
7356 /* MSC timer = 0xfff * 8ms = 32760 ms */ in r8153c_init()
7357 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); in r8153c_init()
7407 data = r8153_phy_status(tp, 0); in r8156_hw_phy_cfg()
7412 data = ocp_reg_read(tp, 0xa468); in r8156_hw_phy_cfg()
7414 ocp_reg_write(tp, 0xa468, data); in r8156_hw_phy_cfg()
7438 data = ocp_reg_read(tp, 0xad40); in r8156_hw_phy_cfg()
7439 data &= ~0x3ff; in r8156_hw_phy_cfg()
7441 ocp_reg_write(tp, 0xad40, data); in r8156_hw_phy_cfg()
7443 data = ocp_reg_read(tp, 0xad4e); in r8156_hw_phy_cfg()
7445 ocp_reg_write(tp, 0xad4e, data); in r8156_hw_phy_cfg()
7446 data = ocp_reg_read(tp, 0xad16); in r8156_hw_phy_cfg()
7447 data &= ~0x3ff; in r8156_hw_phy_cfg()
7448 data |= 0x6; in r8156_hw_phy_cfg()
7449 ocp_reg_write(tp, 0xad16, data); in r8156_hw_phy_cfg()
7450 data = ocp_reg_read(tp, 0xad32); in r8156_hw_phy_cfg()
7451 data &= ~0x3f; in r8156_hw_phy_cfg()
7453 ocp_reg_write(tp, 0xad32, data); in r8156_hw_phy_cfg()
7454 data = ocp_reg_read(tp, 0xac08); in r8156_hw_phy_cfg()
7456 ocp_reg_write(tp, 0xac08, data); in r8156_hw_phy_cfg()
7457 data = ocp_reg_read(tp, 0xac8a); in r8156_hw_phy_cfg()
7460 ocp_reg_write(tp, 0xac8a, data); in r8156_hw_phy_cfg()
7461 data = ocp_reg_read(tp, 0xad18); in r8156_hw_phy_cfg()
7463 ocp_reg_write(tp, 0xad18, data); in r8156_hw_phy_cfg()
7464 data = ocp_reg_read(tp, 0xad1a); in r8156_hw_phy_cfg()
7465 data |= 0x3ff; in r8156_hw_phy_cfg()
7466 ocp_reg_write(tp, 0xad1a, data); in r8156_hw_phy_cfg()
7467 data = ocp_reg_read(tp, 0xad1c); in r8156_hw_phy_cfg()
7468 data |= 0x3ff; in r8156_hw_phy_cfg()
7469 ocp_reg_write(tp, 0xad1c, data); in r8156_hw_phy_cfg()
7471 data = sram_read(tp, 0x80ea); in r8156_hw_phy_cfg()
7472 data &= ~0xff00; in r8156_hw_phy_cfg()
7473 data |= 0xc400; in r8156_hw_phy_cfg()
7474 sram_write(tp, 0x80ea, data); in r8156_hw_phy_cfg()
7475 data = sram_read(tp, 0x80eb); in r8156_hw_phy_cfg()
7476 data &= ~0x0700; in r8156_hw_phy_cfg()
7477 data |= 0x0300; in r8156_hw_phy_cfg()
7478 sram_write(tp, 0x80eb, data); in r8156_hw_phy_cfg()
7479 data = sram_read(tp, 0x80f8); in r8156_hw_phy_cfg()
7480 data &= ~0xff00; in r8156_hw_phy_cfg()
7481 data |= 0x1c00; in r8156_hw_phy_cfg()
7482 sram_write(tp, 0x80f8, data); in r8156_hw_phy_cfg()
7483 data = sram_read(tp, 0x80f1); in r8156_hw_phy_cfg()
7484 data &= ~0xff00; in r8156_hw_phy_cfg()
7485 data |= 0x3000; in r8156_hw_phy_cfg()
7486 sram_write(tp, 0x80f1, data); in r8156_hw_phy_cfg()
7488 data = sram_read(tp, 0x80fe); in r8156_hw_phy_cfg()
7489 data &= ~0xff00; in r8156_hw_phy_cfg()
7490 data |= 0xa500; in r8156_hw_phy_cfg()
7491 sram_write(tp, 0x80fe, data); in r8156_hw_phy_cfg()
7492 data = sram_read(tp, 0x8102); in r8156_hw_phy_cfg()
7493 data &= ~0xff00; in r8156_hw_phy_cfg()
7494 data |= 0x5000; in r8156_hw_phy_cfg()
7495 sram_write(tp, 0x8102, data); in r8156_hw_phy_cfg()
7496 data = sram_read(tp, 0x8015); in r8156_hw_phy_cfg()
7497 data &= ~0xff00; in r8156_hw_phy_cfg()
7498 data |= 0x3300; in r8156_hw_phy_cfg()
7499 sram_write(tp, 0x8015, data); in r8156_hw_phy_cfg()
7500 data = sram_read(tp, 0x8100); in r8156_hw_phy_cfg()
7501 data &= ~0xff00; in r8156_hw_phy_cfg()
7502 data |= 0x7000; in r8156_hw_phy_cfg()
7503 sram_write(tp, 0x8100, data); in r8156_hw_phy_cfg()
7504 data = sram_read(tp, 0x8014); in r8156_hw_phy_cfg()
7505 data &= ~0xff00; in r8156_hw_phy_cfg()
7506 data |= 0xf000; in r8156_hw_phy_cfg()
7507 sram_write(tp, 0x8014, data); in r8156_hw_phy_cfg()
7508 data = sram_read(tp, 0x8016); in r8156_hw_phy_cfg()
7509 data &= ~0xff00; in r8156_hw_phy_cfg()
7510 data |= 0x6500; in r8156_hw_phy_cfg()
7511 sram_write(tp, 0x8016, data); in r8156_hw_phy_cfg()
7512 data = sram_read(tp, 0x80dc); in r8156_hw_phy_cfg()
7513 data &= ~0xff00; in r8156_hw_phy_cfg()
7514 data |= 0xed00; in r8156_hw_phy_cfg()
7515 sram_write(tp, 0x80dc, data); in r8156_hw_phy_cfg()
7516 data = sram_read(tp, 0x80df); in r8156_hw_phy_cfg()
7518 sram_write(tp, 0x80df, data); in r8156_hw_phy_cfg()
7519 data = sram_read(tp, 0x80e1); in r8156_hw_phy_cfg()
7521 sram_write(tp, 0x80e1, data); in r8156_hw_phy_cfg()
7523 data = ocp_reg_read(tp, 0xbf06); in r8156_hw_phy_cfg()
7524 data &= ~0x003f; in r8156_hw_phy_cfg()
7525 data |= 0x0038; in r8156_hw_phy_cfg()
7526 ocp_reg_write(tp, 0xbf06, data); in r8156_hw_phy_cfg()
7528 sram_write(tp, 0x819f, 0xddb6); in r8156_hw_phy_cfg()
7530 ocp_reg_write(tp, 0xbc34, 0x5555); in r8156_hw_phy_cfg()
7531 data = ocp_reg_read(tp, 0xbf0a); in r8156_hw_phy_cfg()
7532 data &= ~0x0e00; in r8156_hw_phy_cfg()
7533 data |= 0x0a00; in r8156_hw_phy_cfg()
7534 ocp_reg_write(tp, 0xbf0a, data); in r8156_hw_phy_cfg()
7536 data = ocp_reg_read(tp, 0xbd2c); in r8156_hw_phy_cfg()
7538 ocp_reg_write(tp, 0xbd2c, data); in r8156_hw_phy_cfg()
7541 data = ocp_reg_read(tp, 0xad16); in r8156_hw_phy_cfg()
7542 data |= 0x3ff; in r8156_hw_phy_cfg()
7543 ocp_reg_write(tp, 0xad16, data); in r8156_hw_phy_cfg()
7544 data = ocp_reg_read(tp, 0xad32); in r8156_hw_phy_cfg()
7545 data &= ~0x3f; in r8156_hw_phy_cfg()
7547 ocp_reg_write(tp, 0xad32, data); in r8156_hw_phy_cfg()
7548 data = ocp_reg_read(tp, 0xac08); in r8156_hw_phy_cfg()
7550 ocp_reg_write(tp, 0xac08, data); in r8156_hw_phy_cfg()
7551 data = ocp_reg_read(tp, 0xacc0); in r8156_hw_phy_cfg()
7552 data &= ~0x3; in r8156_hw_phy_cfg()
7554 ocp_reg_write(tp, 0xacc0, data); in r8156_hw_phy_cfg()
7555 data = ocp_reg_read(tp, 0xad40); in r8156_hw_phy_cfg()
7556 data &= ~0xe7; in r8156_hw_phy_cfg()
7558 ocp_reg_write(tp, 0xad40, data); in r8156_hw_phy_cfg()
7559 data = ocp_reg_read(tp, 0xac14); in r8156_hw_phy_cfg()
7561 ocp_reg_write(tp, 0xac14, data); in r8156_hw_phy_cfg()
7562 data = ocp_reg_read(tp, 0xac80); in r8156_hw_phy_cfg()
7564 ocp_reg_write(tp, 0xac80, data); in r8156_hw_phy_cfg()
7565 data = ocp_reg_read(tp, 0xac5e); in r8156_hw_phy_cfg()
7566 data &= ~0x7; in r8156_hw_phy_cfg()
7568 ocp_reg_write(tp, 0xac5e, data); in r8156_hw_phy_cfg()
7569 ocp_reg_write(tp, 0xad4c, 0x00a8); in r8156_hw_phy_cfg()
7570 ocp_reg_write(tp, 0xac5c, 0x01ff); in r8156_hw_phy_cfg()
7571 data = ocp_reg_read(tp, 0xac8a); in r8156_hw_phy_cfg()
7572 data &= ~0xf0; in r8156_hw_phy_cfg()
7574 ocp_reg_write(tp, 0xac8a, data); in r8156_hw_phy_cfg()
7575 ocp_reg_write(tp, 0xb87c, 0x8157); in r8156_hw_phy_cfg()
7576 data = ocp_reg_read(tp, 0xb87e); in r8156_hw_phy_cfg()
7577 data &= ~0xff00; in r8156_hw_phy_cfg()
7578 data |= 0x0500; in r8156_hw_phy_cfg()
7579 ocp_reg_write(tp, 0xb87e, data); in r8156_hw_phy_cfg()
7580 ocp_reg_write(tp, 0xb87c, 0x8159); in r8156_hw_phy_cfg()
7581 data = ocp_reg_read(tp, 0xb87e); in r8156_hw_phy_cfg()
7582 data &= ~0xff00; in r8156_hw_phy_cfg()
7583 data |= 0x0700; in r8156_hw_phy_cfg()
7584 ocp_reg_write(tp, 0xb87e, data); in r8156_hw_phy_cfg()
7587 ocp_reg_write(tp, 0xb87c, 0x80a2); in r8156_hw_phy_cfg()
7588 ocp_reg_write(tp, 0xb87e, 0x0153); in r8156_hw_phy_cfg()
7589 ocp_reg_write(tp, 0xb87c, 0x809c); in r8156_hw_phy_cfg()
7590 ocp_reg_write(tp, 0xb87e, 0x0153); in r8156_hw_phy_cfg()
7593 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056); in r8156_hw_phy_cfg()
7599 sram_write(tp, 0x8257, 0x020f); /* XG PLL */ in r8156_hw_phy_cfg()
7600 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */ in r8156_hw_phy_cfg()
7623 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); in r8156_hw_phy_cfg()
7630 data = ocp_reg_read(tp, 0xd068); in r8156_hw_phy_cfg()
7632 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7635 data = sram_read(tp, 0x81a2); in r8156_hw_phy_cfg()
7637 sram_write(tp, 0x81a2, data); in r8156_hw_phy_cfg()
7638 data = ocp_reg_read(tp, 0xb54c); in r8156_hw_phy_cfg()
7639 data &= ~0xff00; in r8156_hw_phy_cfg()
7640 data |= 0xdb00; in r8156_hw_phy_cfg()
7641 ocp_reg_write(tp, 0xb54c, data); in r8156_hw_phy_cfg()
7644 data = ocp_reg_read(tp, 0xa454); in r8156_hw_phy_cfg()
7645 data &= ~BIT(0); in r8156_hw_phy_cfg()
7646 ocp_reg_write(tp, 0xa454, data); in r8156_hw_phy_cfg()
7652 data = ocp_reg_read(tp, 0xad4e); in r8156_hw_phy_cfg()
7654 ocp_reg_write(tp, 0xad4e, data); in r8156_hw_phy_cfg()
7655 data = ocp_reg_read(tp, 0xa86a); in r8156_hw_phy_cfg()
7656 data &= ~BIT(0); in r8156_hw_phy_cfg()
7657 ocp_reg_write(tp, 0xa86a, data); in r8156_hw_phy_cfg()
7661 (ocp_reg_read(tp, 0xd068) & BIT(1))) { in r8156_hw_phy_cfg()
7664 data = ocp_reg_read(tp, 0xd068); in r8156_hw_phy_cfg()
7665 data &= ~0x1f; in r8156_hw_phy_cfg()
7666 data |= 0x1; /* p0 */ in r8156_hw_phy_cfg()
7667 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7668 swap_a = ocp_reg_read(tp, 0xd06a); in r8156_hw_phy_cfg()
7669 data &= ~0x18; in r8156_hw_phy_cfg()
7670 data |= 0x18; /* p3 */ in r8156_hw_phy_cfg()
7671 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7672 swap_b = ocp_reg_read(tp, 0xd06a); in r8156_hw_phy_cfg()
7673 data &= ~0x18; /* p0 */ in r8156_hw_phy_cfg()
7674 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7675 ocp_reg_write(tp, 0xd06a, in r8156_hw_phy_cfg()
7676 (swap_a & ~0x7ff) | (swap_b & 0x7ff)); in r8156_hw_phy_cfg()
7677 data |= 0x18; /* p3 */ in r8156_hw_phy_cfg()
7678 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7679 ocp_reg_write(tp, 0xd06a, in r8156_hw_phy_cfg()
7680 (swap_b & ~0x7ff) | (swap_a & 0x7ff)); in r8156_hw_phy_cfg()
7681 data &= ~0x18; in r8156_hw_phy_cfg()
7682 data |= 0x08; /* p1 */ in r8156_hw_phy_cfg()
7683 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7684 swap_a = ocp_reg_read(tp, 0xd06a); in r8156_hw_phy_cfg()
7685 data &= ~0x18; in r8156_hw_phy_cfg()
7686 data |= 0x10; /* p2 */ in r8156_hw_phy_cfg()
7687 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7688 swap_b = ocp_reg_read(tp, 0xd06a); in r8156_hw_phy_cfg()
7689 data &= ~0x18; in r8156_hw_phy_cfg()
7690 data |= 0x08; /* p1 */ in r8156_hw_phy_cfg()
7691 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7692 ocp_reg_write(tp, 0xd06a, in r8156_hw_phy_cfg()
7693 (swap_a & ~0x7ff) | (swap_b & 0x7ff)); in r8156_hw_phy_cfg()
7694 data &= ~0x18; in r8156_hw_phy_cfg()
7695 data |= 0x10; /* p2 */ in r8156_hw_phy_cfg()
7696 ocp_reg_write(tp, 0xd068, data); in r8156_hw_phy_cfg()
7697 ocp_reg_write(tp, 0xd06a, in r8156_hw_phy_cfg()
7698 (swap_b & ~0x7ff) | (swap_a & 0x7ff)); in r8156_hw_phy_cfg()
7699 swap_a = ocp_reg_read(tp, 0xbd5a); in r8156_hw_phy_cfg()
7700 swap_b = ocp_reg_read(tp, 0xbd5c); in r8156_hw_phy_cfg()
7701 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) | in r8156_hw_phy_cfg()
7702 ((swap_b & 0x1f) << 8) | in r8156_hw_phy_cfg()
7703 ((swap_b >> 8) & 0x1f)); in r8156_hw_phy_cfg()
7704 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) | in r8156_hw_phy_cfg()
7705 ((swap_a & 0x1f) << 8) | in r8156_hw_phy_cfg()
7706 ((swap_a >> 8) & 0x1f)); in r8156_hw_phy_cfg()
7707 swap_a = ocp_reg_read(tp, 0xbc18); in r8156_hw_phy_cfg()
7708 swap_b = ocp_reg_read(tp, 0xbc1a); in r8156_hw_phy_cfg()
7709 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) | in r8156_hw_phy_cfg()
7710 ((swap_b & 0x1f) << 8) | in r8156_hw_phy_cfg()
7711 ((swap_b >> 8) & 0x1f)); in r8156_hw_phy_cfg()
7712 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) | in r8156_hw_phy_cfg()
7713 ((swap_a & 0x1f) << 8) | in r8156_hw_phy_cfg()
7714 ((swap_a >> 8) & 0x1f)); in r8156_hw_phy_cfg()
7728 data = ocp_reg_read(tp, 0xa428); in r8156_hw_phy_cfg()
7730 ocp_reg_write(tp, 0xa428, data); in r8156_hw_phy_cfg()
7731 data = ocp_reg_read(tp, 0xa5ea); in r8156_hw_phy_cfg()
7732 data &= ~BIT(0); in r8156_hw_phy_cfg()
7733 ocp_reg_write(tp, 0xa5ea, data); in r8156_hw_phy_cfg()
7734 tp->ups_info.lite_mode = 0; in r8156_hw_phy_cfg()
7753 ocp_reg_write(tp, 0xbf86, 0x9000); in r8156b_hw_phy_cfg()
7754 data = ocp_reg_read(tp, 0xc402); in r8156b_hw_phy_cfg()
7756 ocp_reg_write(tp, 0xc402, data); in r8156b_hw_phy_cfg()
7758 ocp_reg_write(tp, 0xc402, data); in r8156b_hw_phy_cfg()
7759 ocp_reg_write(tp, 0xbd86, 0x1010); in r8156b_hw_phy_cfg()
7760 ocp_reg_write(tp, 0xbd88, 0x1010); in r8156b_hw_phy_cfg()
7761 data = ocp_reg_read(tp, 0xbd4e); in r8156b_hw_phy_cfg()
7764 ocp_reg_write(tp, 0xbd4e, data); in r8156b_hw_phy_cfg()
7765 data = ocp_reg_read(tp, 0xbf46); in r8156b_hw_phy_cfg()
7766 data &= ~0xf00; in r8156b_hw_phy_cfg()
7767 data |= 0x700; in r8156b_hw_phy_cfg()
7768 ocp_reg_write(tp, 0xbf46, data); in r8156b_hw_phy_cfg()
7784 data = r8153_phy_status(tp, 0); in r8156b_hw_phy_cfg()
7789 data = ocp_reg_read(tp, 0xa466); in r8156b_hw_phy_cfg()
7790 data &= ~BIT(0); in r8156b_hw_phy_cfg()
7791 ocp_reg_write(tp, 0xa466, data); in r8156b_hw_phy_cfg()
7793 data = ocp_reg_read(tp, 0xa468); in r8156b_hw_phy_cfg()
7795 ocp_reg_write(tp, 0xa468, data); in r8156b_hw_phy_cfg()
7825 data = ocp_reg_read(tp, 0xbc08); in r8156b_hw_phy_cfg()
7827 ocp_reg_write(tp, 0xbc08, data); in r8156b_hw_phy_cfg()
7829 data = sram_read(tp, 0x8fff); in r8156b_hw_phy_cfg()
7830 data &= ~0xff00; in r8156b_hw_phy_cfg()
7831 data |= 0x0400; in r8156b_hw_phy_cfg()
7832 sram_write(tp, 0x8fff, data); in r8156b_hw_phy_cfg()
7834 data = ocp_reg_read(tp, 0xacda); in r8156b_hw_phy_cfg()
7835 data |= 0xff00; in r8156b_hw_phy_cfg()
7836 ocp_reg_write(tp, 0xacda, data); in r8156b_hw_phy_cfg()
7837 data = ocp_reg_read(tp, 0xacde); in r8156b_hw_phy_cfg()
7838 data |= 0xf000; in r8156b_hw_phy_cfg()
7839 ocp_reg_write(tp, 0xacde, data); in r8156b_hw_phy_cfg()
7840 ocp_reg_write(tp, 0xac8c, 0x0ffc); in r8156b_hw_phy_cfg()
7841 ocp_reg_write(tp, 0xac46, 0xb7b4); in r8156b_hw_phy_cfg()
7842 ocp_reg_write(tp, 0xac50, 0x0fbc); in r8156b_hw_phy_cfg()
7843 ocp_reg_write(tp, 0xac3c, 0x9240); in r8156b_hw_phy_cfg()
7844 ocp_reg_write(tp, 0xac4e, 0x0db4); in r8156b_hw_phy_cfg()
7845 ocp_reg_write(tp, 0xacc6, 0x0707); in r8156b_hw_phy_cfg()
7846 ocp_reg_write(tp, 0xacc8, 0xa0d3); in r8156b_hw_phy_cfg()
7847 ocp_reg_write(tp, 0xad08, 0x0007); in r8156b_hw_phy_cfg()
7849 ocp_reg_write(tp, 0xb87c, 0x8560); in r8156b_hw_phy_cfg()
7850 ocp_reg_write(tp, 0xb87e, 0x19cc); in r8156b_hw_phy_cfg()
7851 ocp_reg_write(tp, 0xb87c, 0x8562); in r8156b_hw_phy_cfg()
7852 ocp_reg_write(tp, 0xb87e, 0x19cc); in r8156b_hw_phy_cfg()
7853 ocp_reg_write(tp, 0xb87c, 0x8564); in r8156b_hw_phy_cfg()
7854 ocp_reg_write(tp, 0xb87e, 0x19cc); in r8156b_hw_phy_cfg()
7855 ocp_reg_write(tp, 0xb87c, 0x8566); in r8156b_hw_phy_cfg()
7856 ocp_reg_write(tp, 0xb87e, 0x147d); in r8156b_hw_phy_cfg()
7857 ocp_reg_write(tp, 0xb87c, 0x8568); in r8156b_hw_phy_cfg()
7858 ocp_reg_write(tp, 0xb87e, 0x147d); in r8156b_hw_phy_cfg()
7859 ocp_reg_write(tp, 0xb87c, 0x856a); in r8156b_hw_phy_cfg()
7860 ocp_reg_write(tp, 0xb87e, 0x147d); in r8156b_hw_phy_cfg()
7861 ocp_reg_write(tp, 0xb87c, 0x8ffe); in r8156b_hw_phy_cfg()
7862 ocp_reg_write(tp, 0xb87e, 0x0907); in r8156b_hw_phy_cfg()
7863 ocp_reg_write(tp, 0xb87c, 0x80d6); in r8156b_hw_phy_cfg()
7864 ocp_reg_write(tp, 0xb87e, 0x2801); in r8156b_hw_phy_cfg()
7865 ocp_reg_write(tp, 0xb87c, 0x80f2); in r8156b_hw_phy_cfg()
7866 ocp_reg_write(tp, 0xb87e, 0x2801); in r8156b_hw_phy_cfg()
7867 ocp_reg_write(tp, 0xb87c, 0x80f4); in r8156b_hw_phy_cfg()
7868 ocp_reg_write(tp, 0xb87e, 0x6077); in r8156b_hw_phy_cfg()
7869 ocp_reg_write(tp, 0xb506, 0x01e7); in r8156b_hw_phy_cfg()
7871 ocp_reg_write(tp, 0xb87c, 0x8013); in r8156b_hw_phy_cfg()
7872 ocp_reg_write(tp, 0xb87e, 0x0700); in r8156b_hw_phy_cfg()
7873 ocp_reg_write(tp, 0xb87c, 0x8fb9); in r8156b_hw_phy_cfg()
7874 ocp_reg_write(tp, 0xb87e, 0x2801); in r8156b_hw_phy_cfg()
7875 ocp_reg_write(tp, 0xb87c, 0x8fba); in r8156b_hw_phy_cfg()
7876 ocp_reg_write(tp, 0xb87e, 0x0100); in r8156b_hw_phy_cfg()
7877 ocp_reg_write(tp, 0xb87c, 0x8fbc); in r8156b_hw_phy_cfg()
7878 ocp_reg_write(tp, 0xb87e, 0x1900); in r8156b_hw_phy_cfg()
7879 ocp_reg_write(tp, 0xb87c, 0x8fbe); in r8156b_hw_phy_cfg()
7880 ocp_reg_write(tp, 0xb87e, 0xe100); in r8156b_hw_phy_cfg()
7881 ocp_reg_write(tp, 0xb87c, 0x8fc0); in r8156b_hw_phy_cfg()
7882 ocp_reg_write(tp, 0xb87e, 0x0800); in r8156b_hw_phy_cfg()
7883 ocp_reg_write(tp, 0xb87c, 0x8fc2); in r8156b_hw_phy_cfg()
7884 ocp_reg_write(tp, 0xb87e, 0xe500); in r8156b_hw_phy_cfg()
7885 ocp_reg_write(tp, 0xb87c, 0x8fc4); in r8156b_hw_phy_cfg()
7886 ocp_reg_write(tp, 0xb87e, 0x0f00); in r8156b_hw_phy_cfg()
7887 ocp_reg_write(tp, 0xb87c, 0x8fc6); in r8156b_hw_phy_cfg()
7888 ocp_reg_write(tp, 0xb87e, 0xf100); in r8156b_hw_phy_cfg()
7889 ocp_reg_write(tp, 0xb87c, 0x8fc8); in r8156b_hw_phy_cfg()
7890 ocp_reg_write(tp, 0xb87e, 0x0400); in r8156b_hw_phy_cfg()
7891 ocp_reg_write(tp, 0xb87c, 0x8fca); in r8156b_hw_phy_cfg()
7892 ocp_reg_write(tp, 0xb87e, 0xf300); in r8156b_hw_phy_cfg()
7893 ocp_reg_write(tp, 0xb87c, 0x8fcc); in r8156b_hw_phy_cfg()
7894 ocp_reg_write(tp, 0xb87e, 0xfd00); in r8156b_hw_phy_cfg()
7895 ocp_reg_write(tp, 0xb87c, 0x8fce); in r8156b_hw_phy_cfg()
7896 ocp_reg_write(tp, 0xb87e, 0xff00); in r8156b_hw_phy_cfg()
7897 ocp_reg_write(tp, 0xb87c, 0x8fd0); in r8156b_hw_phy_cfg()
7898 ocp_reg_write(tp, 0xb87e, 0xfb00); in r8156b_hw_phy_cfg()
7899 ocp_reg_write(tp, 0xb87c, 0x8fd2); in r8156b_hw_phy_cfg()
7900 ocp_reg_write(tp, 0xb87e, 0x0100); in r8156b_hw_phy_cfg()
7901 ocp_reg_write(tp, 0xb87c, 0x8fd4); in r8156b_hw_phy_cfg()
7902 ocp_reg_write(tp, 0xb87e, 0xf400); in r8156b_hw_phy_cfg()
7903 ocp_reg_write(tp, 0xb87c, 0x8fd6); in r8156b_hw_phy_cfg()
7904 ocp_reg_write(tp, 0xb87e, 0xff00); in r8156b_hw_phy_cfg()
7905 ocp_reg_write(tp, 0xb87c, 0x8fd8); in r8156b_hw_phy_cfg()
7906 ocp_reg_write(tp, 0xb87e, 0xf600); in r8156b_hw_phy_cfg()
7911 ocp_reg_write(tp, 0xb87c, 0x813d); in r8156b_hw_phy_cfg()
7912 ocp_reg_write(tp, 0xb87e, 0x390e); in r8156b_hw_phy_cfg()
7913 ocp_reg_write(tp, 0xb87c, 0x814f); in r8156b_hw_phy_cfg()
7914 ocp_reg_write(tp, 0xb87e, 0x790e); in r8156b_hw_phy_cfg()
7915 ocp_reg_write(tp, 0xb87c, 0x80b0); in r8156b_hw_phy_cfg()
7916 ocp_reg_write(tp, 0xb87e, 0x0f31); in r8156b_hw_phy_cfg()
7917 data = ocp_reg_read(tp, 0xbf4c); in r8156b_hw_phy_cfg()
7919 ocp_reg_write(tp, 0xbf4c, data); in r8156b_hw_phy_cfg()
7920 data = ocp_reg_read(tp, 0xbcca); in r8156b_hw_phy_cfg()
7922 ocp_reg_write(tp, 0xbcca, data); in r8156b_hw_phy_cfg()
7923 ocp_reg_write(tp, 0xb87c, 0x8141); in r8156b_hw_phy_cfg()
7924 ocp_reg_write(tp, 0xb87e, 0x320e); in r8156b_hw_phy_cfg()
7925 ocp_reg_write(tp, 0xb87c, 0x8153); in r8156b_hw_phy_cfg()
7926 ocp_reg_write(tp, 0xb87e, 0x720e); in r8156b_hw_phy_cfg()
7927 ocp_reg_write(tp, 0xb87c, 0x8529); in r8156b_hw_phy_cfg()
7928 ocp_reg_write(tp, 0xb87e, 0x050e); in r8156b_hw_phy_cfg()
7933 sram_write(tp, 0x816c, 0xc4a0); in r8156b_hw_phy_cfg()
7934 sram_write(tp, 0x8170, 0xc4a0); in r8156b_hw_phy_cfg()
7935 sram_write(tp, 0x8174, 0x04a0); in r8156b_hw_phy_cfg()
7936 sram_write(tp, 0x8178, 0x04a0); in r8156b_hw_phy_cfg()
7937 sram_write(tp, 0x817c, 0x0719); in r8156b_hw_phy_cfg()
7938 sram_write(tp, 0x8ff4, 0x0400); in r8156b_hw_phy_cfg()
7939 sram_write(tp, 0x8ff1, 0x0404); in r8156b_hw_phy_cfg()
7941 ocp_reg_write(tp, 0xbf4a, 0x001b); in r8156b_hw_phy_cfg()
7942 ocp_reg_write(tp, 0xb87c, 0x8033); in r8156b_hw_phy_cfg()
7943 ocp_reg_write(tp, 0xb87e, 0x7c13); in r8156b_hw_phy_cfg()
7944 ocp_reg_write(tp, 0xb87c, 0x8037); in r8156b_hw_phy_cfg()
7945 ocp_reg_write(tp, 0xb87e, 0x7c13); in r8156b_hw_phy_cfg()
7946 ocp_reg_write(tp, 0xb87c, 0x803b); in r8156b_hw_phy_cfg()
7947 ocp_reg_write(tp, 0xb87e, 0xfc32); in r8156b_hw_phy_cfg()
7948 ocp_reg_write(tp, 0xb87c, 0x803f); in r8156b_hw_phy_cfg()
7949 ocp_reg_write(tp, 0xb87e, 0x7c13); in r8156b_hw_phy_cfg()
7950 ocp_reg_write(tp, 0xb87c, 0x8043); in r8156b_hw_phy_cfg()
7951 ocp_reg_write(tp, 0xb87e, 0x7c13); in r8156b_hw_phy_cfg()
7952 ocp_reg_write(tp, 0xb87c, 0x8047); in r8156b_hw_phy_cfg()
7953 ocp_reg_write(tp, 0xb87e, 0x7c13); in r8156b_hw_phy_cfg()
7955 ocp_reg_write(tp, 0xb87c, 0x8145); in r8156b_hw_phy_cfg()
7956 ocp_reg_write(tp, 0xb87e, 0x370e); in r8156b_hw_phy_cfg()
7957 ocp_reg_write(tp, 0xb87c, 0x8157); in r8156b_hw_phy_cfg()
7958 ocp_reg_write(tp, 0xb87e, 0x770e); in r8156b_hw_phy_cfg()
7959 ocp_reg_write(tp, 0xb87c, 0x8169); in r8156b_hw_phy_cfg()
7960 ocp_reg_write(tp, 0xb87e, 0x0d0a); in r8156b_hw_phy_cfg()
7961 ocp_reg_write(tp, 0xb87c, 0x817b); in r8156b_hw_phy_cfg()
7962 ocp_reg_write(tp, 0xb87e, 0x1d0a); in r8156b_hw_phy_cfg()
7964 data = sram_read(tp, 0x8217); in r8156b_hw_phy_cfg()
7965 data &= ~0xff00; in r8156b_hw_phy_cfg()
7966 data |= 0x5000; in r8156b_hw_phy_cfg()
7967 sram_write(tp, 0x8217, data); in r8156b_hw_phy_cfg()
7968 data = sram_read(tp, 0x821a); in r8156b_hw_phy_cfg()
7969 data &= ~0xff00; in r8156b_hw_phy_cfg()
7970 data |= 0x5000; in r8156b_hw_phy_cfg()
7971 sram_write(tp, 0x821a, data); in r8156b_hw_phy_cfg()
7972 sram_write(tp, 0x80da, 0x0403); in r8156b_hw_phy_cfg()
7973 data = sram_read(tp, 0x80dc); in r8156b_hw_phy_cfg()
7974 data &= ~0xff00; in r8156b_hw_phy_cfg()
7975 data |= 0x1000; in r8156b_hw_phy_cfg()
7976 sram_write(tp, 0x80dc, data); in r8156b_hw_phy_cfg()
7977 sram_write(tp, 0x80b3, 0x0384); in r8156b_hw_phy_cfg()
7978 sram_write(tp, 0x80b7, 0x2007); in r8156b_hw_phy_cfg()
7979 data = sram_read(tp, 0x80ba); in r8156b_hw_phy_cfg()
7980 data &= ~0xff00; in r8156b_hw_phy_cfg()
7981 data |= 0x6c00; in r8156b_hw_phy_cfg()
7982 sram_write(tp, 0x80ba, data); in r8156b_hw_phy_cfg()
7983 sram_write(tp, 0x80b5, 0xf009); in r8156b_hw_phy_cfg()
7984 data = sram_read(tp, 0x80bd); in r8156b_hw_phy_cfg()
7985 data &= ~0xff00; in r8156b_hw_phy_cfg()
7986 data |= 0x9f00; in r8156b_hw_phy_cfg()
7987 sram_write(tp, 0x80bd, data); in r8156b_hw_phy_cfg()
7988 sram_write(tp, 0x80c7, 0xf083); in r8156b_hw_phy_cfg()
7989 sram_write(tp, 0x80dd, 0x03f0); in r8156b_hw_phy_cfg()
7990 data = sram_read(tp, 0x80df); in r8156b_hw_phy_cfg()
7991 data &= ~0xff00; in r8156b_hw_phy_cfg()
7992 data |= 0x1000; in r8156b_hw_phy_cfg()
7993 sram_write(tp, 0x80df, data); in r8156b_hw_phy_cfg()
7994 sram_write(tp, 0x80cb, 0x2007); in r8156b_hw_phy_cfg()
7995 data = sram_read(tp, 0x80ce); in r8156b_hw_phy_cfg()
7996 data &= ~0xff00; in r8156b_hw_phy_cfg()
7997 data |= 0x6c00; in r8156b_hw_phy_cfg()
7998 sram_write(tp, 0x80ce, data); in r8156b_hw_phy_cfg()
7999 sram_write(tp, 0x80c9, 0x8009); in r8156b_hw_phy_cfg()
8000 data = sram_read(tp, 0x80d1); in r8156b_hw_phy_cfg()
8001 data &= ~0xff00; in r8156b_hw_phy_cfg()
8002 data |= 0x8000; in r8156b_hw_phy_cfg()
8003 sram_write(tp, 0x80d1, data); in r8156b_hw_phy_cfg()
8004 sram_write(tp, 0x80a3, 0x200a); in r8156b_hw_phy_cfg()
8005 sram_write(tp, 0x80a5, 0xf0ad); in r8156b_hw_phy_cfg()
8006 sram_write(tp, 0x809f, 0x6073); in r8156b_hw_phy_cfg()
8007 sram_write(tp, 0x80a1, 0x000b); in r8156b_hw_phy_cfg()
8008 data = sram_read(tp, 0x80a9); in r8156b_hw_phy_cfg()
8009 data &= ~0xff00; in r8156b_hw_phy_cfg()
8010 data |= 0xc000; in r8156b_hw_phy_cfg()
8011 sram_write(tp, 0x80a9, data); in r8156b_hw_phy_cfg()
8016 data = ocp_reg_read(tp, 0xb896); in r8156b_hw_phy_cfg()
8017 data &= ~BIT(0); in r8156b_hw_phy_cfg()
8018 ocp_reg_write(tp, 0xb896, data); in r8156b_hw_phy_cfg()
8019 data = ocp_reg_read(tp, 0xb892); in r8156b_hw_phy_cfg()
8020 data &= ~0xff00; in r8156b_hw_phy_cfg()
8021 ocp_reg_write(tp, 0xb892, data); in r8156b_hw_phy_cfg()
8022 ocp_reg_write(tp, 0xb88e, 0xc23e); in r8156b_hw_phy_cfg()
8023 ocp_reg_write(tp, 0xb890, 0x0000); in r8156b_hw_phy_cfg()
8024 ocp_reg_write(tp, 0xb88e, 0xc240); in r8156b_hw_phy_cfg()
8025 ocp_reg_write(tp, 0xb890, 0x0103); in r8156b_hw_phy_cfg()
8026 ocp_reg_write(tp, 0xb88e, 0xc242); in r8156b_hw_phy_cfg()
8027 ocp_reg_write(tp, 0xb890, 0x0507); in r8156b_hw_phy_cfg()
8028 ocp_reg_write(tp, 0xb88e, 0xc244); in r8156b_hw_phy_cfg()
8029 ocp_reg_write(tp, 0xb890, 0x090b); in r8156b_hw_phy_cfg()
8030 ocp_reg_write(tp, 0xb88e, 0xc246); in r8156b_hw_phy_cfg()
8031 ocp_reg_write(tp, 0xb890, 0x0c0e); in r8156b_hw_phy_cfg()
8032 ocp_reg_write(tp, 0xb88e, 0xc248); in r8156b_hw_phy_cfg()
8033 ocp_reg_write(tp, 0xb890, 0x1012); in r8156b_hw_phy_cfg()
8034 ocp_reg_write(tp, 0xb88e, 0xc24a); in r8156b_hw_phy_cfg()
8035 ocp_reg_write(tp, 0xb890, 0x1416); in r8156b_hw_phy_cfg()
8036 data = ocp_reg_read(tp, 0xb896); in r8156b_hw_phy_cfg()
8037 data |= BIT(0); in r8156b_hw_phy_cfg()
8038 ocp_reg_write(tp, 0xb896, data); in r8156b_hw_phy_cfg()
8042 data = ocp_reg_read(tp, 0xa86a); in r8156b_hw_phy_cfg()
8043 data |= BIT(0); in r8156b_hw_phy_cfg()
8044 ocp_reg_write(tp, 0xa86a, data); in r8156b_hw_phy_cfg()
8045 data = ocp_reg_read(tp, 0xa6f0); in r8156b_hw_phy_cfg()
8046 data |= BIT(0); in r8156b_hw_phy_cfg()
8047 ocp_reg_write(tp, 0xa6f0, data); in r8156b_hw_phy_cfg()
8049 ocp_reg_write(tp, 0xbfa0, 0xd70d); in r8156b_hw_phy_cfg()
8050 ocp_reg_write(tp, 0xbfa2, 0x4100); in r8156b_hw_phy_cfg()
8051 ocp_reg_write(tp, 0xbfa4, 0xe868); in r8156b_hw_phy_cfg()
8052 ocp_reg_write(tp, 0xbfa6, 0xdc59); in r8156b_hw_phy_cfg()
8053 ocp_reg_write(tp, 0xb54c, 0x3c18); in r8156b_hw_phy_cfg()
8054 data = ocp_reg_read(tp, 0xbfa4); in r8156b_hw_phy_cfg()
8056 ocp_reg_write(tp, 0xbfa4, data); in r8156b_hw_phy_cfg()
8057 data = sram_read(tp, 0x817d); in r8156b_hw_phy_cfg()
8059 sram_write(tp, 0x817d, data); in r8156b_hw_phy_cfg()
8063 data = ocp_reg_read(tp, 0xac46); in r8156b_hw_phy_cfg()
8064 data &= ~0x00f0; in r8156b_hw_phy_cfg()
8065 data |= 0x0090; in r8156b_hw_phy_cfg()
8066 ocp_reg_write(tp, 0xac46, data); in r8156b_hw_phy_cfg()
8067 data = ocp_reg_read(tp, 0xad30); in r8156b_hw_phy_cfg()
8068 data &= ~0x0003; in r8156b_hw_phy_cfg()
8069 data |= 0x0001; in r8156b_hw_phy_cfg()
8070 ocp_reg_write(tp, 0xad30, data); in r8156b_hw_phy_cfg()
8074 ocp_reg_write(tp, 0xb87c, 0x80f5); in r8156b_hw_phy_cfg()
8075 ocp_reg_write(tp, 0xb87e, 0x760e); in r8156b_hw_phy_cfg()
8076 ocp_reg_write(tp, 0xb87c, 0x8107); in r8156b_hw_phy_cfg()
8077 ocp_reg_write(tp, 0xb87e, 0x360e); in r8156b_hw_phy_cfg()
8078 ocp_reg_write(tp, 0xb87c, 0x8551); in r8156b_hw_phy_cfg()
8079 data = ocp_reg_read(tp, 0xb87e); in r8156b_hw_phy_cfg()
8080 data &= ~0xff00; in r8156b_hw_phy_cfg()
8081 data |= 0x0800; in r8156b_hw_phy_cfg()
8082 ocp_reg_write(tp, 0xb87e, data); in r8156b_hw_phy_cfg()
8085 data = ocp_reg_read(tp, 0xbf00); in r8156b_hw_phy_cfg()
8086 data &= ~0xe000; in r8156b_hw_phy_cfg()
8087 data |= 0xa000; in r8156b_hw_phy_cfg()
8088 ocp_reg_write(tp, 0xbf00, data); in r8156b_hw_phy_cfg()
8089 data = ocp_reg_read(tp, 0xbf46); in r8156b_hw_phy_cfg()
8090 data &= ~0x0f00; in r8156b_hw_phy_cfg()
8091 data |= 0x0300; in r8156b_hw_phy_cfg()
8092 ocp_reg_write(tp, 0xbf46, data); in r8156b_hw_phy_cfg()
8095 sram_write(tp, 0x8044, 0x2417); in r8156b_hw_phy_cfg()
8096 sram_write(tp, 0x804a, 0x2417); in r8156b_hw_phy_cfg()
8097 sram_write(tp, 0x8050, 0x2417); in r8156b_hw_phy_cfg()
8098 sram_write(tp, 0x8056, 0x2417); in r8156b_hw_phy_cfg()
8099 sram_write(tp, 0x805c, 0x2417); in r8156b_hw_phy_cfg()
8100 sram_write(tp, 0x8062, 0x2417); in r8156b_hw_phy_cfg()
8101 sram_write(tp, 0x8068, 0x2417); in r8156b_hw_phy_cfg()
8102 sram_write(tp, 0x806e, 0x2417); in r8156b_hw_phy_cfg()
8103 sram_write(tp, 0x8074, 0x2417); in r8156b_hw_phy_cfg()
8104 sram_write(tp, 0x807a, 0x2417); in r8156b_hw_phy_cfg()
8107 data = ocp_reg_read(tp, 0xbf84); in r8156b_hw_phy_cfg()
8108 data &= ~0xe000; in r8156b_hw_phy_cfg()
8109 data |= 0xa000; in r8156b_hw_phy_cfg()
8110 ocp_reg_write(tp, 0xbf84, data); in r8156b_hw_phy_cfg()
8145 data = ocp_reg_read(tp, 0xa428); in r8156b_hw_phy_cfg()
8147 ocp_reg_write(tp, 0xa428, data); in r8156b_hw_phy_cfg()
8148 data = ocp_reg_read(tp, 0xa5ea); in r8156b_hw_phy_cfg()
8149 data &= ~BIT(0); in r8156b_hw_phy_cfg()
8150 ocp_reg_write(tp, 0xa5ea, data); in r8156b_hw_phy_cfg()
8151 tp->ups_info.lite_mode = 0; in r8156b_hw_phy_cfg()
8176 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); in r8156_init()
8184 for (i = 0; i < 500; i++) { in r8156_init()
8194 data = r8153_phy_status(tp, 0); in r8156_init()
8196 data = ocp_reg_read(tp, 0xa468); in r8156_init()
8198 ocp_reg_write(tp, 0xa468, data); in r8156_init()
8212 /* MSC timer = 0xfff * 8ms = 32760 ms */ in r8156_init()
8213 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); in r8156_init()
8272 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); in r8156b_init()
8293 for (i = 0; i < 500; i++) { in r8156b_init()
8303 data = r8153_phy_status(tp, 0); in r8156b_init()
8305 data = ocp_reg_read(tp, 0xa468); in r8156b_init()
8307 ocp_reg_write(tp, 0xa468, data); in r8156b_init()
8309 data = ocp_reg_read(tp, 0xa466); in r8156b_init()
8310 data &= ~BIT(0); in r8156b_init()
8311 ocp_reg_write(tp, 0xa466, data); in r8156b_init()
8324 /* MSC timer = 0xfff * 8ms = 32760 ms */ in r8156b_init()
8325 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); in r8156b_init()
8394 if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) { in rtl_check_vendor_ok()
8428 return 0; in rtl8152_pre_reset()
8432 return 0; in rtl8152_pre_reset()
8448 return 0; in rtl8152_pre_reset()
8463 if (determine_ethernet_addr(tp, &sa) >= 0) in rtl8152_post_reset()
8489 return 0; in rtl8152_post_reset()
8551 return 0; in rtl8152_runtime_resume()
8580 return 0; in rtl8152_system_resume()
8586 int ret = 0; in rtl8152_runtime_suspend()
8595 u32 rcr = 0; in rtl8152_runtime_suspend()
8665 pm_wakeup_event(&tp->udev->dev, 0); in rtl8152_system_suspend()
8667 return 0; in rtl8152_system_suspend()
8713 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); in rtl8152_reset_resume()
8722 if (usb_autopm_get_interface(tp->intf) < 0) in rtl8152_get_wol()
8726 wol->supported = 0; in rtl8152_get_wol()
8727 wol->wolopts = 0; in rtl8152_get_wol()
8750 if (ret < 0) in rtl8152_set_wol()
8804 if (ret < 0) in rtl8152_get_link_ksettings()
8839 u32 advertising = 0; in rtl8152_set_link_ksettings()
8843 if (ret < 0) in rtl8152_set_link_ksettings()
8925 if (usb_autopm_get_interface(tp->intf) < 0) in rtl8152_get_ethtool_stats()
8932 data[0] = le64_to_cpu(tally.tx_packets); in rtl8152_get_ethtool_stats()
8975 return 0; in r8152_get_eee()
8987 return 0; in r8152_set_eee()
9009 return 0; in r8153_get_eee()
9024 if (ret < 0) in rtl_ethtool_get_eee()
9051 if (ret < 0) in rtl_ethtool_set_eee()
9074 if (ret < 0) in rtl8152_nway_reset()
9107 return 0; in rtl8152_get_coalesce()
9131 if (ret < 0) in rtl8152_set_coalesce()
9172 return 0; in rtl8152_get_tunable()
9207 return 0; in rtl8152_set_tunable()
9243 return 0; in rtl8152_set_ringparam()
9252 if (usb_autopm_get_interface(tp->intf) < 0) in rtl8152_get_pauseparam()
9266 pause->autoneg = 0; in rtl8152_get_pauseparam()
9267 pause->rx_pause = 0; in rtl8152_get_pauseparam()
9268 pause->tx_pause = 0; in rtl8152_get_pauseparam()
9287 u8 cap = 0; in rtl8152_set_pauseparam()
9291 if (ret < 0) in rtl8152_set_pauseparam()
9355 if (res < 0) in rtl8152_ioctl()
9399 return 0; in rtl8152_change_mtu()
9405 if (ret < 0) in rtl8152_change_mtu()
9479 int ret = 0; in rtl_ops_init()
9671 return 0; in rtl_fw_init()
9676 u32 ocp_data = 0; in __rtl_get_hw_ver()
9684 return 0; in __rtl_get_hw_ver()
9690 for (i = 0; i < 3; i++) { in __rtl_get_hw_ver()
9691 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), in __rtl_get_hw_ver()
9695 if (ret > 0) { in __rtl_get_hw_ver()
9701 if (i != 0 && ret > 0) in __rtl_get_hw_ver()
9707 case 0x4c00: in __rtl_get_hw_ver()
9710 case 0x4c10: in __rtl_get_hw_ver()
9713 case 0x5c00: in __rtl_get_hw_ver()
9716 case 0x5c10: in __rtl_get_hw_ver()
9719 case 0x5c20: in __rtl_get_hw_ver()
9722 case 0x5c30: in __rtl_get_hw_ver()
9725 case 0x4800: in __rtl_get_hw_ver()
9728 case 0x6000: in __rtl_get_hw_ver()
9731 case 0x6010: in __rtl_get_hw_ver()
9734 case 0x7010: in __rtl_get_hw_ver()
9737 case 0x7020: in __rtl_get_hw_ver()
9740 case 0x7030: in __rtl_get_hw_ver()
9743 case 0x7400: in __rtl_get_hw_ver()
9746 case 0x7410: in __rtl_get_hw_ver()
9749 case 0x6400: in __rtl_get_hw_ver()
9752 case 0x7420: in __rtl_get_hw_ver()
9757 dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data); in __rtl_get_hw_ver()
9770 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); in rtl8152_get_version()
9794 case 0x8153: in rtl8152_supports_lenovo_macpassthru()
9798 return 0; in rtl8152_supports_lenovo_macpassthru()
9818 tp->msg_enable = 0x7FFF; in rtl8152_probe_once()
9825 tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0); in rtl8152_probe_once()
9826 tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0); in rtl8152_probe_once()
9835 tp->mii.supports_gmii = 0; in rtl8152_probe_once()
9876 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && in rtl8152_probe_once()
9918 tp->mii.phy_id_mask = 0x3f; in rtl8152_probe_once()
9919 tp->mii.reg_num_mask = 0x1f; in rtl8152_probe_once()
9944 __rtl_set_wol(tp, 0); in rtl8152_probe_once()
9953 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); in rtl8152_probe_once()
9961 if (ret != 0) { in rtl8152_probe_once()
9980 return 0; in rtl8152_probe_once()
10019 for (i = 0; i < RTL8152_PROBE_TRIES; i++) { in rtl8152_probe()
10054 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) },
10055 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) },
10056 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) },
10057 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) },
10058 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) },
10059 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) },
10062 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },
10063 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) },
10064 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) },
10065 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) },
10066 { USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) },
10067 { USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) },
10068 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) },
10069 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) },
10070 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) },
10071 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) },
10072 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3098) },
10073 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) },
10074 { USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) },
10075 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) },
10076 { USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) },
10077 { USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) },
10078 { USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },
10079 { USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) },
10080 { USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) },
10081 { USB_DEVICE(VENDOR_ID_DLINK, 0xb301) },
10082 { USB_DEVICE(VENDOR_ID_ASUS, 0x1976) },
10116 for (i = 0; i < num_configs; (i++, c++)) { in rtl8152_cfgselector_choose_configuration()
10121 desc = &c->intf_cache[0]->altsetting->desc; in rtl8152_cfgselector_choose_configuration()