123 	err = phy_write(phydev, MII_VSC8244_EXT_CON1, extcon);  in vsc824x_add_skew()
132 	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,  in vsc824x_config_init()
226 	phy_write(phydev, 0x1f, 0x2a30);  in vsc73xx_config_init()
228 	phy_write(phydev, 0x1f, 0x0000);  in vsc73xx_config_init()
248 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
250 	phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
251 	phy_write(phydev, 0x10, 0xb68a);  in vsc738x_config_init()
254 	phy_write(phydev, 0x10, 0x968a);  in vsc738x_config_init()
255 	phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
257 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
265 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
267 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
268 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
269 		phy_write(phydev, 0x11, 0x0689);  in vsc738x_config_init()
270 		phy_write(phydev, 0x10, 0x8f92);  in vsc738x_config_init()
271 		phy_write(phydev, 0x1f, 0x52b5);  in vsc738x_config_init()
272 		phy_write(phydev, 0x12, 0x0000);  in vsc738x_config_init()
273 		phy_write(phydev, 0x11, 0x0e35);  in vsc738x_config_init()
274 		phy_write(phydev, 0x10, 0x9786);  in vsc738x_config_init()
275 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
277 		phy_write(phydev, 0x17, 0xff80);  in vsc738x_config_init()
278 		phy_write(phydev, 0x17, 0x0000);  in vsc738x_config_init()
281 	phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
282 	phy_write(phydev, 0x12, 0x0048);  in vsc738x_config_init()
285 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
286 		phy_write(phydev, 0x14, 0x6600);  in vsc738x_config_init()
287 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
288 		phy_write(phydev, 0x18, 0xa24e);  in vsc738x_config_init()
290 		phy_write(phydev, 0x1f, 0x2a30);  in vsc738x_config_init()
296 		phy_write(phydev, 0x1f, 0x0001);  in vsc738x_config_init()
298 		phy_write(phydev, 0x1f, 0x0000);  in vsc738x_config_init()
313 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
315 	phy_write(phydev, 0x1f, 0x52b5);  in vsc739x_config_init()
316 	phy_write(phydev, 0x10, 0xb68a);  in vsc739x_config_init()
319 	phy_write(phydev, 0x10, 0x968a);  in vsc739x_config_init()
320 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
322 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
324 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
325 	phy_write(phydev, 0x12, 0x0048);  in vsc739x_config_init()
326 	phy_write(phydev, 0x1f, 0x2a30);  in vsc739x_config_init()
329 	phy_write(phydev, 0x1f, 0x0001);  in vsc739x_config_init()
331 	phy_write(phydev, 0x1f, 0x0000);  in vsc739x_config_init()
365 	ret = phy_write(phydev, MII_VSC73XX_PHY_BYPASS_CTRL, val);  in vsc73xx_mdix_set()
420 	return phy_write(phydev, MII_VSC8601_EPHY_CTL, ret);  in vsc8601_add_skew()
444 		err = phy_write(phydev, MII_VSC8244_IMASK,  in vsc82xx_config_intr()
460 		err = phy_write(phydev, MII_VSC8244_IMASK, 0);  in vsc82xx_config_intr()
495 	err = phy_write(phydev, MII_VSC8244_AUX_CONSTAT,  in vsc8221_config_init()
518 	ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5);  in vsc82x4_config_autocross_enable()
520 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012);  in vsc82x4_config_autocross_enable()
522 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803);  in vsc82x4_config_autocross_enable()
524 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa);  in vsc82x4_config_autocross_enable()
527 		ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()
529 		phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000);  in vsc82x4_config_autocross_enable()