Lines Matching +full:0 +full:x0200
16 #define MII_VSC73XX_EXT_PAGE_1E 0x01
17 #define MII_VSC82X4_EXT_PAGE_16E 0x10
18 #define MII_VSC82X4_EXT_PAGE_17E 0x11
19 #define MII_VSC82X4_EXT_PAGE_18E 0x12
22 #define MII_VSC8244_EXT_CON1 0x17
23 #define MII_VSC8244_EXTCON1_INIT 0x0000
24 #define MII_VSC8244_EXTCON1_TX_SKEW_MASK 0x0c00
25 #define MII_VSC8244_EXTCON1_RX_SKEW_MASK 0x0300
26 #define MII_VSC8244_EXTCON1_TX_SKEW 0x0800
27 #define MII_VSC8244_EXTCON1_RX_SKEW 0x0200
30 #define MII_VSC8244_IMASK 0x19
31 #define MII_VSC8244_IMASK_IEN 0x8000
32 #define MII_VSC8244_IMASK_SPEED 0x4000
33 #define MII_VSC8244_IMASK_LINK 0x2000
34 #define MII_VSC8244_IMASK_DUPLEX 0x1000
35 #define MII_VSC8244_IMASK_MASK 0xf000
37 #define MII_VSC8221_IMASK_MASK 0xa000
40 #define MII_VSC8244_ISTAT 0x1a
41 #define MII_VSC8244_ISTAT_STATUS 0x8000
42 #define MII_VSC8244_ISTAT_SPEED 0x4000
43 #define MII_VSC8244_ISTAT_LINK 0x2000
44 #define MII_VSC8244_ISTAT_DUPLEX 0x1000
52 #define MII_VSC8244_AUX_CONSTAT 0x1c
53 #define MII_VSC8244_AUXCONSTAT_INIT 0x0000
54 #define MII_VSC8244_AUXCONSTAT_DUPLEX 0x0020
55 #define MII_VSC8244_AUXCONSTAT_SPEED 0x0018
56 #define MII_VSC8244_AUXCONSTAT_GBIT 0x0010
57 #define MII_VSC8244_AUXCONSTAT_100 0x0008
59 #define MII_VSC8221_AUXCONSTAT_INIT 0x0004 /* need to set this bit? */
60 #define MII_VSC8221_AUXCONSTAT_RESERVED 0x0004
63 #define MII_VSC82X4_EXT_PAGE_ACCESS 0x1f
66 #define MII_VSC73XX_PHY_CTRL_EXT3 0x14
88 #define MII_VSC8601_EPHY_CTL 0x17
91 #define PHY_ID_VSC8234 0x000fc620
92 #define PHY_ID_VSC8244 0x000fc6c0
93 #define PHY_ID_VSC8572 0x000704d0
94 #define PHY_ID_VSC8601 0x00070420
95 #define PHY_ID_VSC7385 0x00070450
96 #define PHY_ID_VSC7388 0x00070480
97 #define PHY_ID_VSC7395 0x00070550
98 #define PHY_ID_VSC7398 0x00070580
99 #define PHY_ID_VSC8662 0x00070660
100 #define PHY_ID_VSC8221 0x000fc550
101 #define PHY_ID_VSC8211 0x000fc4b0
114 if (extcon < 0) in vsc824x_add_skew()
134 if (err < 0) in vsc824x_config_init()
143 #define VSC73XX_EXT_PAGE_ACCESS 0x1f
161 if (val < 0) in vsc73xx_get_downshift()
169 return 0; in vsc73xx_get_downshift()
185 val = 0; in vsc73xx_set_downshift()
195 if (ret < 0) in vsc73xx_set_downshift()
226 phy_write(phydev, 0x1f, 0x2a30); in vsc73xx_config_init()
227 phy_modify(phydev, 0x0c, 0x0300, 0x0200); in vsc73xx_config_init()
228 phy_write(phydev, 0x1f, 0x0000); in vsc73xx_config_init()
230 /* Config LEDs 0x61 */ in vsc73xx_config_init()
231 phy_modify(phydev, MII_TPISTATUS, 0xff00, 0x0061); in vsc73xx_config_init()
248 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
249 phy_modify(phydev, 0x08, 0x0200, 0x0200); in vsc738x_config_init()
250 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
251 phy_write(phydev, 0x10, 0xb68a); in vsc738x_config_init()
252 phy_modify(phydev, 0x12, 0xff07, 0x0003); in vsc738x_config_init()
253 phy_modify(phydev, 0x11, 0x00ff, 0x00a2); in vsc738x_config_init()
254 phy_write(phydev, 0x10, 0x968a); in vsc738x_config_init()
255 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
256 phy_modify(phydev, 0x08, 0x0200, 0x0000); in vsc738x_config_init()
257 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
261 rev &= 0x0f; in vsc738x_config_init()
263 /* Special quirk for revision 0 */ in vsc738x_config_init()
264 if (rev == 0) { in vsc738x_config_init()
265 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
266 phy_modify(phydev, 0x08, 0x0200, 0x0200); in vsc738x_config_init()
267 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
268 phy_write(phydev, 0x12, 0x0000); in vsc738x_config_init()
269 phy_write(phydev, 0x11, 0x0689); in vsc738x_config_init()
270 phy_write(phydev, 0x10, 0x8f92); in vsc738x_config_init()
271 phy_write(phydev, 0x1f, 0x52b5); in vsc738x_config_init()
272 phy_write(phydev, 0x12, 0x0000); in vsc738x_config_init()
273 phy_write(phydev, 0x11, 0x0e35); in vsc738x_config_init()
274 phy_write(phydev, 0x10, 0x9786); in vsc738x_config_init()
275 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
276 phy_modify(phydev, 0x08, 0x0200, 0x0000); in vsc738x_config_init()
277 phy_write(phydev, 0x17, 0xff80); in vsc738x_config_init()
278 phy_write(phydev, 0x17, 0x0000); in vsc738x_config_init()
281 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
282 phy_write(phydev, 0x12, 0x0048); in vsc738x_config_init()
284 if (rev == 0) { in vsc738x_config_init()
285 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
286 phy_write(phydev, 0x14, 0x6600); in vsc738x_config_init()
287 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
288 phy_write(phydev, 0x18, 0xa24e); in vsc738x_config_init()
290 phy_write(phydev, 0x1f, 0x2a30); in vsc738x_config_init()
291 phy_modify(phydev, 0x16, 0x0fc0, 0x0240); in vsc738x_config_init()
292 phy_modify(phydev, 0x14, 0x6000, 0x4000); in vsc738x_config_init()
293 /* bits 14-15 in extended register 0x14 controls DACG amplitude in vsc738x_config_init()
296 phy_write(phydev, 0x1f, 0x0001); in vsc738x_config_init()
297 phy_modify(phydev, 0x14, 0xe000, 0x6000); in vsc738x_config_init()
298 phy_write(phydev, 0x1f, 0x0000); in vsc738x_config_init()
303 return 0; in vsc738x_config_init()
313 phy_write(phydev, 0x1f, 0x2a30); in vsc739x_config_init()
314 phy_modify(phydev, 0x08, 0x0200, 0x0200); in vsc739x_config_init()
315 phy_write(phydev, 0x1f, 0x52b5); in vsc739x_config_init()
316 phy_write(phydev, 0x10, 0xb68a); in vsc739x_config_init()
317 phy_modify(phydev, 0x12, 0xff07, 0x0003); in vsc739x_config_init()
318 phy_modify(phydev, 0x11, 0x00ff, 0x00a2); in vsc739x_config_init()
319 phy_write(phydev, 0x10, 0x968a); in vsc739x_config_init()
320 phy_write(phydev, 0x1f, 0x2a30); in vsc739x_config_init()
321 phy_modify(phydev, 0x08, 0x0200, 0x0000); in vsc739x_config_init()
322 phy_write(phydev, 0x1f, 0x0000); in vsc739x_config_init()
324 phy_write(phydev, 0x1f, 0x0000); in vsc739x_config_init()
325 phy_write(phydev, 0x12, 0x0048); in vsc739x_config_init()
326 phy_write(phydev, 0x1f, 0x2a30); in vsc739x_config_init()
327 phy_modify(phydev, 0x16, 0x0fc0, 0x0240); in vsc739x_config_init()
328 phy_modify(phydev, 0x14, 0x6000, 0x4000); in vsc739x_config_init()
329 phy_write(phydev, 0x1f, 0x0001); in vsc739x_config_init()
330 phy_modify(phydev, 0x14, 0xe000, 0x6000); in vsc739x_config_init()
331 phy_write(phydev, 0x1f, 0x0000); in vsc739x_config_init()
335 return 0; in vsc739x_config_init()
393 return 0; in vsc73xx_mdix_get()
401 if (ret < 0) in vsc73xx_read_status()
416 if (ret < 0) in vsc8601_add_skew()
425 int ret = 0; in vsc8601_config_init()
430 if (ret < 0) in vsc8601_config_init()
433 return 0; in vsc8601_config_init()
457 if (err < 0) in vsc82xx_config_intr()
460 err = phy_write(phydev, MII_VSC8244_IMASK, 0); in vsc82xx_config_intr()
478 if (irq_status < 0) { in vsc82xx_handle_interrupt()
515 return 0; in vsc82x4_config_autocross_enable()
517 /* map extended registers set 0x10 - 0x1e */ in vsc82x4_config_autocross_enable()
518 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x52b5); in vsc82x4_config_autocross_enable()
519 if (ret >= 0) in vsc82x4_config_autocross_enable()
520 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_18E, 0x0012); in vsc82x4_config_autocross_enable()
521 if (ret >= 0) in vsc82x4_config_autocross_enable()
522 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_17E, 0x2803); in vsc82x4_config_autocross_enable()
523 if (ret >= 0) in vsc82x4_config_autocross_enable()
524 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_16E, 0x87fa); in vsc82x4_config_autocross_enable()
525 /* map standard registers set 0x10 - 0x1e */ in vsc82x4_config_autocross_enable()
526 if (ret >= 0) in vsc82x4_config_autocross_enable()
527 ret = phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000); in vsc82x4_config_autocross_enable()
529 phy_write(phydev, MII_VSC82X4_EXT_PAGE_ACCESS, 0x0000); in vsc82x4_config_autocross_enable()
552 if (ret < 0) /* error */ in vsc82x4_config_aneg()
566 .phy_id_mask = 0x000ffff0,
575 .phy_id_mask = 0x000fffc0,
584 .phy_id_mask = 0x000ffff0,
593 .phy_id_mask = 0x000ffff0,
601 .phy_id_mask = 0x000ffff0,
613 .phy_id_mask = 0x000ffff0,
625 .phy_id_mask = 0x000ffff0,
637 .phy_id_mask = 0x000ffff0,
649 .phy_id_mask = 0x000ffff0,
658 .phy_id_mask = 0x000ffff0,
667 .phy_id_mask = 0x000ffff0,
678 { PHY_ID_VSC8234, 0x000ffff0 },
679 { PHY_ID_VSC8244, 0x000fffc0 },
680 { PHY_ID_VSC8572, 0x000ffff0 },
681 { PHY_ID_VSC7385, 0x000ffff0 },
682 { PHY_ID_VSC7388, 0x000ffff0 },
683 { PHY_ID_VSC7395, 0x000ffff0 },
684 { PHY_ID_VSC7398, 0x000ffff0 },
685 { PHY_ID_VSC8662, 0x000ffff0 },
686 { PHY_ID_VSC8221, 0x000ffff0 },
687 { PHY_ID_VSC8211, 0x000ffff0 },