9 #define QCA808X_PHY_DEBUG_ADC_THRESHOLD		0x2c80
10 #define QCA808X_ADC_THRESHOLD_MASK		GENMASK(7, 0)
11 #define QCA808X_ADC_THRESHOLD_80MV		0
12 #define QCA808X_ADC_THRESHOLD_100MV		0xf0
13 #define QCA808X_ADC_THRESHOLD_200MV		0x0f
14 #define QCA808X_ADC_THRESHOLD_300MV		0xff
17 #define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7		0x8007
19 #define QCA808X_8023AZ_AFE_EN			0x90
22 #define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL	0x8008
23 #define QCA808X_MMD3_AZ_TRAINING_VAL		0x1c32
25 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB	0x8014
26 #define QCA808X_MSE_THRESHOLD_20DB_VALUE	0x529
28 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB	0x800E
29 #define QCA808X_MSE_THRESHOLD_17DB_VALUE	0x341
31 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB	0x801E
32 #define QCA808X_MSE_THRESHOLD_27DB_VALUE	0x419
34 #define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB	0x8020
35 #define QCA808X_MSE_THRESHOLD_28DB_VALUE	0x341
37 #define QCA808X_PHY_MMD7_TOP_OPTION1		0x901c
38 #define QCA808X_TOP_OPTION1_DATA		0x0
40 #define QCA808X_PHY_MMD3_DEBUG_1		0xa100
41 #define QCA808X_MMD3_DEBUG_1_VALUE		0x9203
42 #define QCA808X_PHY_MMD3_DEBUG_2		0xa101
43 #define QCA808X_MMD3_DEBUG_2_VALUE		0x48ad
44 #define QCA808X_PHY_MMD3_DEBUG_3		0xa103
45 #define QCA808X_MMD3_DEBUG_3_VALUE		0x1698
46 #define QCA808X_PHY_MMD3_DEBUG_4		0xa105
47 #define QCA808X_MMD3_DEBUG_4_VALUE		0x8001
48 #define QCA808X_PHY_MMD3_DEBUG_5		0xa106
49 #define QCA808X_MMD3_DEBUG_5_VALUE		0x1111
50 #define QCA808X_PHY_MMD3_DEBUG_6		0xa011
51 #define QCA808X_MMD3_DEBUG_6_VALUE		0x5f85
57 #define QCA808X_MASTER_SLAVE_SEED_RANGE		0x32
62 #define QCA808X_DBG_AN_TEST			0xb
65 #define QCA808X_MMD7_LED2_CTRL			0x8074
66 #define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
67 #define QCA808X_MMD7_LED1_CTRL			0x8076
68 #define QCA808X_MMD7_LED1_FORCE_CTRL		0x8077
69 #define QCA808X_MMD7_LED0_CTRL			0x8078
70 #define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
72 #define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
73 #define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
75 #define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
76 /* QSDK sets by default 0x46 to this reg that sets BIT 6 for
82 #define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
83 #define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
85 #define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
88 #define QCA8081_PHY_ID				0x004dd101
130 	return 0;  in qca808x_phy_fast_retrain_config()
139 				QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);  in qca808x_phy_ms_seed_enable()
164 	if (ret < 0)  in qca808x_is_1g_only()
194 	return 0;  in qca808x_probe()
231 		if (ret < 0)  in qca808x_config_init()
254 	struct at803x_ss_mask ss_mask = { 0 };  in qca808x_read_status()
258 	if (ret < 0)  in qca808x_read_status()
272 	if (ret < 0)  in qca808x_read_status()
300 	return 0;  in qca808x_read_status()
308 	if (ret < 0)  in qca808x_soft_reset()
328 	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);  in qca808x_cable_test_start()
329 	if (ret < 0)  in qca808x_cable_test_start()
333 	if (ret < 0)  in qca808x_cable_test_start()
340 	if (ret < 0)  in qca808x_cable_test_start()
344 	if (ret < 0)  in qca808x_cable_test_start()
348 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);  in qca808x_cable_test_start()
349 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);  in qca808x_cable_test_start()
350 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);  in qca808x_cable_test_start()
351 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);  in qca808x_cable_test_start()
352 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);  in qca808x_cable_test_start()
353 	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);  in qca808x_cable_test_start()
355 	return 0;  in qca808x_cable_test_start()
374 	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.  in qca808x_get_features()
379 	return 0;  in qca808x_get_features()
384 	int phy_ctrl = 0;  in qca808x_config_aneg()
402 	if (ret < 0)  in qca808x_config_aneg()
416 				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);  in qca808x_link_change_notify()
448 	return 0;  in qca808x_led_parse_netdev()
465 	u16 offload_trigger = 0;  in qca808x_led_hw_is_supported()
476 	u16 reg, offload_trigger = 0;  in qca808x_led_hw_control_set()
541 	return 0;  in qca808x_led_hw_control_get()
610 	if (priv->led_polarity_mode >= 0 &&  in qca808x_led_polarity_set()
622 			      active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);  in qca808x_led_polarity_set()