Lines Matching full:phydev
15 * @phydev: target phy_device struct
17 static bool genphy_c45_baset1_able(struct phy_device *phydev) in genphy_c45_baset1_able() argument
21 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
22 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_baset1_able()
26 phydev->pma_extable = val; in genphy_c45_baset1_able()
29 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
34 * @phydev: target phy_device struct
36 static bool genphy_c45_pma_can_sleep(struct phy_device *phydev) in genphy_c45_pma_can_sleep() argument
40 stat1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT1); in genphy_c45_pma_can_sleep()
49 * @phydev: target phy_device struct
51 int genphy_c45_pma_resume(struct phy_device *phydev) in genphy_c45_pma_resume() argument
53 if (!genphy_c45_pma_can_sleep(phydev)) in genphy_c45_pma_resume()
56 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_resume()
63 * @phydev: target phy_device struct
65 int genphy_c45_pma_suspend(struct phy_device *phydev) in genphy_c45_pma_suspend() argument
67 if (!genphy_c45_pma_can_sleep(phydev)) in genphy_c45_pma_suspend()
70 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, in genphy_c45_pma_suspend()
78 * @phydev: target phy_device struct
80 int genphy_c45_pma_baset1_setup_master_slave(struct phy_device *phydev) in genphy_c45_pma_baset1_setup_master_slave() argument
84 switch (phydev->master_slave_set) { in genphy_c45_pma_baset1_setup_master_slave()
96 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); in genphy_c45_pma_baset1_setup_master_slave()
100 return phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, in genphy_c45_pma_baset1_setup_master_slave()
107 * @phydev: target phy_device struct
109 int genphy_c45_pma_setup_forced(struct phy_device *phydev) in genphy_c45_pma_setup_forced() argument
114 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
117 ctrl1 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_pma_setup_forced()
121 ctrl2 = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2); in genphy_c45_pma_setup_forced()
132 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
134 if (genphy_c45_baset1_able(phydev)) in genphy_c45_pma_setup_forced()
167 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1, ctrl1); in genphy_c45_pma_setup_forced()
171 ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL2, ctrl2); in genphy_c45_pma_setup_forced()
175 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_pma_setup_forced()
176 ret = genphy_c45_pma_baset1_setup_master_slave(phydev); in genphy_c45_pma_setup_forced()
181 if (phydev->speed == SPEED_1000) in genphy_c45_pma_setup_forced()
184 ret = phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL, in genphy_c45_pma_setup_forced()
190 return genphy_c45_an_disable_aneg(phydev); in genphy_c45_pma_setup_forced()
202 static int genphy_c45_baset1_an_config_aneg(struct phy_device *phydev) in genphy_c45_baset1_an_config_aneg() argument
214 switch (phydev->master_slave_set) { in genphy_c45_baset1_an_config_aneg()
233 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); in genphy_c45_baset1_an_config_aneg()
237 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
239 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L, in genphy_c45_baset1_an_config_aneg()
246 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
248 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M, in genphy_c45_baset1_an_config_aneg()
260 * @phydev: target phy_device struct
262 * Configure advertisement registers based on modes set in phydev->advertising
267 int genphy_c45_an_config_aneg(struct phy_device *phydev) in genphy_c45_an_config_aneg() argument
272 linkmode_and(phydev->advertising, phydev->advertising, in genphy_c45_an_config_aneg()
273 phydev->supported); in genphy_c45_an_config_aneg()
275 ret = genphy_c45_an_config_eee_aneg(phydev); in genphy_c45_an_config_aneg()
281 if (genphy_c45_baset1_able(phydev)) in genphy_c45_an_config_aneg()
282 return genphy_c45_baset1_an_config_aneg(phydev); in genphy_c45_an_config_aneg()
284 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
286 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE, in genphy_c45_an_config_aneg()
295 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
297 ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_an_config_aneg()
312 * @phydev: target phy_device struct
319 int genphy_c45_an_disable_aneg(struct phy_device *phydev) in genphy_c45_an_disable_aneg() argument
323 if (genphy_c45_baset1_able(phydev)) in genphy_c45_an_disable_aneg()
326 return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_an_disable_aneg()
333 * @phydev: target phy_device struct
339 int genphy_c45_restart_aneg(struct phy_device *phydev) in genphy_c45_restart_aneg() argument
343 if (genphy_c45_baset1_able(phydev)) in genphy_c45_restart_aneg()
346 return phy_set_bits_mmd(phydev, MDIO_MMD_AN, reg, in genphy_c45_restart_aneg()
353 * @phydev: target phy_device struct
360 int genphy_c45_check_and_restart_aneg(struct phy_device *phydev, bool restart) in genphy_c45_check_and_restart_aneg() argument
365 if (genphy_c45_baset1_able(phydev)) in genphy_c45_check_and_restart_aneg()
370 ret = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_check_and_restart_aneg()
379 return genphy_c45_restart_aneg(phydev); in genphy_c45_check_and_restart_aneg()
387 * @phydev: target phy_device struct
396 int genphy_c45_aneg_done(struct phy_device *phydev) in genphy_c45_aneg_done() argument
401 if (genphy_c45_baset1_able(phydev)) in genphy_c45_aneg_done()
404 val = phy_read_mmd(phydev, MDIO_MMD_AN, reg); in genphy_c45_aneg_done()
412 * @phydev: target phy_device struct
415 * that the link is up, set phydev->link to 1. If an error is encountered,
418 int genphy_c45_read_link(struct phy_device *phydev) in genphy_c45_read_link() argument
424 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_read_link()
425 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1); in genphy_c45_read_link()
433 phydev->link = 0; in genphy_c45_read_link()
447 if (!phy_polling_mode(phydev) || !phydev->link) { in genphy_c45_read_link()
448 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
455 val = phy_read_mmd(phydev, devad, MDIO_STAT1); in genphy_c45_read_link()
463 phydev->link = link; in genphy_c45_read_link()
472 * pause and asym_pause members in phydev.
474 static int genphy_c45_baset1_read_lpa(struct phy_device *phydev) in genphy_c45_baset1_read_lpa() argument
478 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); in genphy_c45_baset1_read_lpa()
483 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); in genphy_c45_baset1_read_lpa()
484 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
485 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
487 phydev->pause = 0; in genphy_c45_baset1_read_lpa()
488 phydev->asym_pause = 0; in genphy_c45_baset1_read_lpa()
493 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); in genphy_c45_baset1_read_lpa()
495 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_L); in genphy_c45_baset1_read_lpa()
499 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
500 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; in genphy_c45_baset1_read_lpa()
501 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; in genphy_c45_baset1_read_lpa()
503 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_LP_M); in genphy_c45_baset1_read_lpa()
507 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
514 * @phydev: target phy_device struct
518 * in @phydev. This assumes that the auto-negotiation MMD is present, and
522 int genphy_c45_read_lpa(struct phy_device *phydev) in genphy_c45_read_lpa() argument
526 if (genphy_c45_baset1_able(phydev)) in genphy_c45_read_lpa()
527 return genphy_c45_baset1_read_lpa(phydev); in genphy_c45_read_lpa()
529 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_read_lpa()
535 phydev->lp_advertising); in genphy_c45_read_lpa()
536 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
537 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
538 phydev->pause = 0; in genphy_c45_read_lpa()
539 phydev->asym_pause = 0; in genphy_c45_read_lpa()
544 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, in genphy_c45_read_lpa()
548 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_LPA); in genphy_c45_read_lpa()
552 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
553 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; in genphy_c45_read_lpa()
554 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; in genphy_c45_read_lpa()
557 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT); in genphy_c45_read_lpa()
561 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
570 * @phydev: target phy_device struct
572 int genphy_c45_pma_baset1_read_master_slave(struct phy_device *phydev) in genphy_c45_pma_baset1_read_master_slave() argument
576 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
577 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
579 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1_CTRL); in genphy_c45_pma_baset1_read_master_slave()
584 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_pma_baset1_read_master_slave()
585 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in genphy_c45_pma_baset1_read_master_slave()
587 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_pma_baset1_read_master_slave()
588 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in genphy_c45_pma_baset1_read_master_slave()
597 * @phydev: target phy_device struct
599 int genphy_c45_read_pma(struct phy_device *phydev) in genphy_c45_read_pma() argument
603 linkmode_zero(phydev->lp_advertising); in genphy_c45_read_pma()
605 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_CTRL1); in genphy_c45_read_pma()
611 phydev->speed = SPEED_10; in genphy_c45_read_pma()
614 phydev->speed = SPEED_100; in genphy_c45_read_pma()
617 phydev->speed = SPEED_1000; in genphy_c45_read_pma()
620 phydev->speed = SPEED_2500; in genphy_c45_read_pma()
623 phydev->speed = SPEED_5000; in genphy_c45_read_pma()
626 phydev->speed = SPEED_10000; in genphy_c45_read_pma()
629 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_pma()
633 phydev->duplex = DUPLEX_FULL; in genphy_c45_read_pma()
635 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_read_pma()
636 val = genphy_c45_pma_baset1_read_master_slave(phydev); in genphy_c45_read_pma()
647 * @phydev: target phy_device struct
649 int genphy_c45_read_mdix(struct phy_device *phydev) in genphy_c45_read_mdix() argument
653 if (phydev->speed == SPEED_10000) { in genphy_c45_read_mdix()
654 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_read_mdix()
661 phydev->mdix = ETH_TP_MDI; in genphy_c45_read_mdix()
665 phydev->mdix = ETH_TP_MDI_X; in genphy_c45_read_mdix()
669 phydev->mdix = ETH_TP_MDI_INVALID; in genphy_c45_read_mdix()
680 * @phydev: target phy_device struct
683 int genphy_c45_write_eee_adv(struct phy_device *phydev, unsigned long *adv) in genphy_c45_write_eee_adv() argument
687 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_write_eee_adv()
693 val &= ~phydev->eee_broken_modes; in genphy_c45_write_eee_adv()
698 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
710 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_write_eee_adv()
716 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
727 phydev->supported_eee)) { in genphy_c45_write_eee_adv()
732 val = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, in genphy_c45_write_eee_adv()
747 * @phydev: target phy_device struct
750 int genphy_c45_read_eee_adv(struct phy_device *phydev, unsigned long *adv) in genphy_c45_read_eee_adv() argument
754 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_adv()
758 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV); in genphy_c45_read_eee_adv()
765 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_adv()
769 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV2); in genphy_c45_read_eee_adv()
777 phydev->supported_eee)) { in genphy_c45_read_eee_adv()
781 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_CTRL); in genphy_c45_read_eee_adv()
793 * @phydev: target phy_device struct
796 static int genphy_c45_read_eee_lpa(struct phy_device *phydev, in genphy_c45_read_eee_lpa() argument
801 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_lpa()
805 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); in genphy_c45_read_eee_lpa()
812 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_lpa()
816 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE2); in genphy_c45_read_eee_lpa()
824 phydev->supported_eee)) { in genphy_c45_read_eee_lpa()
828 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10BT1_AN_STAT); in genphy_c45_read_eee_lpa()
840 * @phydev: target phy_device struct
842 static int genphy_c45_read_eee_cap1(struct phy_device *phydev) in genphy_c45_read_eee_cap1() argument
849 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); in genphy_c45_read_eee_cap1()
861 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); in genphy_c45_read_eee_cap1()
866 linkmode_and(phydev->supported_eee, phydev->supported_eee, in genphy_c45_read_eee_cap1()
867 phydev->supported); in genphy_c45_read_eee_cap1()
874 * @phydev: target phy_device struct
876 static int genphy_c45_read_eee_cap2(struct phy_device *phydev) in genphy_c45_read_eee_cap2() argument
883 val = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE2); in genphy_c45_read_eee_cap2()
891 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); in genphy_c45_read_eee_cap2()
898 * @phydev: target phy_device struct
900 int genphy_c45_read_eee_abilities(struct phy_device *phydev) in genphy_c45_read_eee_abilities() argument
908 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_abilities()
909 val = genphy_c45_read_eee_cap1(phydev); in genphy_c45_read_eee_abilities()
915 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_abilities()
916 val = genphy_c45_read_eee_cap2(phydev); in genphy_c45_read_eee_abilities()
922 phydev->supported)) { in genphy_c45_read_eee_abilities()
926 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10T1L_STAT); in genphy_c45_read_eee_abilities()
931 phydev->supported_eee, in genphy_c45_read_eee_abilities()
941 * @phydev: target phy_device struct
943 int genphy_c45_an_config_eee_aneg(struct phy_device *phydev) in genphy_c45_an_config_eee_aneg() argument
945 if (!phydev->eee_enabled) { in genphy_c45_an_config_eee_aneg()
948 return genphy_c45_write_eee_adv(phydev, adv); in genphy_c45_an_config_eee_aneg()
951 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); in genphy_c45_an_config_eee_aneg()
956 * @phydev: target phy_device struct
960 int genphy_c45_pma_baset1_read_abilities(struct phy_device *phydev) in genphy_c45_pma_baset1_read_abilities() argument
964 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_PMD_BT1); in genphy_c45_pma_baset1_read_abilities()
969 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
973 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
977 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
980 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_STAT); in genphy_c45_pma_baset1_read_abilities()
985 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
994 * @phydev: target phy_device struct
999 int genphy_c45_pma_read_ext_abilities(struct phy_device *phydev) in genphy_c45_pma_read_ext_abilities() argument
1003 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_EXTABLE); in genphy_c45_pma_read_ext_abilities()
1008 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1011 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1014 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1017 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1020 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1023 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1027 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1030 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1034 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1037 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1041 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, in genphy_c45_pma_read_ext_abilities()
1047 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1051 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1056 val = genphy_c45_pma_baset1_read_abilities(phydev); in genphy_c45_pma_read_ext_abilities()
1067 * @phydev: target phy_device struct
1076 int genphy_c45_pma_read_abilities(struct phy_device *phydev) in genphy_c45_pma_read_abilities() argument
1080 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); in genphy_c45_pma_read_abilities()
1081 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_pma_read_abilities()
1082 val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_STAT1); in genphy_c45_pma_read_abilities()
1088 phydev->supported); in genphy_c45_pma_read_abilities()
1091 val = phy_read_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_STAT2); in genphy_c45_pma_read_abilities()
1096 phydev->supported, in genphy_c45_pma_read_abilities()
1100 phydev->supported, in genphy_c45_pma_read_abilities()
1104 phydev->supported, in genphy_c45_pma_read_abilities()
1108 val = genphy_c45_pma_read_ext_abilities(phydev); in genphy_c45_pma_read_abilities()
1116 genphy_c45_read_eee_abilities(phydev); in genphy_c45_pma_read_abilities()
1128 int genphy_c45_baset1_read_status(struct phy_device *phydev) in genphy_c45_baset1_read_status() argument
1133 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_baset1_read_status()
1134 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_baset1_read_status()
1136 ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_L); in genphy_c45_baset1_read_status()
1140 cfg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_T1_ADV_M); in genphy_c45_baset1_read_status()
1146 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_baset1_read_status()
1148 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_baset1_read_status()
1151 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; in genphy_c45_baset1_read_status()
1153 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; in genphy_c45_baset1_read_status()
1162 * @phydev: target phy_device struct
1166 int genphy_c45_read_status(struct phy_device *phydev) in genphy_c45_read_status() argument
1170 ret = genphy_c45_read_link(phydev); in genphy_c45_read_status()
1174 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_status()
1175 phydev->duplex = DUPLEX_UNKNOWN; in genphy_c45_read_status()
1176 phydev->pause = 0; in genphy_c45_read_status()
1177 phydev->asym_pause = 0; in genphy_c45_read_status()
1179 if (phydev->autoneg == AUTONEG_ENABLE) { in genphy_c45_read_status()
1180 ret = genphy_c45_read_lpa(phydev); in genphy_c45_read_status()
1184 if (genphy_c45_baset1_able(phydev)) { in genphy_c45_read_status()
1185 ret = genphy_c45_baset1_read_status(phydev); in genphy_c45_read_status()
1190 phy_resolve_aneg_linkmode(phydev); in genphy_c45_read_status()
1192 ret = genphy_c45_read_pma(phydev); in genphy_c45_read_status()
1201 * @phydev: target phy_device struct
1207 int genphy_c45_config_aneg(struct phy_device *phydev) in genphy_c45_config_aneg() argument
1212 if (phydev->autoneg == AUTONEG_DISABLE) in genphy_c45_config_aneg()
1213 return genphy_c45_pma_setup_forced(phydev); in genphy_c45_config_aneg()
1215 ret = genphy_c45_an_config_aneg(phydev); in genphy_c45_config_aneg()
1221 return genphy_c45_check_and_restart_aneg(phydev, changed); in genphy_c45_config_aneg()
1227 int gen10g_config_aneg(struct phy_device *phydev) in gen10g_config_aneg() argument
1233 int genphy_c45_loopback(struct phy_device *phydev, bool enable) in genphy_c45_loopback() argument
1235 return phy_modify_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL1, in genphy_c45_loopback()
1243 * @phydev: target phy_device struct
1251 int genphy_c45_fast_retrain(struct phy_device *phydev, bool enable) in genphy_c45_fast_retrain() argument
1256 return phy_clear_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
1259 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { in genphy_c45_fast_retrain()
1260 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL, in genphy_c45_fast_retrain()
1265 ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN, MDIO_AN_CTRL2, in genphy_c45_fast_retrain()
1271 return phy_set_bits_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_PMA_10GBR_FSRT_CSR, in genphy_c45_fast_retrain()
1278 * @phydev: target phy_device struct
1285 int genphy_c45_plca_get_cfg(struct phy_device *phydev, in genphy_c45_plca_get_cfg() argument
1290 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_IDVER); in genphy_c45_plca_get_cfg()
1299 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL0); in genphy_c45_plca_get_cfg()
1305 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_CTRL1); in genphy_c45_plca_get_cfg()
1312 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_TOTMR); in genphy_c45_plca_get_cfg()
1318 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_BURST); in genphy_c45_plca_get_cfg()
1331 * @phydev: target phy_device struct
1339 int genphy_c45_plca_set_cfg(struct phy_device *phydev, in genphy_c45_plca_set_cfg() argument
1351 ret = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1366 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1383 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1391 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1406 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1423 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1432 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, in genphy_c45_plca_set_cfg()
1446 * @phydev: target phy_device struct
1453 int genphy_c45_plca_get_status(struct phy_device *phydev, in genphy_c45_plca_get_status() argument
1458 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, MDIO_OATC14_PLCA_STATUS); in genphy_c45_plca_get_status()
1469 * @phydev: target phy_device struct
1477 int genphy_c45_eee_is_active(struct phy_device *phydev, unsigned long *adv, in genphy_c45_eee_is_active() argument
1486 ret = genphy_c45_read_eee_adv(phydev, tmp_adv); in genphy_c45_eee_is_active()
1490 ret = genphy_c45_read_eee_lpa(phydev, tmp_lp); in genphy_c45_eee_is_active()
1497 eee_active = phy_check_valid(phydev->speed, phydev->duplex, in genphy_c45_eee_is_active()
1515 * @phydev: target phy_device struct
1521 int genphy_c45_ethtool_get_eee(struct phy_device *phydev, in genphy_c45_ethtool_get_eee() argument
1529 ret = genphy_c45_eee_is_active(phydev, adv, lp, &is_enabled); in genphy_c45_ethtool_get_eee()
1535 linkmode_copy(data->supported, phydev->supported_eee); in genphy_c45_ethtool_get_eee()
1545 * @phydev: target phy_device struct
1556 int genphy_c45_ethtool_set_eee(struct phy_device *phydev, in genphy_c45_ethtool_set_eee() argument
1567 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) { in genphy_c45_ethtool_set_eee()
1568 phydev_warn(phydev, "At least some EEE link modes are not supported.\n"); in genphy_c45_ethtool_set_eee()
1572 adv = phydev->supported_eee; in genphy_c45_ethtool_set_eee()
1575 linkmode_copy(phydev->advertising_eee, adv); in genphy_c45_ethtool_set_eee()
1578 phydev->eee_enabled = data->eee_enabled; in genphy_c45_ethtool_set_eee()
1580 ret = genphy_c45_an_config_eee_aneg(phydev); in genphy_c45_ethtool_set_eee()
1582 ret = phy_restart_aneg(phydev); in genphy_c45_ethtool_set_eee()