Lines Matching full:phydev
290 static int nxp_c45_macsec_write(struct phy_device *phydev, u16 addr, u32 value) in nxp_c45_macsec_write() argument
298 phydev_dbg(phydev, "write addr 0x%x value 0x%x\n", addr, value); in nxp_c45_macsec_write()
301 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue); in nxp_c45_macsec_write()
307 ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, laddr, lvalue); in nxp_c45_macsec_write()
312 static int nxp_c45_macsec_read(struct phy_device *phydev, u16 addr, u32 *value) in nxp_c45_macsec_read() argument
321 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr); in nxp_c45_macsec_read()
327 ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, laddr); in nxp_c45_macsec_read()
334 phydev_dbg(phydev, "read addr 0x%x value 0x%x\n", addr, *value); in nxp_c45_macsec_read()
339 static void nxp_c45_macsec_read32_64(struct phy_device *phydev, u16 addr, in nxp_c45_macsec_read32_64() argument
344 nxp_c45_macsec_read(phydev, addr, &lvalue); in nxp_c45_macsec_read32_64()
348 static void nxp_c45_macsec_read64(struct phy_device *phydev, u16 addr, in nxp_c45_macsec_read64() argument
353 nxp_c45_macsec_read(phydev, addr, &lvalue); in nxp_c45_macsec_read64()
355 nxp_c45_macsec_read(phydev, addr + 4, &lvalue); in nxp_c45_macsec_read64()
359 static void nxp_c45_secy_irq_en(struct phy_device *phydev, in nxp_c45_secy_irq_en() argument
364 nxp_c45_macsec_read(phydev, MACSEC_EVER, ®); in nxp_c45_secy_irq_en()
369 nxp_c45_macsec_write(phydev, MACSEC_EVER, reg); in nxp_c45_secy_irq_en()
466 static void nxp_c45_sa_set_pn(struct phy_device *phydev, in nxp_c45_sa_set_pn() argument
474 nxp_c45_macsec_write(phydev, sa_regs->npn, npn.lower); in nxp_c45_sa_set_pn()
475 nxp_c45_macsec_write(phydev, sa_regs->xnpn, npn.upper); in nxp_c45_sa_set_pn()
484 nxp_c45_macsec_write(phydev, sa_regs->lnpn, lnpn.lower); in nxp_c45_sa_set_pn()
485 nxp_c45_macsec_write(phydev, sa_regs->lxnpn, lnpn.upper); in nxp_c45_sa_set_pn()
492 struct phy_device *phydev = ctx->phydev; in nxp_c45_sa_set_key() local
503 nxp_c45_macsec_write(phydev, reg, value); in nxp_c45_sa_set_key()
510 nxp_c45_macsec_write(phydev, reg, value); in nxp_c45_sa_set_key()
514 nxp_c45_macsec_write(phydev, sa_regs->ssci, value); in nxp_c45_sa_set_key()
517 nxp_c45_macsec_write(phydev, sa_regs->cs, MACSEC_SA_CS_A); in nxp_c45_sa_set_key()
520 static void nxp_c45_rx_sa_clear_stats(struct phy_device *phydev, in nxp_c45_rx_sa_clear_stats() argument
523 nxp_c45_macsec_write(phydev, sa->regs->ipis, 0); in nxp_c45_rx_sa_clear_stats()
524 nxp_c45_macsec_write(phydev, sa->regs->ipnvs, 0); in nxp_c45_rx_sa_clear_stats()
525 nxp_c45_macsec_write(phydev, sa->regs->ipos, 0); in nxp_c45_rx_sa_clear_stats()
527 nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + sa->an * 4, 0); in nxp_c45_rx_sa_clear_stats()
528 nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + sa->an * 4, 0); in nxp_c45_rx_sa_clear_stats()
531 static void nxp_c45_rx_sa_read_stats(struct phy_device *phydev, in nxp_c45_rx_sa_read_stats() argument
535 nxp_c45_macsec_read(phydev, sa->regs->ipis, &stats->InPktsInvalid); in nxp_c45_rx_sa_read_stats()
536 nxp_c45_macsec_read(phydev, sa->regs->ipnvs, &stats->InPktsNotValid); in nxp_c45_rx_sa_read_stats()
537 nxp_c45_macsec_read(phydev, sa->regs->ipos, &stats->InPktsOK); in nxp_c45_rx_sa_read_stats()
540 static void nxp_c45_tx_sa_clear_stats(struct phy_device *phydev, in nxp_c45_tx_sa_clear_stats() argument
543 nxp_c45_macsec_write(phydev, sa->regs->opps, 0); in nxp_c45_tx_sa_clear_stats()
544 nxp_c45_macsec_write(phydev, sa->regs->opes, 0); in nxp_c45_tx_sa_clear_stats()
547 static void nxp_c45_tx_sa_read_stats(struct phy_device *phydev, in nxp_c45_tx_sa_read_stats() argument
551 nxp_c45_macsec_read(phydev, sa->regs->opps, &stats->OutPktsProtected); in nxp_c45_tx_sa_read_stats()
552 nxp_c45_macsec_read(phydev, sa->regs->opes, &stats->OutPktsEncrypted); in nxp_c45_tx_sa_read_stats()
555 static void nxp_c45_rx_sa_update(struct phy_device *phydev, in nxp_c45_rx_sa_update() argument
563 nxp_c45_macsec_write(phydev, sa_regs->cs, cfg); in nxp_c45_rx_sa_update()
566 static void nxp_c45_tx_sa_update(struct phy_device *phydev, in nxp_c45_tx_sa_update() argument
571 nxp_c45_macsec_read(phydev, MACSEC_TXSC_CFG, &cfg); in nxp_c45_tx_sa_update()
586 nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg); in nxp_c45_tx_sa_update()
589 static void nxp_c45_set_sci(struct phy_device *phydev, u16 sci_base_addr, in nxp_c45_set_sci() argument
594 nxp_c45_macsec_write(phydev, sci_base_addr, lsci >> 32); in nxp_c45_set_sci()
595 nxp_c45_macsec_write(phydev, sci_base_addr + 4, lsci); in nxp_c45_set_sci()
605 static void nxp_c45_select_secy(struct phy_device *phydev, u8 id) in nxp_c45_select_secy() argument
607 nxp_c45_macsec_write(phydev, MACSEC_RXSCA, id); in nxp_c45_select_secy()
608 nxp_c45_macsec_write(phydev, MACSEC_RXSCKA, id); in nxp_c45_select_secy()
609 nxp_c45_macsec_write(phydev, MACSEC_TXSCA, id); in nxp_c45_select_secy()
610 nxp_c45_macsec_write(phydev, MACSEC_TXSCKA, id); in nxp_c45_select_secy()
654 struct nxp_c45_phy *priv = ctx->phydev->priv; in nxp_c45_mac_addr_free()
669 static void nxp_c45_tx_sc_en_flt(struct phy_device *phydev, int secy_id, in nxp_c45_tx_sc_en_flt() argument
675 nxp_c45_macsec_read(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), ®); in nxp_c45_tx_sc_en_flt()
680 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg); in nxp_c45_tx_sc_en_flt()
683 static void nxp_c45_tx_sc_set_flt(struct phy_device *phydev, in nxp_c45_tx_sc_set_flt() argument
691 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_DA_SA(tx_flt_base), reg); in nxp_c45_tx_sc_set_flt()
695 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_SA(tx_flt_base), reg); in nxp_c45_tx_sc_set_flt()
696 nxp_c45_macsec_read(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), ®); in nxp_c45_tx_sc_set_flt()
699 nxp_c45_macsec_write(phydev, TX_SC_FLT_MAC_CFG(tx_flt_base), reg); in nxp_c45_tx_sc_set_flt()
702 static void nxp_c45_tx_sc_update(struct phy_device *phydev, in nxp_c45_tx_sc_update() argument
707 nxp_c45_macsec_read(phydev, MACSEC_TXSC_CFG, &cfg); in nxp_c45_tx_sc_update()
709 phydev_dbg(phydev, "XPN %s\n", phy_secy->secy->xpn ? "on" : "off"); in nxp_c45_tx_sc_update()
715 phydev_dbg(phydev, "key len %u\n", phy_secy->secy->key_len); in nxp_c45_tx_sc_update()
721 phydev_dbg(phydev, "encryption %s\n", in nxp_c45_tx_sc_update()
728 phydev_dbg(phydev, "protect frames %s\n", in nxp_c45_tx_sc_update()
735 phydev_dbg(phydev, "send sci %s\n", in nxp_c45_tx_sc_update()
742 phydev_dbg(phydev, "end station %s\n", in nxp_c45_tx_sc_update()
749 phydev_dbg(phydev, "scb %s\n", in nxp_c45_tx_sc_update()
756 nxp_c45_macsec_write(phydev, MACSEC_TXSC_CFG, cfg); in nxp_c45_tx_sc_update()
759 static void nxp_c45_tx_sc_clear_stats(struct phy_device *phydev, in nxp_c45_tx_sc_clear_stats() argument
766 nxp_c45_tx_sa_clear_stats(phydev, pos); in nxp_c45_tx_sc_clear_stats()
768 nxp_c45_macsec_write(phydev, MACSEC_OPUS, 0); in nxp_c45_tx_sc_clear_stats()
769 nxp_c45_macsec_write(phydev, MACSEC_OPTLS, 0); in nxp_c45_tx_sc_clear_stats()
770 nxp_c45_macsec_write(phydev, MACSEC_OOP1HS, 0); in nxp_c45_tx_sc_clear_stats()
771 nxp_c45_macsec_write(phydev, MACSEC_OOP2HS, 0); in nxp_c45_tx_sc_clear_stats()
772 nxp_c45_macsec_write(phydev, MACSEC_OOE1HS, 0); in nxp_c45_tx_sc_clear_stats()
773 nxp_c45_macsec_write(phydev, MACSEC_OOE2HS, 0); in nxp_c45_tx_sc_clear_stats()
776 static void nxp_c45_set_rx_sc0_impl(struct phy_device *phydev, in nxp_c45_set_rx_sc0_impl() argument
781 nxp_c45_macsec_read(phydev, MACSEC_CFG, ®); in nxp_c45_set_rx_sc0_impl()
786 nxp_c45_macsec_write(phydev, MACSEC_CFG, reg); in nxp_c45_set_rx_sc0_impl()
800 static void nxp_c45_rx_sc_en(struct phy_device *phydev, in nxp_c45_rx_sc_en() argument
805 nxp_c45_macsec_read(phydev, MACSEC_RXSC_CFG, ®); in nxp_c45_rx_sc_en()
810 nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, reg); in nxp_c45_rx_sc_en()
813 static void nxp_c45_rx_sc_update(struct phy_device *phydev, in nxp_c45_rx_sc_update() argument
817 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_rx_sc_update()
820 nxp_c45_macsec_read(phydev, MACSEC_RXSC_CFG, &cfg); in nxp_c45_rx_sc_update()
824 phydev_dbg(phydev, "validate frames %u\n", in nxp_c45_rx_sc_update()
826 phydev_dbg(phydev, "replay_protect %s window %u\n", in nxp_c45_rx_sc_update()
831 nxp_c45_macsec_write(phydev, MACSEC_RPW, in nxp_c45_rx_sc_update()
837 phydev_dbg(phydev, "rx_sc->active %s\n", in nxp_c45_rx_sc_update()
845 phydev_dbg(phydev, "key len %u\n", phy_secy->secy->key_len); in nxp_c45_rx_sc_update()
851 phydev_dbg(phydev, "XPN %s\n", phy_secy->secy->xpn ? "on" : "off"); in nxp_c45_rx_sc_update()
857 nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, cfg); in nxp_c45_rx_sc_update()
860 static void nxp_c45_rx_sc_clear_stats(struct phy_device *phydev, in nxp_c45_rx_sc_clear_stats() argument
868 nxp_c45_rx_sa_clear_stats(phydev, pos); in nxp_c45_rx_sc_clear_stats()
870 nxp_c45_macsec_write(phydev, MACSEC_INOD1HS, 0); in nxp_c45_rx_sc_clear_stats()
871 nxp_c45_macsec_write(phydev, MACSEC_INOD2HS, 0); in nxp_c45_rx_sc_clear_stats()
873 nxp_c45_macsec_write(phydev, MACSEC_INOV1HS, 0); in nxp_c45_rx_sc_clear_stats()
874 nxp_c45_macsec_write(phydev, MACSEC_INOV2HS, 0); in nxp_c45_rx_sc_clear_stats()
876 nxp_c45_macsec_write(phydev, MACSEC_RXSCIPDS, 0); in nxp_c45_rx_sc_clear_stats()
877 nxp_c45_macsec_write(phydev, MACSEC_RXSCIPLS, 0); in nxp_c45_rx_sc_clear_stats()
878 nxp_c45_macsec_write(phydev, MACSEC_RXSCIPUS, 0); in nxp_c45_rx_sc_clear_stats()
881 nxp_c45_macsec_write(phydev, MACSEC_RXAN0INUSS + i * 4, 0); in nxp_c45_rx_sc_clear_stats()
882 nxp_c45_macsec_write(phydev, MACSEC_RXAN0IPUSS + i * 4, 0); in nxp_c45_rx_sc_clear_stats()
886 static void nxp_c45_rx_sc_del(struct phy_device *phydev, in nxp_c45_rx_sc_del() argument
891 nxp_c45_macsec_write(phydev, MACSEC_RXSC_CFG, 0); in nxp_c45_rx_sc_del()
892 nxp_c45_macsec_write(phydev, MACSEC_RPW, 0); in nxp_c45_rx_sc_del()
893 nxp_c45_set_sci(phydev, MACSEC_RXSC_SCI_1H, 0); in nxp_c45_rx_sc_del()
895 nxp_c45_rx_sc_clear_stats(phydev, phy_secy); in nxp_c45_rx_sc_del()
899 nxp_c45_rx_sa_update(phydev, pos, false); in nxp_c45_rx_sc_del()
905 static void nxp_c45_clear_global_stats(struct phy_device *phydev) in nxp_c45_clear_global_stats() argument
907 nxp_c45_macsec_write(phydev, MACSEC_INPBTS, 0); in nxp_c45_clear_global_stats()
908 nxp_c45_macsec_write(phydev, MACSEC_INPWTS, 0); in nxp_c45_clear_global_stats()
909 nxp_c45_macsec_write(phydev, MACSEC_IPSNFS, 0); in nxp_c45_clear_global_stats()
912 static void nxp_c45_macsec_en(struct phy_device *phydev, bool en) in nxp_c45_macsec_en() argument
916 nxp_c45_macsec_read(phydev, MACSEC_CFG, ®); in nxp_c45_macsec_en()
921 nxp_c45_macsec_write(phydev, MACSEC_CFG, reg); in nxp_c45_macsec_en()
926 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_dev_open() local
927 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_dev_open()
935 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_dev_open()
937 nxp_c45_tx_sc_en_flt(phydev, phy_secy->secy_id, true); in nxp_c45_mdo_dev_open()
938 nxp_c45_set_rx_sc0_impl(phydev, phy_secy->rx_sc0_impl); in nxp_c45_mdo_dev_open()
940 nxp_c45_rx_sc_en(phydev, phy_secy->rx_sc, true); in nxp_c45_mdo_dev_open()
944 nxp_c45_macsec_en(phydev, true); in nxp_c45_mdo_dev_open()
953 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_dev_stop() local
954 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_dev_stop()
962 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_dev_stop()
964 nxp_c45_tx_sc_en_flt(phydev, phy_secy->secy_id, false); in nxp_c45_mdo_dev_stop()
966 nxp_c45_rx_sc_en(phydev, phy_secy->rx_sc, false); in nxp_c45_mdo_dev_stop()
967 nxp_c45_set_rx_sc0_impl(phydev, false); in nxp_c45_mdo_dev_stop()
972 nxp_c45_macsec_en(phydev, false); in nxp_c45_mdo_dev_stop()
979 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_add_secy() local
980 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_add_secy()
985 phydev_dbg(phydev, "add SecY SCI %016llx\n", in nxp_c45_mdo_add_secy()
1017 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_add_secy()
1018 nxp_c45_set_sci(phydev, MACSEC_TXSC_SCI_1H, ctx->secy->sci); in nxp_c45_mdo_add_secy()
1019 nxp_c45_tx_sc_set_flt(phydev, phy_secy); in nxp_c45_mdo_add_secy()
1020 nxp_c45_tx_sc_update(phydev, phy_secy); in nxp_c45_mdo_add_secy()
1021 if (phy_interrupt_is_valid(phydev)) in nxp_c45_mdo_add_secy()
1022 nxp_c45_secy_irq_en(phydev, phy_secy, true); in nxp_c45_mdo_add_secy()
1047 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_upd_secy() local
1048 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_upd_secy()
1053 phydev_dbg(phydev, "update SecY SCI %016llx\n", in nxp_c45_mdo_upd_secy()
1071 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_upd_secy()
1072 nxp_c45_tx_sc_set_flt(phydev, phy_secy); in nxp_c45_mdo_upd_secy()
1073 nxp_c45_tx_sc_update(phydev, phy_secy); in nxp_c45_mdo_upd_secy()
1075 nxp_c45_tx_sa_update(phydev, &next_sa, ctx->secy->operational); in nxp_c45_mdo_upd_secy()
1077 nxp_c45_set_rx_sc0_impl(phydev, phy_secy->rx_sc0_impl); in nxp_c45_mdo_upd_secy()
1079 nxp_c45_rx_sc_update(phydev, phy_secy); in nxp_c45_mdo_upd_secy()
1087 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_del_secy() local
1088 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_del_secy()
1092 phydev_dbg(phydev, "delete SecY SCI %016llx\n", in nxp_c45_mdo_del_secy()
1098 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_del_secy()
1102 nxp_c45_tx_sa_update(phydev, &next_sa, false); in nxp_c45_mdo_del_secy()
1103 nxp_c45_tx_sc_clear_stats(phydev, phy_secy); in nxp_c45_mdo_del_secy()
1105 nxp_c45_rx_sc_del(phydev, phy_secy); in nxp_c45_mdo_del_secy()
1108 if (phy_interrupt_is_valid(phydev)) in nxp_c45_mdo_del_secy()
1109 nxp_c45_secy_irq_en(phydev, phy_secy, false); in nxp_c45_mdo_del_secy()
1115 nxp_c45_clear_global_stats(phydev); in nxp_c45_mdo_del_secy()
1122 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_add_rxsc() local
1123 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_add_rxsc()
1126 phydev_dbg(phydev, "add RX SC SCI %016llx %s\n", in nxp_c45_mdo_add_rxsc()
1143 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_add_rxsc()
1144 nxp_c45_set_sci(phydev, MACSEC_RXSC_SCI_1H, ctx->rx_sc->sci); in nxp_c45_mdo_add_rxsc()
1145 nxp_c45_rx_sc_update(phydev, phy_secy); in nxp_c45_mdo_add_rxsc()
1152 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_upd_rxsc() local
1153 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_upd_rxsc()
1156 phydev_dbg(phydev, "update RX SC SCI %016llx %s\n", in nxp_c45_mdo_upd_rxsc()
1164 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_upd_rxsc()
1165 nxp_c45_rx_sc_update(phydev, phy_secy); in nxp_c45_mdo_upd_rxsc()
1172 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_del_rxsc() local
1173 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_del_rxsc()
1176 phydev_dbg(phydev, "delete RX SC SCI %016llx %s\n", in nxp_c45_mdo_del_rxsc()
1184 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_del_rxsc()
1185 nxp_c45_rx_sc_del(phydev, phy_secy); in nxp_c45_mdo_del_rxsc()
1194 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_add_rxsa() local
1195 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_add_rxsa()
1200 phydev_dbg(phydev, "add RX SA %u %s to RX SC SCI %016llx\n", in nxp_c45_mdo_add_rxsa()
1212 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_add_rxsa()
1213 nxp_c45_sa_set_pn(phydev, sa, rx_sa->next_pn, in nxp_c45_mdo_add_rxsa()
1216 nxp_c45_rx_sa_update(phydev, sa, rx_sa->active); in nxp_c45_mdo_add_rxsa()
1224 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_upd_rxsa() local
1225 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_upd_rxsa()
1230 phydev_dbg(phydev, "update RX SA %u %s to RX SC SCI %016llx\n", in nxp_c45_mdo_upd_rxsa()
1242 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_upd_rxsa()
1244 nxp_c45_sa_set_pn(phydev, sa, rx_sa->next_pn, in nxp_c45_mdo_upd_rxsa()
1246 nxp_c45_rx_sa_update(phydev, sa, rx_sa->active); in nxp_c45_mdo_upd_rxsa()
1254 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_del_rxsa() local
1255 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_del_rxsa()
1260 phydev_dbg(phydev, "delete RX SA %u %s to RX SC SCI %016llx\n", in nxp_c45_mdo_del_rxsa()
1272 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_del_rxsa()
1273 nxp_c45_rx_sa_update(phydev, sa, false); in nxp_c45_mdo_del_rxsa()
1274 nxp_c45_rx_sa_clear_stats(phydev, sa); in nxp_c45_mdo_del_rxsa()
1284 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_add_txsa() local
1285 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_add_txsa()
1290 phydev_dbg(phydev, "add TX SA %u %s to TX SC %016llx\n", in nxp_c45_mdo_add_txsa()
1302 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_add_txsa()
1303 nxp_c45_sa_set_pn(phydev, sa, tx_sa->next_pn, 0); in nxp_c45_mdo_add_txsa()
1306 nxp_c45_tx_sa_update(phydev, sa, tx_sa->active); in nxp_c45_mdo_add_txsa()
1314 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_upd_txsa() local
1315 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_upd_txsa()
1320 phydev_dbg(phydev, "update TX SA %u %s to TX SC %016llx\n", in nxp_c45_mdo_upd_txsa()
1332 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_upd_txsa()
1334 nxp_c45_sa_set_pn(phydev, sa, tx_sa->next_pn, 0); in nxp_c45_mdo_upd_txsa()
1336 nxp_c45_tx_sa_update(phydev, sa, tx_sa->active); in nxp_c45_mdo_upd_txsa()
1343 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_del_txsa() local
1344 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_del_txsa()
1349 phydev_dbg(phydev, "delete TX SA %u %s to TX SC %016llx\n", in nxp_c45_mdo_del_txsa()
1361 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_del_txsa()
1363 nxp_c45_tx_sa_update(phydev, sa, false); in nxp_c45_mdo_del_txsa()
1364 nxp_c45_tx_sa_clear_stats(phydev, sa); in nxp_c45_mdo_del_txsa()
1373 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_get_dev_stats() local
1374 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_get_dev_stats()
1383 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_get_dev_stats()
1385 nxp_c45_macsec_read32_64(phydev, MACSEC_OPUS, in nxp_c45_mdo_get_dev_stats()
1387 nxp_c45_macsec_read32_64(phydev, MACSEC_OPTLS, in nxp_c45_mdo_get_dev_stats()
1389 nxp_c45_macsec_read32_64(phydev, MACSEC_INPBTS, in nxp_c45_mdo_get_dev_stats()
1393 nxp_c45_macsec_read32_64(phydev, MACSEC_INPWTS, in nxp_c45_mdo_get_dev_stats()
1396 nxp_c45_macsec_read32_64(phydev, MACSEC_INPWTS, in nxp_c45_mdo_get_dev_stats()
1400 nxp_c45_macsec_read32_64(phydev, MACSEC_IPSNFS, in nxp_c45_mdo_get_dev_stats()
1403 nxp_c45_macsec_read32_64(phydev, MACSEC_IPSNFS, in nxp_c45_mdo_get_dev_stats()
1414 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_get_tx_sc_stats() local
1415 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_get_tx_sc_stats()
1426 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_get_tx_sc_stats()
1428 nxp_c45_macsec_read64(phydev, MACSEC_OOE1HS, in nxp_c45_mdo_get_tx_sc_stats()
1430 nxp_c45_macsec_read64(phydev, MACSEC_OOP1HS, in nxp_c45_mdo_get_tx_sc_stats()
1437 nxp_c45_tx_sa_read_stats(phydev, pos, &tx_sa_stats); in nxp_c45_mdo_get_tx_sc_stats()
1448 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_get_tx_sa_stats() local
1449 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_get_tx_sa_stats()
1464 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_get_tx_sa_stats()
1465 nxp_c45_tx_sa_read_stats(phydev, sa, stats); in nxp_c45_mdo_get_tx_sa_stats()
1472 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_get_rx_sc_stats() local
1473 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_get_rx_sc_stats()
1489 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_get_rx_sc_stats()
1496 nxp_c45_rx_sa_read_stats(phydev, pos, &rx_sa_stats); in nxp_c45_mdo_get_rx_sc_stats()
1504 nxp_c45_macsec_read(phydev, MACSEC_RXAN0INUSS + i * 4, ®); in nxp_c45_mdo_get_rx_sc_stats()
1506 nxp_c45_macsec_read(phydev, MACSEC_RXAN0IPUSS + i * 4, ®); in nxp_c45_mdo_get_rx_sc_stats()
1510 nxp_c45_macsec_read64(phydev, MACSEC_INOD1HS, in nxp_c45_mdo_get_rx_sc_stats()
1512 nxp_c45_macsec_read64(phydev, MACSEC_INOV1HS, in nxp_c45_mdo_get_rx_sc_stats()
1515 nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPDS, in nxp_c45_mdo_get_rx_sc_stats()
1517 nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPLS, in nxp_c45_mdo_get_rx_sc_stats()
1519 nxp_c45_macsec_read32_64(phydev, MACSEC_RXSCIPUS, in nxp_c45_mdo_get_rx_sc_stats()
1527 struct phy_device *phydev = ctx->phydev; in nxp_c45_mdo_get_rx_sa_stats() local
1528 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_mdo_get_rx_sa_stats()
1543 nxp_c45_select_secy(phydev, phy_secy->secy_id); in nxp_c45_mdo_get_rx_sa_stats()
1545 nxp_c45_rx_sa_read_stats(phydev, sa, stats); in nxp_c45_mdo_get_rx_sa_stats()
1546 nxp_c45_macsec_read(phydev, MACSEC_RXAN0INUSS + an * 4, in nxp_c45_mdo_get_rx_sa_stats()
1548 nxp_c45_macsec_read(phydev, MACSEC_RXAN0IPUSS + an * 4, in nxp_c45_mdo_get_rx_sa_stats()
1561 static int nxp_c45_mdo_insert_tx_tag(struct phy_device *phydev, in nxp_c45_mdo_insert_tx_tag() argument
1604 int nxp_c45_macsec_config_init(struct phy_device *phydev) in nxp_c45_macsec_config_init() argument
1606 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_macsec_config_init()
1612 ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_PORT_FUNC_ENABLES, in nxp_c45_macsec_config_init()
1617 ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_CONFIG_EN | in nxp_c45_macsec_config_init()
1622 ret = nxp_c45_macsec_write(phydev, ADPTR_TX_TAG_CNTRL, in nxp_c45_macsec_config_init()
1627 ret = nxp_c45_macsec_write(phydev, ADPTR_CNTRL, ADPTR_CNTRL_ADPTR_EN); in nxp_c45_macsec_config_init()
1631 ret = nxp_c45_macsec_write(phydev, MACSEC_TPNET, PN_WRAP_THRESHOLD); in nxp_c45_macsec_config_init()
1636 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0D2, ETH_P_PAE); in nxp_c45_macsec_config_init()
1640 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M1, MACSEC_OVP); in nxp_c45_macsec_config_init()
1644 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0M2, ETYPE_MASK); in nxp_c45_macsec_config_init()
1648 ret = nxp_c45_macsec_write(phydev, MACSEC_UPFR0R, MACSEC_UPFR_EN); in nxp_c45_macsec_config_init()
1653 int nxp_c45_macsec_probe(struct phy_device *phydev) in nxp_c45_macsec_probe() argument
1655 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_macsec_probe()
1656 struct device *dev = &phydev->mdio.dev; in nxp_c45_macsec_probe()
1663 phydev->macsec_ops = &nxp_c45_macsec_ops; in nxp_c45_macsec_probe()
1668 void nxp_c45_macsec_remove(struct phy_device *phydev) in nxp_c45_macsec_remove() argument
1670 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_macsec_remove()
1679 nxp_c45_macsec_en(phydev, false); in nxp_c45_macsec_remove()
1688 void nxp_c45_handle_macsec_interrupt(struct phy_device *phydev, in nxp_c45_handle_macsec_interrupt() argument
1691 struct nxp_c45_phy *priv = phydev->priv; in nxp_c45_handle_macsec_interrupt()
1702 nxp_c45_macsec_read(phydev, MACSEC_EVR, ®); in nxp_c45_handle_macsec_interrupt()
1715 phydev_dbg(phydev, "pn_wrapped: TX SC %d, encoding_sa %u\n", in nxp_c45_handle_macsec_interrupt()
1725 nxp_c45_macsec_write(phydev, MACSEC_EVR, in nxp_c45_handle_macsec_interrupt()